Semiconductor memories were introduced in the late 1960s. Increased storage density, speed, and reduced cost were their main advantages. In the basic form, semiconductor random access memory (RAM) information is stored in a cell that is replicated for each bit. RAMs are broadly classified as nonvolatile, such as flash memories, or volatile, such as static RAM (SRAM) and dynamic RAM (DRAM). No single memory satisfies all system needs. However, the highest density and lowest cost per bit of DRAMs have given them a prominent role, whether in mainframe computers and PCs, telecommunications, or so many other high-tech applications such as avionics and space. Hence, during the last four decades the number of DRAM bits/chip has increased four times every three years and the cost/bit ratio has declined nearly by the same order. Communication systems, graphic subsystems, and the extremely fast expanding mobile industry became catalysts for the rapid growth in the demand for large-volume memories. The present work is an attempt to describe the technological developments that allowed the design and optimization of high-density and cost-efficient DRAMs.
The one-device DRAM cell was conceptualized and then manufactured at the 1 Kbit level in planar form. Rapid advancements have presently enabled the one-device cell as three-dimensional entity with 2 Gbit DRAMs (DDR3) firmly established in the market and 4 Gbit DRAMs on the threshold. This book tries to look into the breakthroughs that contributed to the fast evolution of DRAMs.
A DRAM cell consists of a storage capacitor and a select transistor with cells arranged in arrays of rows (word lines or WLs) and columns (bit lines or BLs). For higher density DRAMs, multiple subarrays replace a single large array to shorten the WLs and the BLs and thereby make the cell faster. Once a transistor selects a cell, it can be read or written. Storage capacitor changes bit line potential and a sense amplifier detects this small signal change. With continuous decrease in cell size and working voltage, storage capacitance value must be maintained above a critical value and a large amount of research is going on to maintain the critical value of the charge on it without increasing (rather decreasing) its projected chip area. Advancements in the sensing techniques for this critical charge and hence, design of sense amplifiers, assume great importance. At the same time development of storage capacitance with thinly layered high dielectric constant materials compatible with other materials gained extreme significance.
The reading process of DRAM disturbs stored information; hence, it is to be restored after each read. In addition, cell capacitor charge continuously leaks and thus needs continuous replenishment, requiring additional power to retain the correct data. Different types of leakages, and the circuits and technologies employed as the remedial measures, have become extremely important, especially with increasing DRAM density.
The topic of semiconductor memories does find a regular place in undergraduate technology curricula and elective courses are given at institutes at the graduate level; research work has been limited mainly to the big industries involved in DRAM manufacture. For a large number of people to be involved, which is essential for rapid developments, technological advancement needs to be presented to generate wider interest. It is a fair assumption that more books must be made available as references and in textbook form on the topic of semiconductor memory to make it popular as a separate subject in academic circles. Only a few books are available on semiconductor memories in general and fewer on DRAMs. It is expected that the present work will be a worthwhile addition for enhancing interest in the study of semiconductor memories. It is also likely to be useful to people in semiconductor manufacturing and the electronic industry as expert groups involved in a different nature of activities might like to look for related topics. Academicians and researchers interested in state-of-the-art work on semiconductor memories may also find it useful as parts of the book can be included in a graduate-level course.
Although a great amount of effort and attention has been paid in the preparation of the manuscript, the book may still have some shortcomings and mistakes. The author would greatly appreciate any correction or suggestion, whether with regard to the method of presentation, technical flaws, or content.
The book has been divided into eight chapters. The first chapter includes basic construction, working and simple modes of operation of DRAM, and its evolution from the six-transistor SRAM. Some important developments of the 1970s such as the introduction of sense amplifiers in DRAMs and a discussion on open and folded bit line structures are added. The rest of the chapter is devoted to some other emerging competitors of DRAM, such as capacitor-less DRAM and potential nonvolatile memories, namely, ferroelectric RAM (FRAM), magnetoresistive RAM (MRAM), including STT MRAM, and phase-change RAM.
It is not only that the size of the cell is to be reduced with increasing DRAM density but the way the two basic components, the transistor and the storage capacitor, are realized and positioned physically with respect to each other, and how the word and bit line are fabricated are also important for its functional and economic feasibility. Early-and medium-stage DRAM cells are discussed in Chapter 2. It includes planar DRAM cells used for 1–4 Mbit density, in which a metal-oxide-semiconductor field-effect transistor (MOSFET) and a capacitor were fabricated side by side. As it was physically not possible to accommodate higher-density DRAMs in a two-dimensional small area, capacitor was located below the substrate surface in trench capacitor cells or the capacitor above the surface of the substrate in stacked capacitor cells. Types of first-generation trench capacitor cells in which the storage node was outside the dielectrically lined trench were the initial stage three-dimensional cells. With the main intention of decreasing cell leakage and improving soft error rate, inverted trench cells were fabricated in which the storage electrode was inside the isolated trench. Further increases in the density of DRAMs brought cells very close to each other, increasing leakage. Moreover, to get sufficient capacitance, the trench was required to be deeper. Facing a bottleneck in technology advancements, stacked capacitors, with horizontal and vertical fin–structured capacitor cells, were found to be more suitable. With improved technology and better fabrication processes, higher value dielectric-based capacitors realized higher-density DRAM cells.
In the planar DRAM cell, a thoroughly studied planar MOSFET was used. However, 1 Gbit and beyond DRAMs found the drivability of the conventional transistor impractical because of its small channel width. Cell array voltage was also coming down and problems of short channel effect, leakage currents, hot electron generation, and so on, forced researchers to pursue different/advanced transistors. Recessed types of transistors, delta-structured transistors that later took the form of Fin field effect transistors (FinFETs), replaced the conventional transistors. Along with a discussion on these transistors, a few other transistors like body-tied MOSFET bulk FinFET and saddle MOSFETs are included in Chapter 4. A major advancement came in the form of the surrounding gate transistor (SGT) and stacked SGT, with the help of which cell size could be highly reduced. Vertical cells and some advanced cells that combined the better features of earlier developed transistors have also been used. Buried strap (BEST) and vertical BEST (VERIBEST) DRAM cells are examples of cells with advanced trench capacitors.
Fabrication of storage capacitance in an ever decreasing available chip area is a critical issue for DRAMs. Considerable attention has been paid to the use of a variety of dielectrics, materials for the capacitor electrodes, and the physical formation of the capacitor. Obviously planar transistors with polysilicon electrodes and SiO2 as dielectric had a limit, even when dielectric thickness was reduced to its minimum permissible value of 3–4 nm. Use of textured storage nodes has been shown effective in increasing realized capacitance not only in planar capacitors but also in capacitors with other complex shapes. However, major advancement behind capacitance enhancement came with the use of metal-insulator-metal (MIM) capacitors with high dielectric constants value insulators like Ta2O5 and barium strontium titanate (BST).
An increase in DRAM density and improvement in its performance could become possible with improvements in fabrication processes, circuit innovations, and technological advances. A cornerstone in DRAM development is the reduction in minimum feature size F or technology scaling. Technological developments since the early stage to around 1 Gbit DRAM density are included in Chapter 3, and advanced developments are included in Chapter 6 after going through the study of advanced cell transistors and storage capacitor enhancement techniques in Chapters 4 and 5, as the technology is strongly connected with the two basic components of the DRAM. Change over to complementary MOSFET (CMOS) technology was a major event that occurred mainly to reduce power consumption. An important connected circuit innovation was (VDD/2) precharging of the bit line before the read operation, which changed many design rules in a positive way. Stacked capacitor developments especially in crown shape with Ta2O5 as dielectric-related technological developments were very significant.
Another class of stacked capacitor arrangement in which the realized capacitor enclosed the bit line has continued its usage as it helped in minimizing bit-line noise considerably. Advancements in the DRAM technologies are focused mainly on fabricating a high-performance transistor and a compact capacitor in a minimum-sized cell and interconnections with a minimum of parasitic capacitance and resistance with the help of advanced lithographic technologies. Obviously every generation brought new challenges. Initial-stage capacitor-over-bit-line (COB) cells, discussed in Chapter 3, were improved to remove some drawbacks of difficulty in making connection with the buried bit line. The advancements in technology were gradual in a sense that at every stage, some new technologies were merged with the older ones; however, on the two sides of 100 nm nodes, technology perspectives were significantly different. The height of the storage node now needed to be so high that it needed mechanical stability. Two prominent technologies for the purpose discussed in Section 6.3 are leaning exterminated ring-type insulator (LERI) and mechanically enhanced storage node for unlimited height (MESH). Most of the advanced transistors and capacitors were already discussed in Chapters 4 and 5, and advantages obtained through them were integrated with other technologies such as developments in lithography and resolution enhancement technologies (RETs), without which ever-decreasing features could not be fabricated. Other important support technologies are in the form of isolation techniques such as moving from local oxidation of silicon (LOCOS) to shallow trench isolation (STI) and the filling of dense oxide in trenches and gaps. Formation of bit lines, word lines, and their connection with source/drain and gate, which assumed significance and performance, had to be improved through the use of low-resistance materials with a minimum of parasitic capacitance.
With decreasing dimension, fringe capacitance dominates and bit-line capacitance does not come down. Use of Si3N4 capping of bit and word lines also adds to the parasitic capacitance. As the word line is to be connected to the transistor gate, while remaining isolated from source/drain, and the storage capacitor node is to be connected with the source, cell connections assume significance; use of materials like Ti and W has found favor. Lithographic error tolerance reduction has to be attended to as well. Smaller width of connecting wires, word lines, and bit lines results in stress-induced fabrication failures, and use of aluminum was constrained. Multilayer connection wire and other metals like Cu became necessary. At the same time as all the wires were surrounded by dielectrics, which resulted in interwire capacitance, use of a low-dielectric environment along with a high-conductivity wire strip became a topic of intense research.
After a brief survey of the technologies deployed at various stages in DRAM development, technology flow is described in Section 6.11. It is hoped that the problems faced and the solutions employed at the 0.18 μm stage, 100 nm to 50 nm, and sub-50 nm levels will help readers form their views about the technological steps. Selection of dielectrics, formation of capacitor electrodes, filling of gaps without or with a minimum of voids, formation of contact holes, planarization, and self-aligned contact (SAC) change their implementation and the direction of the technology progress. Evolution of photolithography while using KrF and ArF has to be paid maximum attention, without which any conceived design would not be born.
Going below 50 nm using stacked capacitor technology presented new challenges, which are being faced through the use of MIM capacitors with dielectric materials like HfO2/Al2O3 stacks and ZrO2 films in conjunction with advanced transistors such as recessed transistors, body tied FinFETs, vertical pillar transistors, and saddle transistors. The buried word-line scheme, which uses extended U-shaped devices with metal gates, is another important technology. Use of high-k materials has also been employed in deep trench technology in sub-100 nm levels. A checkerboard layout (CKB), having highly symmetrical lines and spaces, is helpful in realizing smaller technology nodes. One of the technological solutions for faster data transfer with DRAM was developed in the form of embedded DRAM (eDRAM) in which good points of high-density DRAM and logic modules were combined to lead toward realizing a system-on-chip (SOC). Some contradictory requirements while fabricating high-density DRAM and the logic modules on the same chip are discussed at the end of Chapter 6, and the technologies adopted to overcome the problem faced are described. Fabrication of eDRAM was mostly done on bulk silicon up to 65 nm technologies, but beyond that silicon-on-insulator (SOI) substrate was used in a simplified deep trench process. SOI logic has been realized in 45 nm and 32 nm node technology for advance applications. Stacked capacitor cells, which were not preferred earlier because of the high-temperature processes involved, were also modified to give full-metal eDRAM using MIM capacitor.
Power dissipation in the ever-increasing transistor count on a chip has always been one of the most important issues. One major successful remedy is the reduction in the working voltage, which was otherwise also critical in the highly expanding mobile market. Therefore, low-voltage low-power memories/logic and systems are receiving big attention. Different kinds of leakage currents, which are mainly responsible for power dissipation in DRAMs, are discussed in Chapter 7; their effect on cell signal charge and data retention is studied. Depending upon applications, power dissipation in active mode, sleep mode, or both modes is critical and needs to be minimized. Several methods are now available, which are applicable in general or specific in nature for the active or sleep mode. Another very important factor is the study of power consumption during refreshing of DRAMs and the frequency with which refreshing has to be done. Technological developments have greatly affected this area. A considerable amount of research work is going on looking into different aspects of the DRAM’s power consumption reduction.
Peripherals greatly affect the cost and speed of the DRAM. Though the basics of all the peripherals have remained same, their construction has changed considerably with the increasing complexity of DRAMs. Hence, only the simplest versions of row and column decoders have been included; actual architecture does depend on the way the high-density DRAM is divided in blocks and sub-blocks and the way the bit lines and/or word lines are segmented/divided/shared. The sense amplifier is one very important component and has undergone many changes, despite the basic gated flip-flop remaining firmly placed. Keeping the cost of the DRAM competitive is one major aim; therefore, the use of redundancy techniques and error correction coding (ECC) is also very important. Combinations of redundancy and ECC for high-density DRAMs are also studied briefly in the last chapter on DRAM peripherals.