Cover image for Advances in Embedded and Fan-Out Wafer Level Packaging Technologies

Advances in Embedded and Fan-Out Wafer Level Packaging Technologies

Author Steffen Kroehnert , Beth Keser
Release Date: 2019/02/01
ISBN: 9781119314134
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Book Description

Examines the advantages of Embedded and FO-WLP technologies, potential application spaces, package structures available in the industry, process flows, and material challenges

Embedded and fan-out wafer level packaging (FO-WLP) technologies have been developed across the industry over the past 15 years and have been in high volume manufacturing for nearly a decade. This book covers the advances that have been made in this new packaging technology and discusses the many benefits it provides to the electronic packaging industry and supply chain. It provides a compact overview of the major types of technologies offered in this field, on what is available, how it is processed, what is driving its development, and the pros and cons.

Filled with contributions from some of the field's leading experts,Advances in Embedded and Fan-Out Wafer Level Packaging Technologies begins with a look at the history of the technology. It then goes on to examine the biggest technology and marketing trends. Other sections are dedicated to chip-first FO-WLP, chip-last FO-WLP, embedded die packaging, materials challenges, equipment challenges, and resulting technology fusions.

  • Discusses specific company standards and their development results
  • Content relates to practice as well as to contemporary and future challenges in electronics system integration and packaging

Advances in Embedded and Fan-Out Wafer Level Packaging Technologies will appeal to microelectronic packaging engineers, managers, and decision makers working in OEMs, IDMs, IFMs, OSATs, silicon foundries, materials suppliers, equipment suppliers, and CAD tool suppliers. It is also an excellent book for professors and graduate students working in microelectronic packaging research.

Table of Contents

  1. Cover
  2. Preface
  3. List of Contributors
  4. Acknowledgments
  5. 1 History of Embedded and Fan‐Out Packaging Technology
    1. 1.1 Introduction
    2. 1.2 First Embedding Technologies Based on MCM‐D Concepts
    3. 1.3 First Embedding Technologies Based on Organic Laminates and Flex
    4. 1.4 Helsinki University of Technology and Imbera Electronics Embedded Chips
    5. 1.5 Fraunhofer IZM/TU Berlin Chip‐in‐Polymer (CiP)
    6. 1.6 HiCoFlex, Chip‐in‐Flex, and UTCP
    7. 1.7 Conclusion
    8. References
  6. 2 FO‐WLP Market and Technology Trends
    1. 2.1 Introduction
    2. 2.2 FO‐WLP: A Disruptive Technology
    3. 2.3 Embedded Die Packaging
    4. 2.4 FO‐WLP Advantages
    5. 2.5 FO‐WLP Versions
    6. 2.6 Challenges for FO‐WLP
    7. 2.7 Drivers for FO‐WLP
    8. 2.8 Strong Demand for FO‐WLP
    9. References
  7. 3 Embedded Wafer‐Level Ball Grid Array (eWLB) Packaging Technology Platform
    1. 3.1 Technology Description
    2. 3.2 Basic Package Construction
    3. 3.3 Manufacturing Process Flow and BOM
    4. 3.4 System Integration Capability
    5. 3.5 Manufacturing Format and Scalability
    6. 3.6 Package Performance
    7. 3.7 Robustness and Reliability Data
    8. 3.8 Electrical Test Considerations
    9. 3.9 Applications and Markets
    10. References
  8. 4 Ultrathin 3D FO‐WLP eWLB‐PoP (Embedded Wafer‐Level Ball Grid Array‐Package‐on‐Package) Technology
    1. 4.1 Introduction
    2. 4.2 eWLB‐MLP (Mold Laser Package‐on‐Package) Technology
    3. 4.3 3D eWLB‐PoP Technology
    4. 4.4 3D eWLB SiP/Module
    5. 4.5 Conclusions
    6. References
  9. 5 NEPES’ Fan‐Out Packaging Technology from Single die, SiP to Panel‐Level Packaging
    1. 5.1 Introduction
    2. 5.2 Structure and Process Flow
    3. 5.3 Thin Fan‐Out Packaging
    4. 5.4 Double‐Sided Fan‐Out Packaging
    5. 5.5 Via Frame (VF) Fan‐Out Package
    6. 5.6 System‐in‐Package
    7. 5.7 Panel‐Level Package
    8. 5.8 Performance and Reliability
    9. 5.9 Application
    10. 5.10 Roadmap and Remarks
    11. References
  10. 6 M‐Series™ Fan‐Out with Adaptive Patterning™
    1. 6.1 Technology Description
    2. 6.2 Basic Package Construction
    3. 6.3 Manufacturing Process Flow and BOM
    4. 6.4 Design Features and System Integration Capability
    5. 6.5 Adaptive Patterning
    6. 6.6 Manufacturing Format and Scalability
    7. 6.7 Robustness and Reliability Data
    8. 6.8 Electrical Test Considerations
    9. 6.9 Applications and Markets
    10. Acknowledgment
    11. References
  11. 7 SWIFT® Semiconductor Packaging Technology
    1. 7.1 Technology Description
    2. 7.2 Basic Package Construction
    3. 7.3 Manufacturing Process
    4. 7.4 Design Features
    5. 7.5 Manufacturing Format and Scalability
    6. 7.6 Package Performance
    7. 7.7 Thermal Performance
    8. 7.8 Robustness and Reliability Data
    9. 7.9 Applications and Markets
    10. References
  12. 8 Embedded Silicon Fan‐Out (eSiFO®) Technology for Wafer‐Level System Integration
    1. 8.1 Technology Description
    2. 8.2 Basic Package Construction
    3. 8.3 Manufacturing Process Flow
    4. 8.4 Design Features
    5. 8.5 System Integration Capability
    6. 8.6 Manufacturing Format and Scalability
    7. 8.7 Package Performance
    8. 8.8 Robustness and Reliability Data
    9. 8.9 Applications and Markets
    10. Acknowledgment
    11. References
  13. 9 Embedding of Active and Passive Devices by Using an Embedded Interposer: The i2 Board Technology
    1. 9.1 Technology Description
    2. 9.2 Basic Interposer Construction
    3. 9.3 Manufacturing Process Flow and BOM
    4. 9.4 Design Features
    5. 9.5 System Integration Capability
    6. 9.6 Manufacturing Format and Scalability
    7. 9.7 Package Performance
    8. 9.8 Robustness and Reliability Data
    9. 9.9 Electrical Test Considerations
    10. 9.10 Applications and Markets
    11. 9.11 Summary
    12. References
  14. 10 Embedding of Power Electronic Components: The Smart p2 Pack Technology
    1. 10.1 Introduction
    2. 10.2 Technology Description p Pack
    3. 10.3 Basic Package Construction
    4. 10.4 The p Pack Technology Process Flow
    5. 10.5 Smart p Pack
    6. 10.6 Package Performance
    7. 10.7 Applications and Markets
    8. 10.8 Summary
    9. Acknowledgments
    10. References
  15. 11 Embedded Die in Substrate (Panel‐Level) Packaging Technology
    1. 11.1 Technology Description
    2. 11.2 Basic Package Construction
    3. 11.3 Manufacturing Process Flow and BOM
    4. 11.4 Design Features
    5. 11.5 System Integration Capability
    6. 11.6 Package Performance
    7. 11.7 Diversity of EDS Technology: Module
    8. 11.8 Diversity of EDS Technology: Power Devices
    9. 11.9 Applications and Markets
    10. References
  16. 12 Blade: A Chip‐First Embedded Technology for Power Packaging
    1. 12.1 Technology Description
    2. 12.2 Development and Implementation
    3. 12.3 Basic Package Construction
    4. 12.4 Manufacturing Process Flow and BOM
    5. 12.5 Design Features
    6. 12.6 System Integration Capability
    7. 12.7 Manufacturing Format and Scalability
    8. 12.8 Package Performance
    9. 12.9 Robustness and Reliability Data
    10. 12.10 Electrical Test Considerations
    11. 12.11 Applications and Markets
    12. Acknowledgments
    13. References
  17. 13 The Role of Liquid Molding Compounds in the Success of Fan‐Out Wafer‐Level Packaging Technology
    1. 13.1 Introduction
    2. 13.2 The Necessity of Liquid Molding Compound for FO‐WLP
    3. 13.3 The Required Parameters of Liquid Molding Compound for FO‐WLP
    4. 13.4 Design of LMC Resin Formulation
    5. 13.5 Development of LMC in Connection with Latest Requirements
    6. 13.6 Current LMC Representative Proprieties
    7. 13.7 Conclusions
    8. Acknowledgment
    9. References
  18. 14 Advanced Dielectric Materials (Polyimides and Polybenzoxazoles) for Fan‐Out Wafer‐Level Packaging (FO‐WLP)
    1. 14.1 Introduction
    2. 14.2 Brief History of PI/PBO‐Based Materials in Semiconductor Applications
    3. 14.3 Dielectric Challenges in FO‐WLP Applications
    4. 14.4 HDM Material Sets for FO‐WLP
    5. 14.5 PBO‐Gen3 (Positive‐Acting, Aqueous‐Developable Material)
    6. 14.6 PBO‐Gen3 Process Flow
    7. 14.7 PBO‐Gen3 Lithography
    8. 14.8 PBO‐Gen3 Material Properties
    9. 14.9 PBO‐Gen3 Dielectric Reliability Testing
    10. 14.10 PBO‐Gen3 Package Reliability Performance (TCT Testing at Component and Board Level)
    11. 14.11 Performance Comparison Between PBO‐Gen3 and PBO‐Gen2
    12. 14.12 PI‐Gen2 (Negative‐Acting, Solvent‐Developable Material)
    13. 14.13 PI‐Gen2 Process Flow
    14. 14.14 PI‐Gen2 Lithography
    15. 14.15 PI‐Gen2 Material Properties
    16. 14.16 PI‐Gen2 Dielectric Reliability Data
    17. 14.17 PI‐Gen2 Package Reliability Performance (Component and Board Level)
    18. 14.18 Comparison Between PBO‐Gen3 and PI‐Gen2
    19. 14.19 Summary
    20. References
  19. 15 Enabling Low Temperature Cure Dielectrics for Advanced Wafer‐Level Packaging
    1. 15.1 Description of Technology
    2. 15.2 Material Challenges for FO‐WLP
    3. 15.3 Material Overview
    4. 15.4 Process Flow
    5. 15.5 Material Properties
    6. 15.6 Design Rules
    7. 15.7 Reliability
    8. 15.8 Next Steps
    9. References
  20. 16 The Role of Pick and Place in Fan‐Out Wafer‐Level Packaging
    1. 16.1 Introduction
    2. 16.2 Equipment Requirements for Fan‐Out Bonders
    3. 16.3 Avoiding Fan‐Out Bonding Pitfalls
    4. 16.4 Equipment Qualification for Fan‐Out Pick and Place
    5. 16.5 Running a Large Area Glass‐on‐Glass Process
    6. 16.6 Running a Glass‐on‐Carrier Process
    7. 16.7 Running a Reference Production Lot with Test Die
    8. 16.8 Conclusions
    9. References
  21. 17 Process and Equipment for eWLB: Chip Embedding by Molding
    1. 17.1 Introduction
    2. 17.2 Historical Background Molding
    3. 17.3 The Molded Wafer Idea: Key for the Fan‐Out eWLB Technology
    4. 17.4 The Compression Molding Process
    5. 17.5 Principle Challenges for Chip Embedding with Compression Molding
    6. 17.6 Process Development Solutions for Principle Challenges
    7. 17.7 Compression Molding Equipment for Chip Embedding
    8. 17.8 Chip Embedding Features Achieved by Compression Molding
    9. 17.9 Conclusions and Next Steps
    10. Acknowledgments
    11. References
  22. 18 Tools for Fan‐Out Wafer‐Level Package Processing
    1. 18.1 Turnkey Solution for Fan‐Out Wafer‐Level Packaging
    2. 18.2 Die Placement Process and Tools for FO‐WLP
    3. 18.3 Encapsulation Tool for Large Format Encapsulation
    4. 18.4 The Test Handling and Packing Solution for Wafer‐Level Packaging and FO‐WLP
    5. References
  23. 19 Equipment and Process for eWLB: Required PVD/Sputter Solutions
    1. 19.1 Background
    2. 19.2 Process Flow
    3. 19.3 Equipment Challenges for FO‐WLP
    4. 19.4 Equipment Developed to Overcome Challenges
    5. 19.5 Additional Equipment Features
    6. 19.6 Design Rules Related to the Equipment
    7. 19.7 Reliability
    8. 19.8 Next Steps
    9. References
  24. 20 Excimer Laser Ablation for the Patterning of Ultra‐fine Routings
    1. 20.1 Advanced Packaging Applications and Technology Trends
    2. 20.2 The High Density Structuring Challenge
    3. 20.3 Excimer Laser Ablation Technology
    4. 20.4 Summary and Conclusion
    5. References
  25. 21 Temporary Carrier Technologies for eWLB and RDL‐First Fan‐Out Wafer‐Level Packages
    1. 21.1 Slide‐Off Debonding for FO‐WLP
    2. 21.2 Laser Debonding: Universal Carrier Release Process for Fan‐Out Wafer Packages
    3. 21.3 Parameters Influencing DPSS Laser Debonding
    4. Acknowledgments
    5. References
  26. 22 Encapsulated Wafer‐Level Package Technology (eWLCSP): Robust WLCSP Reliability with Sidewall Protection
    1. 22.1 Improving the Conventional WLCSP Structure
    2. 22.2 The Encapsulated WLCSP Process
    3. 22.3 Advantages of the Encapsulated WLCSP, eWLCSP
    4. 22.4 eWLCSP Reliability
    5. 22.5 Reliability of Larger eWLCSP over 6 mm × 6 mm Package Size
    6. 22.6 eWLCSP Wafer‐Level Final Test
    7. 22.7 Conclusions
    8. References
  27. 23 Embedded Multi‐die Interconnect Bridge (EMIB): A Localized, High Density, High Bandwidth Packaging Interconnect
    1. 23.1 Introduction
    2. 23.2 EMIB Architecture
    3. 23.3 High Level EMIB Process Flow
    4. 23.4 EMIB Signaling
    5. 23.5 Conclusions
    6. Acknowledgments
    7. References
  28. 24 Interconnection Technology Innovations in2.5D Integrated Electronic Systems
    1. 24.1 Introduction
    2. 24.2 Polymer‐Enhanced TSVs
    3. 24.3 HIST
    4. 24.4 Conclusion
    5. References
  29. Index
  30. End User License Agreement
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