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Design Verification with

Author Samir Palnitkar
Release Date: 2003/09/01
ISBN: 0131413090
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Book Description

Design Verification with eSamir Palnitkar

Written for both experienced and new users, DesignVerification with e gives you a broadcoverage of e. It stresses the practical verification perspective of e rather than emphasizing only itslanguage aspects.

This book—

  • Introduces you to e-based verification methodologies

  • Describes e syntax in detail, including structs, units, methods, events, temporal expressions. and TCMs

  • Explains the concepts of automatic generation, checking and coverage

  • Discusses the e Reuse Methodology

  • Describes essential topics such as coverage driven verification, e verification components (eVCs), and interfacing with C/C++

  • Illustrates a complete verification example in e

  • Contains a quick-reference guide to the e language

  • Offers many practical verification tips

Includes over 250 illustrations, examples, andexercises, and a verification resource list. Learning objectives and summariesare provided for each chapter.

“Mr. Palnitkar illustrates how and why the power ofthe everification language and the underlying Specman Elite testbench automationtool are used to develop today's most advanced verification environments. Thisbook is valuable to both the novice and the experienced e user. I highlyrecommend it to anyone exploring functional verification”

—Moshe Gavrielov

Chief Executive Officer

Verisity Design, Inc.

“This book demonstrates how e can be used to createstate-of-the-art verification environments. An ideal book to jumpstarta beginner and a handy reference for experts”

—Rakesh Dodeja

Engineering Manager

Intel Corporation

“The book gives a simple, logical, and well-organizedpresentation of ewith plenty of illustrations. This makes it an ideal text book for universitycourses on functional  verification”

—Dr. Steven Levitan

 Professor

 Department of Electrical Engineering

 University of Pittsburgh, Pittsburgh, PA

“This book is ideal for readers with little or no e programming experience. It gives the reader athorough and practical understanding of not only the e language, but also how to effectively use thislanguage to develop complex functional verification environments.”

—Bill Schubert

Verification Engineer

ST Microelectronics, Inc.

“The flow of the book is logical and gradual. Plentyof illustrations and examples makes this an ideal book for e users. A must-have for both beginners andexperts”

—Karun Menon

Staff Engineer

Sun Microsystems, Inc.

PRENTICEHALL

ProfessionalTechnical Reference

UpperSaddle River, NJ  07458

www.phptr.com

ISBN:0-13-144309-0

Table of Contents

  1. Copyright
  2. Prentice Hall Modern Semiconductor Design Series
  3. Foreword
  4. Preface
  5. Acknowledgements
  6. List of Figures
  7. List of Tables
  8. List of Examples
  9. Introduction
    1. Overview of Functional Verification
      1. The Evolution of Verification
      2. Verification Automation System with e
      3. Benefits of e
      4. Summary
    2. Modeling a Verification Environment in e
      1. Interaction between Specman Elite and the Simulator
      2. Structs and Instances
      3. Components of a Verification Environment
      4. Verification Example
      5. Summary
      6. Exercises
  10. e Basics
    1. Basic e Concepts
      1. Conventions
      2. Data Types
      3. Simulator Variables
      4. Syntax Hierarchy
      5. Summary
      6. Exercises
    2. Creating Hierarchy with Structs and Units
      1. Defining Structs
      2. Extending Structs
      3. Defining Fields
      4. Defining List Fields
      5. Creating Struct Subtypes with when
      6. Units
      7. Summary
      8. Exercises
    3. Constraining Generation
      1. Basic Concepts of Generation
      2. Basic Constraints
      3. Implication Constraints
      4. Soft Constraints
      5. Weighted Constraints
      6. Order of Generation
      7. Constraint Resolution
      8. Do-Not-Generate Fields
      9. Summary
      10. Exercises
    4. Procedural Flow Control
      1. Defining Methods
      2. Conditional Actions
      3. Iterative Actions
      4. Useful Output Routines
      5. Summary
      6. Exercises
    5. Events and Temporal Expressions
      1. Defining Events
      2. Event Emission
      3. Event Redefinition
      4. Sampling Events
      5. Temporal Operators
      6. Temporal Expressions
      7. Predefined Events
      8. Summary
      9. Exercises
    6. Time Consuming Methods
      1. Defining TCMs
      2. Invoking TCMs
      3. Wait and Sync Actions
      4. Gen Action
      5. Using HDL Tasks and Functions
      6. Summary
      7. Exercises
    7. Checking
      1. Packing and Unpacking
      2. Data Checking
      3. Temporal Checking
      4. Summary
      5. Exercises
    8. Coverage
      1. Functional Coverage
      2. Coverage Groups
      3. Basic Coverage Item
      4. Transition Coverage Items
      5. Cross Coverage Items
      6. Latency Coverage
      7. Turning On Coverage
      8. Viewing Coverage Results
      9. Summary
      10. Exercises
    9. Running the Simulation
      1. Verification Components
      2. Execution Flow
      3. Synchronization between HDL Simulator and Specman Elite
      4. Summary
      5. Exercises
  11. Creating a Complete Verification System with e
    1. Verification Setup and Specification
      1. Device Under Test (DUT) Specification
      2. DUT HDL Source Code
      3. Verification Plan
      4. Test Plan
      5. Summary
    2. Creating and Running the Verification Environment
      1. Defining the Packet Data Item
      2. Driver Object
      3. Receiver Object
      4. Data Checker Object
      5. Monitor Object
      6. Coverage Object
      7. Environment Object
      8. Test Scenarios
      9. Summary
  12. Advanced Verification Techniques with e
    1. Coverage-Driven Functional Verification
      1. Traditional Verification Methodology
      2. Why Coverage?
      3. Coverage Approaches
      4. Functional Coverage Setup
      5. Coverage Driven Functional Verification Methodology
      6. Summary
    2. Reusable Verification Components (eVCs)
      1. About eVCs
      2. eVC Architecture
      3. eVC Example
      4. Summary
    3. Interfacing with C
      1. C Interface Features
      2. Integrating C Files
      3. Accessing the e Environment from C
      4. Calling C Routines from e
      5. Calling e Methods from C
      6. C Export
      7. Guidelines for Using the C Interface
      8. Linking with C++ Code
      9. Summary
  13. Appendices
    1. Quick Reference Guide
      1. Predefined Types
      2. Type Conversion
      3. Statements
      4. Structs and Unit Members
      5. Actions
      6. Operators
      7. Coverage Groups and Items
      8. Lists
      9. Temporal Language
      10. Packing and Unpacking Pseudo-Methods
      11. Simulator Interface Statements and Unit Members
      12. Preprocessor Directives
    2. e Tidbits
      1. History of e
      2. e Resources
      3. Verification Resources
  14. Bibliography
    1. Manuals and References
    2. Books
  15. About the Author
  16. Index
13.59.218.147