Cover image for Field-Programmable Gate Arrays: Reconfigurable Logic for Rapid Prototyping and Implementation of Digital Systems

Field-Programmable Gate Arrays: Reconfigurable Logic for Rapid Prototyping and Implementation of Digital Systems

Author Richard C. Dorf , John V. Oldfield
Release Date: 1995/01/01
ISBN: 9780471556657
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Book Description

Timely, authoritative, application-oriented. an in-depth exploration of current and future uses of FPGAs in digital systems The development of field-programmable gate arrays (FPGAs) may well be the most important breakthrough for the microelectronics industry since the invention of the microprocessor. Using FPGAs, a system designer working on a PC can now develop a working prototype in a few hours and change it at will in just a few minutes, rather than waiting weeks or months for a printed-circuit assembly or a custom integrated circuit to be built. This newfound ability to change a system by simply altering its configuration memory is also leading to exciting new forms of computing, such as array applications that exploit parallelism. Now in a book that functions equally well as a working professional reference and a pedagogically consistent computer engineering text, John V. Oldfield and Richard C. Dorf:

  • Provide a detailed overview of FPGAs in digital systems design

  • Explain the underlying principles, strengths, and limitations of most FPGA architectures

  • Supply many real-life case studies, from elementary to advanced applications--including examples of "custom computing machines"

  • Review cutting-edge developments, including new architectures and a new field-programmable interconnect chip

  • Discuss key economic and business aspects of FPGA manufacture and applications and their role in intellectual property protection

  • Demonstrate ways in which FPGAs offer plausible solutions to some of the major computing problems of our day

Table of Contents

  1. Coverpage
  2. Titlepage
  3. Copyright
  4. Dedication
  5. Contents
  6. Foreword
  7. Preface
  8. Acronyms
  9. Trademarks and Proprietary Names
  10. 1.   SYSTEM IMPLEMENTATION STRATEGIES
    1. 1.1   The FPGA Paradigm
    2. 1.2   Design and Implementation Using FPGAs
    3. 1.3   Implementation Styles
      1. 1.3.1   Era of Early Logic Families
      2. 1.3.2   Era of LSI and VLSI Components
      3. 1.3.3   Era of ASICs
      4. 1.3.4   Era of Programmable Logic
    4. 1.4   Design Styles
      1. 1.4.1   The Software Paradigm
      2. 1.4.2   The Hardware Paradigm
      3. 1.4.3   The Configurable Hardware Paradigm
    5. 1.5   Design Methodologies
      1. 1.5.1   Describing a Design
      2. 1.5.2   Hierarchical Design
      3. 1.5.3   Technology-independent Design
      4. 1.5.4   The Mead–Conway Design Method
      5. 1.5.5   Temporal Design
      6. 1.5.6   Pipelined
      7. 1.5.7   Unsynchronized
  11. 2.   REVIEW OF LOGIC DESIGN AND ELECTRICAL ASPECTS
    1. 2.1   Combinational Circuit Design
      1. 2.1.1   Boolean Algebra
      2. 2.1.2   Multiplexers and Boolean Function Evaluation
    2. 2.2   Sequential Circuits
      1. 2.2.1   Latches and Flip-Flops
    3. 2.3   State Machines
      1. 2.3.1   Encoded State Machines
      2. 2.3.2   “One-hot” State Machines
    4. 2.4   Petri Nets for State Machines
      1. 2.4.1   Basic Concepts
      2. 2.4.2   Basic Properties
      3. 2.4.3   Extended Petri Nets for Parallel Controllers
      4. 2.4.4   Simple Example—A Traffic Light Controller
      5. 2.4.5   Implementation of Petri Net Description
    5. 2.5   Electrical Aspects
      1. 2.5.1   Complementary MOS Circuits
      2. 2.5.2   Voltage Levels and Loading
      3. 2.5.3   Three-state Outputs
      4. 2.5.4   Signal Propagation in CMOS
      5. 2.5.5   Electrostatic Precautions and ESD Protection
      6. 2.5.6   Switch Debouncing
      7. 2.5.7   Power Supply Regulation
      8. 2.5.8   Metastability Characteristics
  12. 3.   INTRODUCTION TO FPGA ARCHITECTURE
    1. 3.1   Background to the FPGA Concept
      1. 3.1.1   History
    2. 3.2   Channel-type Field-programmable Gate Arrays
      1. 3.2.1   Distinguishing Architectural Features
      2. 3.2.2   Scaling with Technology Improvements
      3. 3.2.3   The Xilinx 3000 Series
      4. 3.2.4   The Actel ACT 2 Family
    3. 3.3   Structured Programmable Array Logic
      1. 3.3.1   The Altera EP1810
    4. 3.4   Computational Logic Arrays
      1. 3.4.1   The Algotronix CAL 1024
    5. 3.5   VLSI Primitives
      1. 3.5.1   Function Units
      2. 3.5.2   Wide Gates and Long Lines
      3. 3.5.3   Switches and Switch Boxes
      4. 3.5.4   Multiplexers
      5. 3.5.5   Input–Output Pad Design
    6. 3.6   Programming
      1. 3.6.1   Technology
      2. 3.6.2   Issues
    7. 3.7   Benchmarking
      1. 3.7.1   Utilization
      2. 3.7.2   Gate Equivalents
      3. 3.7.3   RAM- and Area-based Benchmarks
      4. 3.7.4   Benchmarking and Dynamic Reconfiguration
      5. 3.7.5   The PREP Benchmarks
      6. 3.7.6   Summary and Health Warning
    8. 3.8   Historical Background
      1. 3.8.1   Early Work
      2. 3.8.2   PALs and Structured PALs
      3. 3.8.3   FPGAs
      4. 3.8.4   Computational Arrays
      5. 3.8.5   VLSI Primitives and Programming
      6. 3.8.6   Benchmarking
  13. 4.   DESIGN PROCESS FLOWS AND SOFTWARE TOOLS
    1. 4.1   The Software Toolbox
      1. 4.1.1   Design Capture
      2. 4.1.2   Tools for Design Validation
      3. 4.1.3   Tools for Physical Design
    2. 4.2   The FPGA Design Dichotomy
    3. 4.3   Design Process Flow
      1. 4.3.1   Conceptual Design of Display Driver
      2. 4.3.2   Design Verification of Display Driver
      3. 4.3.3   Physical Design of Display Driver
    4. 4.4   Design Process Flow: The Application-specific Integrated Circuit Route
      1. 4.4.1   Conceptual Design of Stopwatch
      2. 4.4.2   Design Verification of Stopwatch
      3. 4.4.3   Physical Design of Stopwatch
    5. 4.5   Libraries and Design Idioms
      1. 4.5.1   Parameterized Libraries
    6. 4.6   Placement, Routing, and Wireability
      1. 4.6.1   Rent’s Rule and Package Pin-outs
      2. 4.6.2   Rent’s Rule and Wireability
      3. 4.6.3   Partitioning Designs within and across Chips
  14. 5.   CASE STUDIES
    1. 5.1   Combinational Circuits
      1. 5.1.1   Parallel Adder Cell
      2. 5.1.2   Parallel Adder
    2. 5.2   Sequential Circuits
      1. 5.2.1   Decade Counter
    3. 5.3   Pseudorandom Number Generation
    4. 5.4   Random Testing
      1. 5.4.1   Signature Analyzer
      2. 5.4.2   State Machine
    5. 5.5   Systolic Sorter
    6. 5.6   Multipliers
      1. 5.6.1   Parallel Multipliers
      2. 5.6.2   Serial Multiplier with Parallel Addition
    7. 5.7   A Parallel Controller Design
      1. 5.7.1   Operation of Part of the Petri Net Controller
      2. 5.7.2   Characteristics of the Design Technique
      3. 5.7.3   Implementation on XC3090
      4. 5.7.4   Conclusions
  15. 6.   COMPUTATIONAL APPLICATIONS
    1. 6.1   The State of the Art
    2. 6.2   Architecture of the CHS2×4
      1. 6.2.1   Hardware Architecture
    3. 6.3   DES Encryption
      1. 6.3.1   The DES Process
      2. 6.3.2   Implementation of DES
      3. 6.3.3    Pipelining
      4. 6.3.4    Performance
    4. 6.4    Self-timed First-In First-Out Buffer
      1. 6.4.1    STEP Elements
      2. 6.4.2    CAL Implementation
      3. 6.4.3    Filling the Self-timed FIFO
      4. 6.4.4    Designing in CAL
      5. 6.4.5    A Full-custom Self-timed FIFO
      6. 6.4.6    Conclusions
    5. 6.5    Self-timed Genetic String Distance Evaluation
      1. 6.5.1    String Comparison
      2. 6.5.2    Genetic Sequence Comparison
      3. 6.5.3    Dynamic Programming Algorithm
      4. 6.5.4    Implementation Considerations
      5. 6.5.5    Performance Evaluation
      6. 6.5.6    The Self-timed Implementation
    6. 6.6    Cellular Automaton
      1. 6.6.1    The Model
      2. 6.6.2    Architecture
      3. 6.6.3    Comparison with Previous Systems
      4. 6.6.4    Conclusion
    7. 6.7    Place-and-Route Acceleration
      1. 6.7.1    The Global Routing Algorithm
      2. 6.7.2    Hardware Architecture
      3. 6.7.3    CAL Layout
      4. 6.7.4    Software
      5. 6.7.5    Performance
    8. 6.8    A Field-Programmable Gate Array for Systolic Computing
      1. 6.8.1    Introduction
      2. 6.8.2    CLi6000 Architecture
      3. 6.8.3    Motion Estimation
      4. 6.8.4    Algorithm Overview
      5. 6.8.5    Processing Elements
      6. 6.8.6    Absolute-difference Module and Accumulator
      7. 6.8.7    Processing-element Layout
      8. 6.8.8    Technology Comparisons
      9. 6.8.9    Conclusions
  16. 7.   BUSINESS DEVELOPMENT
    1. 7.1   Technology Push or Market Pull?
    2. 7.2   The Pioneers
    3. 7.3   FPGA Market and Start-up Companies
      1. 7.3.1   Rapid Prototyping
      2. 7.3.2   Logic Replacement
      3. 7.3.3   Arrays of FPGA Chips
      4. 7.3.4   Dynamic Reconfiguration
      5. 7.3.5   Do You Need a Fabrication Facility?
    4. 7.4   The MPGA as an Alternative to the FPGA for Low-volume Production
    5. 7.5   Intellectual Property
      1. 7.5.1   Patents
      2. 7.5.2   Copyrights
      3. 7.5.3   The Semiconductor Chip Protection Act of 1984
      4. 7.5.4   Trade Secrets
      5. 7.5.5   Reverse Engineering
    6. 7.6   Sources for Capital
      1. 7.6.1   Small Business Innovation Research
      2. 7.6.2   Small Business Technology Transfer Program
  17. 8.   RECENT DEVELOPMENTS
    1. 8.1   Introduction
    2. 8.2   New Architectures
      1. 8.2.1   Altera FLEX
      2. 8.2.2   Pilkington (Motorola/Plessey/Toshiba)
      3. 8.2.3   Xilinx XC4000 Family
    3. 8.3   Field-programmable Interconnect
      1. 8.3.1   Aptix Field-programmable Interconnect
      2. 8.3.2   I-Cube IQ160 Description
    4. 8.4   Configurable Logic Arrays and Prototyping Boards
      1. 8.4.1   The XESS RIPP Board
    5. 8.5   CAD Support
      1. 8.5.1   NeoCAD Foundry
    6. 8.6   Future Outlook
  18. AFTERWORD
  19. GLOSSARY
  20. INDEX
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