Cover image for VLSI Design Methodology Development, First Edition

VLSI Design Methodology Development, First Edition

Author Thomas Dillinger
Release Date: 2019/06/01
ISBN: 9780135657645
Topic:
0%
38
Chapters
0-1
Hours read
0k
Total Words
    Start Reading Now    
       Add to Wishlist       
View table of contents

Book Description

The Complete, Modern Tutorial on Practical VLSI Chip Design, Validation, and Analysis

As microelectronics engineers design complex chips using existing circuit libraries, they must ensure correct logical, physical, and electrical properties, and prepare for reliable foundry fabrication. VLSI Design Methodology Development focuses on the design and analysis steps needed to perform these tasks and successfully complete a modern chip design.

Microprocessor design authority Tom Dillinger carefully introduces core concepts, and then guides engineers through modeling, functional design validation, design implementation, electrical analysis, and release to manufacturing. Writing from the engineer's perspective, he covers underlying EDA tool algorithms, flows, criteria for assessing project status, and key tradeoffs and interdependencies. This fresh and accessible tutorial will be valuable to all VLSI system designers, senior undergraduate or graduate students of microelectronics design, and companies offering internal courses for engineers at all levels.

  • Reflect complexity, cost, resources, and schedules in planning a chip design project
  • Perform hierarchical design decomposition, floorplanning, and physical integration, addressing DFT, DFM, and DFY requirements
  • Model functionality and behavior, validate designs, and verify formal equivalency
  • Apply EDA tools for logic synthesis, placement, and routing
  • Analyze timing, noise, power, and electrical issues
  • Prepare for manufacturing release and bring-up, from mastering ECOs to qualification

This guide is for all VLSI system designers, senior undergraduate or graduate students of microelectronics design, and companies offering internal courses for engineers at all levels. It is applicable to engineering teams undertaking new projects and migrating existing designs to new technologies.

Table of Contents

  1. Cover Page
  2. About This eBook
  3. Title Page
  4. Copyright Page
  5. Dedication Page
  6. Contents at a Glance
  7. Contents
  8. Preface
  9. About the Author
  10. Topic I: Overview of VLSI Design Methodology
    1. I.1 Methodology Guidelines for Logical and Physical Design Hierarchy Correspondence
    2. I.2 Managing Inter-Block Glue Logic
    3. Chapter 1. Introduction
      1. 1.1 Definitions
      2. 1.2 Intellectual Property (IP) Models
      3. 1.3 Tapeout and NRE Fabrication Cost
      4. 1.4 Fabrication Technology
      5. 1.5 Power and Clock Domains On-chip
      6. 1.6 Physical Design Planning
      7. 1.7 Summary
      8. References
      9. Further Research
    4. Chapter 2. VLSI Design Methodology
      1. 2.1 IP Design Methodology
      2. 2.2 SoC Physical Design Methodology
      3. 2.3 EDA Tool and Release Flow Management
      4. 2.4 Design Methodology “Trailblazing” and Reference Flows
      5. 2.5 Design Data Management (DDM)
      6. 2.6 Power and Clock Domain Management
      7. 2.7 Design for Testability (DFT)
      8. 2.8 Design-for-Manufacturability (DFM) and Design-for-Yield (DFY) Requirements
      9. 2.9 Design Optimization
      10. 2.10 Methodology Checks
      11. References
      12. Further Research
    5. Chapter 3. Hierarchical Design Decomposition
      1. 3.1 Logical-to-Physical Correspondence
      2. 3.2 Division of SRAM Array Versus Non-Array Functionality
      3. 3.3 Division of Dataflow and Control Flow Functionality
      4. 3.4 Design Block Size for Logic Synthesis and Physical Design
      5. 3.5 Power and Clock Domain Considerations
      6. 3.6 Opportunities for Reuse of Hierarchical Units
      7. 3.7 Automated Test Pattern Generation (ATPG) Limitations
      8. 3.8 Intangibles
      9. 3.9 The Impact of Changes to the SoC Model Hierarchy During Design
      10. 3.10 Generating Hierarchical Electrical Abstracts Versus Top-Level Flat Analysis
      11. 3.11 Methodologies for Top-Level Logical and Physical Hierarchies
      12. 3.12 Summary
      13. References
      14. Further Research
  11. Topic II: Modeling
    1. Chapter 4. Cell and IP Modeling
      1. 4.1 Functional Modeling for Cells and IP
      2. 4.2 Physical Models for Library Cells
      3. 4.3 Library Cell Models for Analysis Flows
      4. 4.4 Design for End-of-Life (EOL) Circuit Parameter Drift
      5. 4.5 Summary
      6. References
      7. Further Research
  12. Topic III: Design Validation
    1. Chapter 5. Characteristics of Functional Validation
      1. 5.1 Software Simulation
      2. 5.2 Testbench Stimulus Development
      3. 5.3 Hardware-Accelerated Simulation: Emulation and Prototyping
      4. 5.4 Behavioral Co-simulation
      5. 5.5 Switch-Level and Symbolic Simulation
      6. 5.6 Simulation Throughput and Resource Planning
      7. 5.7 Validation of Production Test Patterns
      8. 5.8 Event Trace Logging
      9. 5.9 Model Coverage Analysis
      10. 5.10 Switching Activity Factor Estimates for Power Dissipation Analysis
      11. 5.11 Summary
      12. References
      13. Further Research
    2. Chapter 6. Characteristics of Formal Equivalency Verification
      1. 6.1 RTL Combinational Model Equivalency
      2. 6.2 State Mapping for Equivalency
      3. 6.3 Combinational Logic Cone Analysis
      4. 6.4 Use of Model Input Assertions for Equivalency
      5. 6.5 Sequential Model Equivalency
      6. 6.6 Functional and Test-Mode Equivalence Verification
      7. 6.7 Array Equivalence Verification
      8. 6.8 Summary
      9. References
      10. Further Research
  13. Topic IV: Design Implementation
    1. Chapter 7. Logic Synthesis
      1. 7.1 Level of Hardware Description Language Modeling
      2. 7.2 Generation and Verification of Timing Constraints
      3. 7.3 Technology Mapping to the Cell Library
      4. 7.4 Signal Repowering and “High-Fan-out” Net Synthesis (HFNS)
      5. 7.5 Post-Synthesis Netlist Characteristics
      6. 7.6 Synthesis with a Power Format File
      7. 7.7 Post-Technology Mapping Optimizations for Timing and Power
      8. 7.8 Hold Timing Optimization
      9. 7.9 Clock Tree Synthesis (CTS)
      10. 7.10 Integration of Hard IP Macros in Synthesis
      11. 7.11 Low-Effort Synthesis (LES) Methodology
      12. 7.12 Summary
      13. References
      14. Further Research
    2. Chapter 8. Placement
      1. 8.1 Global Floorplanning of Hierarchical Units
      2. 8.2 Parasitic Interconnect Estimation
      3. 8.3 Cell Placement
      4. 8.4 Clock Tree Local Buffer Placement
      5. 8.5 Summary
      6. References
      7. Further Research
    3. Chapter 9. Routing
      1. 9.1 Routing Introduction
      2. 9.2 Global and Detailed Routing Phases
      3. 9.3 Back End Of Line Interconnect “Stacks”
      4. 9.4 Routing Optimizations
      5. 9.5 Summary
      6. References
      7. Further Research
  14. Topic V: Electrical Analysis
    1. Chapter 10. Layout Parasitic Extraction and Electrical Modeling
      1. 10.1 Introduction
      2. 10.2 Cell- and Transistor-Level Parasitic Modeling for Cell Characterization
      3. 10.3 Decoupling Capacitance Calculation for Power Grid Analysis
      4. 10.4 Interconnect Extraction
      5. 10.5 “Selected Net” Extraction Options
      6. 10.6 RLC Modeling
      7. 10.7 Summary
      8. References
      9. Further Research
    2. Chapter 11. Timing Analysis
      1. 11.1 Cell Delay Calculation
      2. 11.2 Interconnect Delay Calculation
      3. 11.3 Electrical Design Checks
      4. 11.4 Static Timing Analysis
      5. 11.5 Summary
      6. References
      7. Further Research
    3. Chapter 12. Noise Analysis
      1. 12.1 Introduction to Noise Analysis
      2. 12.2 Static Noise Analysis, Part I
      3. 12.3 Noise Impact on Delay
      4. 12.4 Electrical Models for Static Noise Analysis
      5. 12.5 Static Noise Analysis, Part II
      6. 12.6 Summary
      7. References
      8. Further Research
    4. Chapter 13. Power Analysis
      1. 13.1 Introduction to Power Analysis
      2. 13.2 Models for Switching Activity Power Dissipation
      3. 13.3 IP Power Models
      4. 13.4 Device Self-Heat Models
      5. 13.5 Design-for-Power Feedback from Power Analysis
      6. 13.6 Summary
      7. References
      8. Further Research
    5. Chapter 14. Power Rail Voltage Drop Analysis
      1. 14.1 Introduction to Power Rail Voltage Drop Analysis
      2. 14.2 Static I*R Rail Analysis
      3. 14.3 Dynamic P/G Voltage Drop Analysis
      4. 14.4 Summary
      5. References
      6. Further Research
    6. Chapter 15. Electromigration (EM) Reliability Analysis
      1. 15.1 Introduction to EM Reliability Analysis
      2. 15.2 Fundamentals of Electromigration
      3. 15.3 Power Rail Electromigration Analysis: powerEM
      4. 15.4 Signal Interconnect Electromigration Analysis: sigEM
      5. 15.5 Summary
      6. References
      7. Further Research
    7. Chapter 16. Miscellaneous Electrical Analysis Requirements
      1. 16.1 SleepFET Power Rail Analysis
      2. 16.2 Substrate Noise Injection and Latchup Analysis
      3. 16.3 Electrostatic Discharge (ESD) Checking
      4. 16.4 Soft Error Rate (SER) Analysis
      5. 16.5 Summary
      6. References
      7. Further Research
  15. Topic VI: Preparation for Manufacturing Release and Bring-Up
    1. Chapter 17. ECOs
      1. 17.1 Application of an Engineering Change
      2. 17.2 ECOs and Equivalency Verification
      3. 17.3 Use of Post-Silicon Cells for ECOs
      4. 17.4 ECOs and Design Version Management
      5. 17.5 Summary
      6. References
      7. Further Research
    2. Chapter 18. Physical Design Verification
      1. 18.1 Design Rule Checking (DRC)
      2. 18.2 Layout-Versus-Schematic (LVS) Verification
      3. 18.3 Electrical Rule Checking (ERC)
      4. 18.4 Lithography Process Checking (LPC)
      5. 18.5 DRC Waivers
      6. 18.6 Summary
      7. Further Research
    3. Chapter 19. Design for Testability Analysis
      1. 19.1 Stuck-at Fault Models and Automated Test Pattern Generation (ATPG)
      2. 19.2 DFT Design Rule Checking
      3. 19.3 Memory Built-in Self-Test (MBIST)
      4. 19.4 Logic Built-in Self-Test (LBIST)
      5. 19.5 Delay Faults
      6. 19.6 Bridging Faults
      7. 19.7 Pattern Diagnostics
      8. 19.8 Summary
      9. References
      10. Further Research
    4. Chapter 20. Preparation for Tapeout
      1. 20.1 Introduction to Tapeout Preparation
      2. 20.2 Foundry Interface Release Tapeout Options
      3. 20.3 Tapeout Checklist Review
      4. 20.4 Project Tapeout Planning
      5. Further Research
    5. Chapter 21. Post-Silicon Debug and Characterization (“Bring-up”) and Product Qualification
      1. 21.1 Systematic Test Fails
      2. 21.2 “Shmoo” of Performance Dropout Versus Frequency
      3. 21.3 Product Qualification
      4. 21.4 Summary
      5. Reference
      6. Further Research
  16. Epilogue
    1. Summary
  17. Index
3.19.31.73