Chapter 12

SPI Bus Projects

Abstract

The SPI (Serial Peripheral Interface) bus is one of the commonly used protocols to connect sensors and many other devices to microcontrollers. The SPI bus is a master-slave-type bus protocol. In this protocol, one device (the microcontroller) is designated as the master, and one or more other devices (usually sensors) are designated as slaves. In a minimum bus configuration there is one master and only one slave. The master establishes communication with the slaves and controls all the activity on the bus. This chapter presents the Nucleo-F411RE development board SPI bus GPIO pins. An SPI bus-based project is given in the chapter using a digital-to-analog converter chip.

Keywords

SPI; Mbed SPI functions; Nucleo-F411RE SPI ports; MISO; MOSI; SCK; CPOL; Square wave; Master-slave; DAC

12.1 Overview

In this chapter we shall be developing projects using the SPI (Serial Peripheral Interface) bus with the Nucleo-F411RE development board.

The SPI bus is one of the commonly used protocols to connect sensors and many other devices to microcontrollers. The SPI bus is a master-slave-type bus protocol. In this protocol, one device (the microcontroller) is designated as the master, and one or more other devices (usually sensors) are designated as slaves. In a minimum bus configuration there is one master and only one slave. The master establishes communication with the slaves and controls all the activity on the bus.

Fig. 12.1 shows an SPI bus example with one master and three slaves. The SPI bus uses three signals: clock (SCK), data in (SDI), and data out (SDO). The SDO of the master is connected to the SDIs of the slaves, and SDOs of the slaves are connected to the SDI of the master. The master generates the SCK signals to enable data to be transferred on the bus. In every clock pulse 1 bit of data is moved from master to slave, or from slave to master. The communication is only between a master and a slave, and the slaves cannot communicate with each other. It is important to note that only one slave can be active at any time since there is no mechanism to identify the slaves. Thus, slave devices have enable lines (e.g., CS) which are normally controlled by the master. A typical communication between a master and several slaves is as follows:

  •  Master enables slave 1.
  •  Master sends SCK signals to read or write data to slave 1.
  •  Master disables slave 1 and enables slave 2.
  •  Master sends SCK signals to read or write data to slave 2.
  •  The above process continues as required.
Fig. 12.1
Fig. 12.1 SPI bus with one master and three slaves.

The SPI signal names are also called MISO (Master in, Slave out), and MOSI (Master out, Slave in). Clock signal SCK is also called SCLK and the CS is also called SSEL. Mbed supports a number of functions for both master and slave SPI bus communication. In the SPI projects in this book the Nucleo-F411RE development board will be the master and one or more slaves will be connected to the bus. Since we will be programming the master only, a list of the functions available for the master nodes is presented in Table 12.1. The format function takes two arguments: data length and mode. The data length is usually 8 bits. The mode can have four values depending on the required clock polarity (CPOL) and clock phase (CPHA). CPOL and CPHA can have the following values:

Table 12.1

Mbed SPI Master Node Functions
FunctionDescription
formatConfigure the data transmission format
frequencySet the SPI bus frequency in Hz
writeWrite to a slave on the SPI bus and return response
CPOLClock Active State
0Clock active HIGH
1Clock active LOW
CPHAClock Phase
0Clock out of phase with data
1Clock in phase with data

The four SPI modes are as follows:

ModeCPOLCPHA
000
101
210
311

When creating an SPI bus variable we have to specify the GPIO pins for the MOSI, MISO, and SCLK. The default bus speed is 1 MHz (1,000,000 Hz), default data length is 8 bits, and the default mode is 0. The mode depends on the requirements of the slave device and the slave data sheet should be checked before a mode is selected.

12.2 Nucleo-F411RE SPI GPIO Pins

There are five SPI modules on the Nucleo-F411RE development board. The following are the GPIO pins for these modules:

SPI ModuleSignalGPIO Pin
SPI1SSELPA_15
SPI1SCLKPA_5
SPI1MISOPA_6
SPI1MOSIPA_7
SPI2MISOPC_2, PB_14
SPI2MOSIPC_3, PB_15
SPI2SSELPB_9, PB_12
SPI2SCLKPC_7, PB_13
SPI3MOSIPC_12, PB_5
SPI3SCLKPC_10, PB_3
SPI3MISOPC_11, PB_4
SPI3SSELPA_4
SPI4MOSIPA_1
SPI4MISOPA_11
SPI5SCLKPB_0
SPI5MISOPA_12
SPI5MOSIPB_8, PA_10
SPI5SSELPB_1

12.3 Project 1—Generating Square Wave

12.3.1 Description

In this project a DAC (digital-to-analog converter) chip is used to generate a square wave signal with a frequency of 1 kHz (period = 1 ms), 50% duty cycle, and an amplitude of 1 V. The DAC used is SPI bus compatible.

12.3.2 Aim

The aim of this project is to show how an SPI bus compatible device can be connected to the Nucleo-F411RE development board and also how it can be programmed using Mbed.

12.3.3 Block Diagram

The block diagram of the project is shown in Fig. 12.2.

Fig. 12.2
Fig. 12.2 Block diagram of the project.

12.3.4 Circuit Diagram

In this project the MCP4921-type SPI bus compatible DAC chip is used. MCP4921 is a 12-bit serial DAC manufactured by Microchip Inc., having the following basic specifications:

  •  12-bit resolution
  •  up to 20 MHz clock rate (SPI)
  •  fast settling time of 4.5 μs
  •  unity or 2 × gain output
  •  external Vref input
  •  2.7–5.5 V operation
  •  extended temperature range (− 40°C to + 125°C)
  •  8-pin DIL package

Fig. 12.3 shows the pin layout of the MCP4921. The pin definitions are as follows:

  • VDD, AVSS: power supply and ground
  • CS: chip select (LOW to enable the chip)
  • SCK, SDI: SPI bus clock and data in
  • VOUTA: analog output
  • VREFA: reference input voltage
  • LDAC: DAC input latch (transfers the input data to the DAC registers.
    • Normally tied to ground so that CS controls the data transfer.
Fig. 12.3
Fig. 12.3 Pin layout of MCP4921 DAC.

Fig. 12.4 shows the circuit diagram of the project. SPI2 module of the development board is used to interface with the DAC chip, where MOSI is pin PC_3 and SCLK is pin PC_7. The CS input of the DAC chip is connected to PC_0 of the development board. The output of the DAC is connected to a PC-based oscilloscope in order to record the generated waveform.

Fig. 12.4
Fig. 12.4 Circuit diagram of the project.

12.3.5 The Construction

The project was constructed on a breadboard as shown in Fig. 12.5 and connections were made to the development board using jumper wires.

Fig. 12.5
Fig. 12.5 Project constructed on a breadboard.

12.3.6 The PDL

Fig. 12.6 shows the program PDL.

Fig. 12.6
Fig. 12.6 Program PDL.

12.3.7 The Program Listing

The digital input of a DAC converter can either be in serial or parallel form. In a parallel converters the width of digital input is equal to the width of the converter. For example, a 12-bit converter has 12 input bits. Serial converters in general use the SPI or the I2C bus and basically a clock and a data signal are used to send data to the converter. Parallel converters provide much faster conversion times but they are housed in larger packages. The DACs are manufactured as either unipolar or bipolar as far as the output voltages are concerned. Unipolar converters can provide only positive output voltages, whereas bipolar converters provide both positive and negative voltages. In this book we will be using only unipolar converters.

The relationship between the digital input-output and the voltage reference is given by

Vo = DVref/2n

where Vo is the output voltage, Vref the reference voltage, D the digital data, and n is the width of the converter. For example, in a 12-bit converter (resolution = 12-bits) with + 3.3 V reference voltage,

Vo = 3.3D/212 = 0.805 DmV

Thus, for example, if the input digital value is 1, the analog output voltage will be 0.805 mV, if the input value is 2, the analog output voltage will be 1.61 mV, and so on.

The program listing (program: SPIDAC) of the project is shown in Fig. 12.7. At the beginning of the program SPI channel 2 is assigned to variable dac and PC_0 (CS of the DAC chip) is configured as an output. Inside the main program, assuming a reference voltage of 3.3 V, variable amplitude is set to 1 V (1000 mV) and the DAC chip is disabled. The remainder of the program runs in an endless loop. Inside this loop function DAC is called and variable amplitude is sent as an argument to the function so that 1 V analog signal is output from the DAC. Then 0.5 ms delay is inserted and 0 is sent to the DAC chip with again 0.5 ms delay so that the Duty Cycle of the signal is 50%. The loop is repeated until stopped by the user.

Fig. 12.7
Fig. 12.7 Program listing.

Function DAC writes data to the DAC chip. Data is written to the DAC in two bytes. The HIGH byte is sent first followed by the LOW byte. The lower byte specifies bits D0:D8 of the digital input data. The upper byte consists of the following bits:

  • D8:D11: bits D8:D11 of the digital input data
  • SHDN: 1, output power down mode; 0, disable output buffer
  • GA: output gain control. 0, gain is 2 ×; 1, gain is 1 ×
  • BUF: 0, input unbuffered; 1, input buffered
  • A/B: 0, write to DACA; 1, write to DACB (MCP4921 supports only DACA)

Data is written to the DAC chip over the SPI bus using function dac.write.

Fig. 12.8 shows the generated output waveform on the oscilloscope.

Fig. 12.8
Fig. 12.8 Output waveform.

12.3.8 Suggestions for Additional Work

Modify the program shown in Fig. 12.6 to generate a sawtooth waveform.

12.4 Summary

In this chapter we have learned about the following:

  •  SPI bus
  •  Mbed SPI bus functions
  •  A project using an SPI compatible device

12.5 Exercises

  1. 1. Explain the signals used in the SPI bus.
  2. 2. Draw a table comparing the advantages and disadvantages of using SPI bus instead of I2C bus.
  3. 3. The Nucleo-F411RE development board is to be connected to three SPI bus slave sensors. Draw the circuit diagram of this project.
  4. 4. What are the limitations for connecting devices to the SPI bus?
  5. 5. Explain the Mbed functions that can be used in SPI bus-based projects.
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