Computer Architecture and Organization (From 8085 to Core2Duo and beyond)
by Subrata Ghosal
Computer Architecture and Organization
- Computer Architecture and Organization (From 8085 to Core2Duo and beyond)
- Copyright
- Dedication (1/5)
- Dedication (2/5)
- Dedication (3/5)
- Dedication (4/5)
- Dedication (5/5)
- Preface
- Acknowledgements
- About the Author
- Chapter 1:Introduction
- Chapter 2: Overview of Computer
- Chapter 3: Fundamentals of Digital Logic Circuits
- Chapter 4: Computer Arithmetic
- 4.1 INTRODUCTION
- 4.2 ADDITION AND SUBTRACTION
- 4.3 MULTIPLICATION ALGORITHMS
- 4.4 BOOTH'S ALGORITHM (1/2)
- 4.4 BOOTH'S ALGORITHM (2/2)
- 4.5 DIVISION ALGORITHMS
- 4.6 DIVISION OF SIGNED INTEGERS
- 4.7 FLOATING-POINT NUMBER REPRESENTATION (1/2)
- 4.7 FLOATING-POINT NUMBER REPRESENTATION (2/2)
- 4.8 FLOATING-POINT ARITHMETIC AND UNIT OPERATIONS
- 4.9 PIPELINED ALU
- SUMMARY
- POINTS TO REMEMBER
- QUICKSAND CORNER
- REVIEW QUESTIONS
- Chapter 5: Processor Basics
- 5.1 INTRODUCTION
- 5.2 PROCESSOR ARCHITECTURE AND ORGANIZATION
- 5.3 PROCESSOR OPERATION
- 5.4 REGISTER SET
- 5.5 STACK ORGANIZATION
- 5.6 INTERRUPTS
- 5.7 INTEL 8085 MICROPROCESSOR (1/2)
- 5.7 INTEL 8085 MICROPROCESSOR (2/2)
- 5.8 INTEL 8086 MICROPROCESSOR (1/3)
- 5.8 INTEL 8086 MICROPROCESSOR (2/3)
- 5.8 INTEL 8086 MICROPROCESSOR (3/3)
- 5.9 INTEL 8051 MICROCONTROLLER
- 5.10 RISC AND CISC PROCESSORS
- 5.11 INTEL 80386 PROCESSOR (1/2)
- 5.11 INTEL 80386 PROCESSOR (2/2)
- 5.12 INTEL PENTIUM 4 PROCESSOR (1/2)
- 5.12 INTEL PENTIUM 4 PROCESSOR (2/2)
- SUMMARY
- POINTS TO REMEMBER
- QUICKSAND CORNER
- REVIEW QUESTIONS
- Chapter 6: Instruction Set and Assembly Language Programming
- 6.1 INTRODUCTION
- 6.2 HIGH LEVEL, ASSEMBLY AND MACHINE LANGUAGE
- 6.3 FUNCTIONS AND CHARACTERISTICS OF INSTRUCTIONS
- 6.4 ADDRESSING MODES (1/2)
- 6.4 ADDRESSING MODES (2/2)
- 6.5 INSTRUCTION FORMATS AND FIELDS
- 6.6 8085 INSTRUCTION SET
- 6.7 8086 INSTRUCTION SET
- 6.8 8051 INSTRUCTION SET
- 6.9 ASSEMBLY LANGUAGE PROGRAMMING
- 6.10 ASSEMBLER
- 6.11 INTEL 80386 PROCESSOR
- 6.12 INTEL PENTIUM 4 PROCESSOR
- 6.13 SOLVED EXAMPLE
- SUMMARY
- POINTS TO REMEMBER
- QUICKSAND CORNER
- REVIEW QUESTIONS
- Chapter 7: The Memory System
- 7.1 INTRODUCTION
- 7.2 MEMORY CLASSIFICATION
- 7.3 MEMORY CHARACTERISTICS AND HIERARCHY
- 7.4 CACHE MEMORY (1/3)
- 7.4 CACHE MEMORY (2/3)
- 7.4 CACHE MEMORY (3/3)
- 7.5 MAIN MEMORY
- 7.6 SECONDARY MEMORY
- 7.7 VIRTUAL MEMORY
- 7.8 MEMORY MANAGEMENT
- 7.9 INTEL 80386 MEMORY ORGANIZATION
- 7.10 PENTIUM 4 MEMORY ORGANIZATION
- 7.11 MEMORY DECODING
- SUMMARY
- POINTS TO REMEMBER
- QUICKSAND CORNER
- REVIEW QUESTIONS
- Chapter 8: Input / Output Organization
- 8.1 INTRODUCTION
- 8.2 BASIC INPUT/OUTPUT STRUCTURE OF COMPUTERS
- 8.3 ASYNCHRONOUS DATA COMMUNICATION
- 8.4 SERIAL AND PARALLEL COMMUNICATIONS
- 8.5 PROGRAMMED I/O (POLLING)
- 8.6 INTERRUPT DRIVEN I/O
- 8.7 INTERRUPT CONTROLLER (8259)
- 8.8 DMA
- 8.9 DEVICE DRIVERS
- 8.10 STANDARD I/O INTERFACES (BUSES) (1/2)
- 8.10 STANDARD I/O INTERFACES (BUSES) (2/2)
- 8.11 BUS ARBITRATION
- 8.12 I/O PROCESSOR
- 8.13 SOLVED EXAMPLE
- SUMMARY
- POINTS TO REMEMBER
- QUICKSAND CORNER
- REVIEW QUESTIONS
- Chapter 9: Microprogramming and Microarchitecture
- 9.1 INTRODUCTION
- 9.2 PROBLEM OF ALLOWING DATA-FLOW (1/2)
- 9.2 PROBLEM OF ALLOWING DATA-FLOW (2/2)
- 9.3 INSTRUCTION CYCLES OF A PROCESSOR
- 9.4 HARDWIRED CONTROL
- 9.5 PROGRAMMED CONTROL
- 9.6 SEQUENCING AND EXECUTION OF MICROINSTRUCTIONS
- 9.7 SOLVED EXAMPLE
- 9.8 UTILIZING SYSTEM CLOCK
- 9.9 PROCESSOR DATA PATH DESIGN
- 9.10 SOLVED EXAMPLE
- SUMMARY
- POINTS TO REMEMBER
- QUICKSAND CORNER
- REVIEW QUESTIONS
- Chapter 10: Control Unit Operation
- 10.1 INTRODUCTION
- 10.2 CONTROL UNIT (CU)
- 10.3 MICRO-OPERATIONS (1/2)
- 10.3 MICRO-OPERATIONS (2/2)
- 10.4 CONTROL OF THE PROCESSOR
- 10.5 HARDWARE IMPLEMENTATION
- 10.6 SOLVED EXAMPLES (1/5)
- 10.6 SOLVED EXAMPLES (2/5)
- 10.6 SOLVED EXAMPLES (3/5)
- 10.6 SOLVED EXAMPLES (4/5)
- 10.6 SOLVED EXAMPLES (5/5)
- SUMMARY
- POINTS TO REMEMBER
- QUICKSAND CORNER
- REVIEW QUESTIONS
- Chapter 11: Operating System
- Chapter 12: Pipelining
- Chapter 13: Parallel Processing and Super-Scalar Operation
- Chapter 14: Embedded Systems
- Chapter 15: Computer Peripherals
- Appendix A: Number Systems
- Appendix B: SPARC and UltraSPARC
- Appendix C: Power PC
- Appendix D: Intel Core2Duo
- Appendix E: MIPS R4000
- Appendix F: Project Bank
- Answers for Target the Correct Option
- Glossary (1/2)
- Glossary (2/2)
- Acronyms
- Bibliography
- Index (1/2)
- Index (2/2)
Computer Architecture
and Organization
(From 8085 to Core2Duo and beyond) (From 8085 to Core2Duo and be
y
ond)
Subrata Ghoshal
Professor and Head, Information Technology Department
Sikkim Manipal Institute of Technology, Sikkim
Delhi • Chennai • Chandigarh
A01_GHOS1557_01_SE_FM.indd iA01_GHOS1557_01_SE_FM.indd i 5/3/11 2:02 PM5/3/11 2:02 PM
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