Input / Output Organization 263
As the number of any type of peripheral devices increased, dedicated I/O controllers came into play
releasing the processor from the duty of looking after serial communication, multiple interrupt handling
and so on. The interfacing bus also became more sophisticated and versatile to look after various types
of peripheral devices and, thereby, we encounter different types of bus controllers. We have discussed
all these I/O interfacing issues in earlier sections of this chapter.
With the increasing demand of time, system designers decided to release the main processor from
the burden of looking after I/O operations by incorporating a dedicated I/O processor in the system.
The idea is very much similar to the idea of providing a dedicated math–coprocessor along with the
processor. Note that, although the ALU of any processor is capable of looking after arithmetic opera-
tions, a math–coprocessor releases the processor’s ALU from the responsibilities of carrying out these
mathematical calculations, which is very frequent during execution of any software.
Conceptually, these I/O processors share the same main memory of the system along with some extra
amount of memory dedicated specially for these I/O processors. To implement I/O operations, the main
processor sends related commands to the I/O processor and thereafter the I/O processor takes over the
duty of completion of further I/O communications.
8.13 SOLVED EXAMPLE
Problem 8.1
To establish a serial communication between a host and a peripheral, a baud rate of 9600 bps was
selected. If only one stop bit was used in the serial data transmission format, how many bytes are trans-
mitted within a second?
Solution 8.1
With one-start-bit and one-stop-bit, the number of bits transmitted per byte would be 10 (in decimal).
Therefore, the number of bytes transmitted per second would be 9600/10 = 960.
SUMMARY
One of the major responsibilities of any computer is to communicate with the external world, which is car-
ried out through its I/O sub-system composed of various I/O devices. These I/O devices are placed at differ-
ent layers and the innermost layer shares the system bus of the processor. Sometimes, this bus is designated
as the I/O bus as memory devices and are interfaced with the processor through a separate bus designated
as the memory bus, for uninterrupted high-speed data communication, essential for instruction execution.
In general, one of the three techniques, namely polling (programmed I/O), interrupt driven I/O and
DMA is used for data communication with I/O devices. Polling demands maximum attention of the
processor, while interrupt driven method frees the processor from such attention. When the quantity of
data is larger, DMA is preferred.
Depending upon its characteristics, data communication may be classi ed as synchronous or asyn-
chronous, serial or parallel and also simplex, full-duplex and half-duplex. Handshaking signals are
essential for asynchronous communication, which is adopted for devices operating under different clock
frequencies. Peripheral devices (ICs), e.g., 8255, are used for asynchronous parallel communication,
while UARTs, e.g., 8251, are used for asynchronous serial communication. Priority interrupt control-
lers, e.g., 8259, are used to look after multiple peripheral devices requesting for processor’s atten-
tion through their interrupts, and the processor offers only one external interrupt request input facility.
Devices like 8237 are used for DMA operation.
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