Microprogramming and Microarchitecture 277
this stage the reader would be con dent enough to investigate Table 9.5 . We shall discuss little later
how these sequencing need to be produced and the necessary control signals generated. At present, we
should complete the discussions on instruction fetching, which we have set aside previously.
Instruction 1 2 3 4 5 6 7 8 9 10
Subtract
R0 from A
ENX
0 = 0
S3
1 to 0
S3
0 to 1
S1 = 1 S2 1 to 0 S2
0 to 1
S4 = 0 S5
1 to 0
S5
0 to 1
S4 = 1
Subtract
R1from A
ENX
1 = 0
S3
1 to 0
S3
0 to 1
S1 = 1 S2 1 to 0 S2
0 to 1
S4 = 0 S5
1 to 0
S5
0 to 1
S4 = 1
Subtract R2
from A
ENX
2 = 0
S3
1 to 0
S3
0 to 1
S1 = 1 S2 1 to 0 S2
0 to 1
S4 = 0 S5
1 to 0
S5
0 to 1
S4 = 1
Subtract R3
from A
ENX
3 = 0
S3
1 to 0
S3
0 to 1
S1 = 1 S2 1 to 0 S2
0 to 1
S4 = 0 S5
1 to 0
S5
0 to 1
S4 = 1
Explanation
of steps
Enable
target
register
Latch
data
in X
Reset
S3
For sub-
tracting
Latch ALU
output in Y
Reset
S2
Enable
Y
Latch
result
in A
Reset
S5
Disable
Y
Table 9.5 Micro-steps for subtracting a register from accumulator
9.3 INSTRUCTION CYCLES OF A PROCESSOR
So far in our discussions, we have assumed that the relevant instruction is present within the instruction
register (IR) of our imaginary processor. However, as we know from our discussions in Chapter 5, the
processor continuously fetches and then executes instruction after instruction from external memory
(primary memory). Therefore, we may say that the processor is continuously executing in a closed-loop,
which is composed of fetch, decode and execute instructions. Apart from these operations, we must not
forget the fourth one, reacting to an interrupt. As a matter of fact, this reaction against any interrupt is
nothing but again fetching another instruction from a special address or vector address, dedicated for
that interrupt. Therefore, the major or simpli ed duty-cycle of a processor may pictorially be presented
as it is shown in Figure 9.4 .
Note that this duty cycle of processor is a simpli ed one. Why do we say so? It is because we have
not considered the complexity of fetching any eventual operand from memory, which may be necessary
to execute some instructions. This requirement may only be understood after decoding an instruction.
Special cases like conditional and unconditional branching and reaction against any subroutine call are
also avoided in the owchart. The wait state generation procedure of a processor is also not considered
here. Moreover, all process protocols for DMA related operations are also eliminated.
By this time, it must be clear to the reader that the design of control signals is merely a mat-
ter of details. It is insisted that students should first prepare a check list and then take up the
detailed design of signals. This would save a lot of precious time.
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