342 Computer Architecture and Organization
Data paths are necessary for the CU to transfer data contained in different registers of the proces-
sor to other registers as and when necessary. Optimization in data path design leads to optimization of
necessary control signals. For proper functioning, registers are generally buffered through tristate buf-
fers, which are controlled by the CU through its control signals. Latching of data within any register
is generally accomplished by the system clock signal. For hardwired CU, Boolean expressions of each
control signal is derived from the input clock sequences and the demand from the opcode of the related
instruction.
POINTS TO REMEMBER
R All internal registers of a processor are equipped with tristate buffers, which may be enabled or dis-
abled by the CU to allow or disallow the communication with the register.
R A hardwired CU functions faster at the expense of its complexity in design.
QUICKSAND CORNER
Design of a CU is the most challenging part for
any processor design. For a CISC processor it
becomes more complex than a RISC processor.
Finally, the inclusion of provision of backward
compatibility increases this complexity manifold.
For an external observer the CU allows some data
ow or its storage at certain locations. However,
maintaining the sequence and optimizing the
number of control signals leads to an ef cient
data path design. Finally, we nd that the whole
design is oriented by the instruction set and pro-
cessor architecture. It is needless to mention that a
well planned instruction set format helps to a great
extent in the design of any ef cient control unit.
REVIEW QUESTIONS
Target the Correct Option
1. Which of the following components of any
processor is responsible for proper function-
ing of the processor?
(a) ALU (c) Accumulator
(b) Control unit (CU) (d) none of these
2. Which one of the following is not a micro-
operation?
(a) Perform an ALU operation.
(b) Allow data within a register to a bus
(c) Service an interrupt
(d) None of these
3. Which one of the following is not considered
to be an input for a control unit (CU)?
(a) System clock (c) Flag-bits
(b) Power in (Vcc) (d) none of these
4. The abbreviation MBR stands for
(a) Memory buffer register
(b) Minor boolean recti cation
(c) Maximum bene t recognized
(d) none of these
5. Which of the following statements is true?
(a) IR is always loaded from MAR
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Control Unit Operation 343
(b) PC contains the address of next instruction
(c) There is no communication between MBR
and IR.
(d) none of these
6. Communication with an I/O port (port read or
port write) is generally conducted during the
(a) fetch cycle (c) execute cycle
(b) indirect cycle (d) none of these
7. At the end of any interrupt cycle, the cycle
code (CC) for the control unit is always set as
(a) fetch cycle (c) execute cycle
(b) indirect cycle (d) none of these
8. Due to minimization of the number of data
paths the number of
(a) enabling signals increases
(b) latching signal increases
(c) both of these
(d) none of these
9. If a register is interfaced with a bidirectional
data path so that the data might be read from
or written within the register, then the register
should be equipped with
(a) one bidirectional buffer
(b) two bidirectional buffers
(c) one bidirectional tristate buffer
(d) none of these
10. For the implementation of a hardwired con-
trol unit, the processor depends on
(a) related Boolean expressions
(b) transistor based hardware circuit
(c) both of these
(d) none of these
Find in Few Seconds
1. What are the major functional blocks of a
processor?
2. What is the role of the control unit (CU) for
a processor?
3. What is meant by micro-operation ?
4. Which register of the processor is directly
connected with its external address bus?
5. What are the good practices for designing
data paths?
6. What is the purpose of an indirect cycle ?
7. What is the harm in recognizing interrupts at
the beginning of an instruction cycle?
8. What is the role of cycle code (CC) for the
performance of a control unit?
9. What are the advantages and disadvantages of
using the system clock as the latching signal?
10. Why it is dif cult to implement a hardwired
control unit for modern CISC processors?
Spend Some Time Here
1. “In many cases, this CU design is governed
by one important factor, compatibility with
previous processors of the series”. Justify the
statement.
2. Is there any role of the control unit (CU) dur-
ing the reset state of a processor? If yes then
what is that role?
3. How the program counter (PC) is incremented
by one during a fetch cycle? Is there any role
of the ALU during this cycle?
4. Is it true that the content of MAR is always
copied from PC?
5. Under what condition(s) two micro-operations
may be combined to be executed during the
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344 Computer Architecture and Organization
same time-slice? What would be the dif culty
if they are executed at different time-slices
instead of the same time-slice?
6. Why the execution time of an execute cycle
is unpredictable? Can it, theoretically, be
stretched to in nity? Justify your answer.
7. Is it possible for a control unit to function
properly without using any cycle code (CC)?
Justify your answer.
8. Make a list of external control signals of Intel
8085 processor which are directly handled (as
either input or output) by its control unit.
9. Identify the micro-operations necessary for
Intel 8085 processor to handle its multiplexed
address-data bus.
10. Design a data path for the problem of Q9.
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