Pipelining 387
Next two stages, indicated as Trace Cache Fetch gathers the decoded micro-operations guided by
branch prediction strategy from the instruction decoder and places in sequence of micro-operations
designated as traces.
The decoded micro-operations are then shifted to rename/allocation module by the drive stage. Here,
the out-of-order execution logic is implemented and micro-operations are reordered and if necessary,
register renaming takes place. Note that the processor contains several hidden registers not accessible
to the programmer but by the control unit of the processor. After this stage they are shifted to the micro-
operation queue, where scheduling and dispatching are taken into account.
Next comes the execution units and the microinstructions are executed in parallel as per their dis-
patching and scheduling. Finally, the branch prediction tables are updated if necessary along with the
branch history ags. Results of executions are then stored in related registers taking care of out-of-order
execution so that nal results are correct.
SUMMARY
Pipeline architecture is implemented in modern processors to make it work faster by working with more
than one instruction concurrently. The number of sub-divisions of an instruction, such as fetch, decode,
execution and so on., determines the stage of pipeline. A 2-stage pipeline sub-divides an instruction in
two parts and a 5-stage pipeline sub-divides it in ve parts.
This concurrent execution of several sub-divisions of instructions within the processor may generate
various types of hazards, most important of which are data hazards, instruction hazards and structural
hazards. Data hazards generally arise out of data dependence, that is, the result of one operation is to be
treated as the operand of the next instruction. This may be avoided by providing a special forwarding
path between the result register of the ALU and its input registers.
Instruction hazards might arise due to cache-miss or conditional branching of instructions. The rst
one may be eliminated by providing an instruction queue, while the second one may be solved by adopt-
ing a suitable algorithm for branch prediction.
Structural hazards generally evolve due to concurrent memory access for data storage and access,
like storing a result and loading an operand. Separate data paths are generally provided to eliminate this
problem. These are the architectural and organizational specialties of the pipeline architecture.
To enhance the pipeline performance, certain techniques, like out-of-order execution, register renam-
ing and speculative execution are implemented in pipelines of modern processors, like Pentium 4. In
the case of out-of-order execution, instructions are fetched in the same order as that in original static
program and nal result of execution of every instruction is also stored in the same order. However,
during execution phases the sequence is changed as per the decision of the scheduler maintaining the
data dependency and other factors.
Many advanced features of P4 like hyper-threading and so on, are not discussed here. Inter-
ested reader may refer to manufacturer’s data sheets for relevant information.
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