388 Computer Architecture and Organization
Most modern processors have some hidden registers available to the processor only and by using
these registers in place of registers indicated by the program, speed of pipeline execution is enhanced.
This technique is known as register renaming. In the case of speculative execution, some instructions
are executed much before their real execution time, expecting that at a later stage these results would be
necessary for the pipeline.
Pentium 4 has a 20-stage pipeline and it decodes and translates all its CISC-like instructions to RISC-
like simple micro-codes and places within its trace-cache before placing within its pipeline. Because a
smaller number of microinstructions are involved, the execution speed is enhanced.
POINTS TO REMEMBER
R A pipelined processor stalls whenever any operation consumes more than its stipulated time-slice.
R Data hazards are primarily due to data dependency.
R Instruction hazards may be due to cache-miss or conditional branching instructions.
R Pipeline architecture demands additional data paths and data storage buffers for concurrent opera-
tions of different instructions during the same time-slice.
QUICKSAND CORNER
The basic aim of pipelined architecture is to speed
up the execution of instructions by concurrent
processing of different cycles related to it. Pipe-
line does not mean just to maintain an instruction
queue or fetching opcode during execution of the
previous opcode. It means a well-planned archi-
tecture and related organization for hazard-free
implementation of uninterrupted data ow, which
is the backbone of pipeline architecture.
Therefore, design of data paths and data stor-
age plays the critical role for it demanding maxi-
mum attention from its designers. Unless all these
are meticulously planned, the goal of implement-
ing pipeline technique may not be achieved.
REVIEW QUESTIONS
Target the Correct Option
1. How many stages are there in the car-manu-
facturing assembly line shown in Figure 12.2 ?
(a) 3 (c) 5
(b) 4 (d) none of these
2. Ideally, the speed of instruction execution for
a two-stage pipelined processor in compari-
son with that of a similar processor but with-
out any pipeline is expected to be
(a) half (c) double
(b) same (d) none of these
3. A control-hazard may occur because of
(a) failure of a control signal
(b) non-availability of an instruction on time
(c) presence of multiple control signals
(d) none of these
4. The hazard due to data dependency may be
solved using hardware method by
(a) providing operand forwarding paths
between the result register and input reg-
isters of the ALU.
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Pipelining 389
(b) incorporating a temporary result register
with ALU.
(c) decomposing ALU into two parts
(d) None of these
5. An instruction queue helps to
(a) eliminate disorder in execution of instruc-
tions
(b) reduce the time of instruction fetch
(c) eliminate instruction hazards related with
cache-miss.
(d) none of these
6. A four-stage branch prediction algorithm
would need
(a) 4 bits for correct prediction
(b) 8 bits for correct prediction
(c) 16 bits for correct prediction
(d) None of these
7. Branch-prediction method depends on
(a) statistical method
(b) past history of branching
(c) random decisions
(d) None of these
8. The most likely reason behind the structural
hazard is
(a) error in program structure
(b) error in data structure
(c) error in compiler’s structure
(d) none of these
9. Which of these following features is essential
for any pipelined processor?
(a) Separate instruction and data cache within
the processor
(b) Separate instruction queue
(c) Both of these
(d) None of these
10. Which one of the following statements is
incorrect?
(i) On an average in pipelined processors
at every clock cycle one instruction is
executed.
(ii) Data-flow visualization is the key aspect
behind the design of any pipelined
processor.
(iii) It is dif cult to implement pipeline archi-
tecture for CISC processors.
(a) (i) (c) (iii)
(b) (ii) (d) none of these
Find in Few Seconds
1. In how many ways a processor may be trans-
formed to work faster than its usual speed of
instruction execution?
2. What is the basic rule of making any pipeline
architecture an ef cient one?
3. Make a list and then explain each operation
for a ve-stage pipeline.
4. What is meant by hazard in pipeline architec-
ture? How many types of hazards are gener-
ally encountered? In which way they might be
reduced?
5. How the hazard arising out of data depen-
dency may be solved by software method?
6. What is the relation between a data hazard
and an I/O wait?
7. How any conditional branching operation
might be predicted ?
8. How structural hazards in pipeline might be
recti ed?
9. Is it possible that data hazards, instruction
hazards and structural hazards might be
encountered simultaneously?
10. Is the cache memory a must for any pipelined
architecture?
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390 Computer Architecture and Organization
Spend Some Time Here
1. Is the pipeline architecture applicable only for
the RISC architecture? Justify your answer.
2. What may be the maximum number of stages
in a pipeline architecture?
3. Why do we need more number of buffers in
pipeline architecture?
4. What is the difference between stalling and
hazards ?
5. Considering that the following operational
instructions are placed in the same order as
they appear here, what would happen for
(a) a two-stage pipelined processor, and
(b) a ve-stage pipelined processor?
P ← P – 7
M ← M/4
P ← M* P
6. The hazard due to data dependency may be
solved either through hardware or by software.
What are the relative merits and demerits in
either case?
7. Just like a conditional branching instruction,
a CALL instruction also disturbs the sequen-
tial fetch operation of any processor. How this
problem may be solved in case of a pipelined
processor?
8. Is it possible that the reason behind some struc-
tural hazard is related with some I/O operation?
9. At the beginning of Section 12.7, a list of
eight points are present, which are related
with a ve-stage pipeline. Is that list going to
change if it is meant for a two-stage pipeline?
If yes then how?
10. Why in Figure 12.7 (b) and in Figure 12.11
two forwarding paths are shown from the
result register of the ALU? What would be
the problem if only one path is provided? In
which conditions both of these paths would
be simultaneously used by a processor?
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