408 Computer Architecture and Organization
QUICKSAND CORNER
Parallel processing is a synthesis of hardware and
software. Inter-connecting several powerful pro-
cessors and allowing each of these processors to
have individual memory modules is only half of the
story. All these exercises are meaningless unless the
software part is properly handled to keep all proces-
sors simultaneously busy. This demands extensive
planning for both micro as well as macro levels.
In general, we are accustomed to develop soft-
ware with sequential arrangement of instructions
to be executed by one processor. At the time of
software development, we rarely think about
independency of its different modules so that they
might be processed in parallel. Entrusting this job
to compiler or the operating system may not be
helpful, in most of the cases. Therefore, parallel
processing demands a different viewpoint at the
time of development of software to be executed by
this special technique.
REVIEW QUESTIONS
Target the Correct Option
1. The difference between multi-processing and
distributed processing is that
(a) in the rst case several processors are
interconnected while in the second case
several computers are inter-connected.
(b) in the rst case it deals with shared mem-
ory while in the second case it has indi-
vidual memory.
(c) both of above.
(d) none of these
2. The following con guration of MIMD is des-
ignated as:
(a) distributed memory (c) NUMA
system
(b) UMA (d) none of these
3. In the single bus topology the interconnecting
path is bidirectional whereas in case of ring
topology, the interconnecting path is
(a) parallel (c) unidirectional
(b) serial (d) none of these
4. The maximum possible number of connec-
tions within any box for multi-stage topology
may be
(a) one (c) three
(b) two (d) none of these
5. The maximum number of possible nodes in a
hypercube con guration may be
(a) eight (c) thirty two
(b) sixteen (d) none of these
Memory
Processor Processor Processor
Interconnections
Memory Memory
POINTS TO REMEMBER
R The most critical task in parallel processing is to subdivide the program so that its parts may be
executed concurrently by different processors.
R Utmost care is necessary in dealing with shared variables in case of parallel processing.
R L1 cache is a must for super-scalar operation.
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Parallel Processing and Super-Scalar Operation 409
6. Lock-bits for memory are helpful for
(a) shared variables (c) both of these
(b) mixed topology (d) none of these
7. In case of write-through process, the main
memory is updated
(a) at a convenient time after updating cache.
(b) simultaneously with the cache
(c) Never
(d) None of these
8. In case of super-scalar operation, the number of
instruction fetched in every clock cycle must be
(a) one (c) two
(b) greater than one (d) none of these
9. Which of the following statements is true?
(i) L1 cache must not be present in super-scalar
operation.
(ii) L1 cache may or may not be present in
super-scalar operation.
(iii) L1 cache is a must for super-scalar opera-
tion.
(a) (i) (c) (iii)
(b) (ii) (d) none of these
10. Array processing is a form of
(a) SISD (c) MIMD
(b) SIMD (d) none of these
Find in Few Seconds
1. What is meant by Flynn’s classi cation?
Explain with suitable examples.
2. In how many different forms the MIMD
architecture might be implemented? Brie y
explain the specialty of each of them.
3. What is the difference between crossbar and
multi-stage topologies?
4. How the relative ef ciency of the tree topology
is enhanced by adopting a fat tree topology?
5. What is meant by program parallelism ?
Explain with a suitable example.
6. What are the precautions to be taken in case
of dealing with shared variables?
7. What is meant by critical section ? What pro-
cedure to be followed to deal with it?
8. What is meant by cache coherence? How it
may be solved?
9. What are the similarities and differences
between super-scalar operation and parallel
processing?
10. What is the utility of array processing?
Explain with an example.
Spend Some Time Here
1. Explain the reason behind non-applicability of
MISD con guration of Flynn’s classi cation.
2. If there are 2N processors, interconnected
through crossbar topology, would it be possible
to allow N simultaneous transactions between
processor pairs, if no processor is communicat-
ing with more than one other processor?
3. Why the two-dimensional mesh topology is
considered to be better than n-dimensional
hypercube topology?
4. Why the implementation of mixed topol-
ogy improves the ef ciency of any network?
Explain with an example.
5. Is there any program parallelism exist-
ing in a subroutine meant for clearing all
elements of a 2-D matrix? Justify your
answer.
6. Why super-scalar operation is not designated
as parallel processing?
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410 Computer Architecture and Organization
7. How multiple execution units help in super-
scalar operation?
8. With neat sketches explain the execution
sequence of any four successive instructions
in super-scalar operation.
9. How the basic I/O scheme may be imple-
mented in case of super-scalar operation?
10. In Figure 13.12 depicting the schematic of
array processing, it is shown that smaller pro-
cessing units are interconnected through bus,
in form of a mesh. Is it possible to implement
these interconnections through wireless, like
Bluetooth? Justify your answer.
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