460 Computer Architecture and Organization
UltraSPARC offers a total of 92 instructions including oating point instructions and restricts its mem-
ory oriented instructions as minimum as possible. This had been achieved by offering a larger set of
internal registers, 136 in total, out of which 32 registers are available at any time through the selected
register window. Out of these 32 registers, the lowest eight registers are designated as global and other
three sets may have inputs, outputs and local variables.
All instructions of UltraSPARC are 32-bit in length and with a total of four instruction formats it is
able to perform data move and data load, arithmetic and logical, conditional and unconditional branch
and all other operations.
POINTS TO REMEMBER
R UltraSPARC is a 64-bit RISC processor with 9-stage pipeline and separate ALUs for integer and
oating point operations.
R The selected register window would always contain lowest eight global registers and other 24 select-
able registers.
R SETHI instruction helps to load 32-bit immediate data by preloading most signi cant 22 bits of it.
REVIEW QUESTIONS
Target the Correct Option
1. Which of the following statements is correct?
(a) UltraSPARC is a 32-bit 9-stage pipelined
CISC processor.
(b) UltraSPARC is a 64-bit processor back-
ward compatible with 32-bit SPARC.
(c) UltraSPARC uses MMX technology for
visual data processing.
(d) None of these
2. Before adopting SPARC, Sun workstations
were operated by
(a) Motorola 68xxx (c) UltraSPARC
(b) Pentium Pro (d) none of these
3. In the 787-pin PGA package of UltraSPARC,
the number of data lines offered is
(a) 64 (c) 256
(b) 128 (d) none of these
4. The L1 instruction cache of UltraSPARC
processor is
(a) directly mapped
(b) two-way set associative
(c) eight-way set associative
(d) none of these
5. The number of general purpose registers in
UltraSPARC is
(a) 64 (c) 136
(b) 128 (d) None of these
6. Apart from eight global registers, the num-
ber of general purpose registers available
through any selected register window of
UltraSPARC is
(a) 8 (c) 24
(b) 16 (d) none of these
7. The prefetch/dispatch module of Ultra-
SPARC has a branch-prediction module
which uses
(a) 1-bit branch-prediction algorithm
(b) 2-bit branch-prediction algorithm
(c) 4-bit branch-prediction algorithm
(d) none of these
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SPARC and UltraSPARC 461
Find in Few Seconds
8. Stage 6 (marked as P1) and Stage 7 (marked
as P2) of integer pipeline of UltraSPARC are
(a) for integer ALU 1 and integer ALU 2
respectively
(b) for integer preprocessing and integer ALU
respectively
(c) dummy only
(d) none of these
9. The instruction format of UltraSPARC is
(a) non-uniform and composed of 32-bit and
64-bit
(b) uniform and always 32-bit
(c) uniform and always 64-bit
(d) none of these
10. In UltraSPARC instruction format, the annul
bit is provided for
(a) controlling the execution of the instruction
immediately following the conditional branch
instruction to avoid any eventual delay.
(b) distinguishing between oating point and
integer operations
(c) indicating that the remaining bits of imme-
diate data is available in the following
instruction
(d) none of these
1. Who are the designers and manufacturers of
UltraSPARC processors?
2. Prepare a list of differences between SPARC
and UltraSPARC processors.
3. Which oating point instructions of Ultra-
SPARC consumes more time than other oat-
ing point instructions?
4. What is the purpose of Stage 4 of oating point
branch within 9-stage pipeline of UltraSPARC?
5. What is the advantage of write-through logic
used in case of L1 data cache of UltraSPARC?
6. A maximum of how many registers may be
accommodated within any one instruction of
UltraSPARC?
7. How UltraSPARC manages to complete the
complex oating point instructions within the
same time duration required by simple integer
operations?
8. Which operations are conducted during Stage
8 of the pipeline of UltraSPARC?
9. What is the purpose of two most signi cant
bits of any instruction format of UltraSPARC?
10. Considering normal operations, how many
instructions are executed by UltraSPARC in
one cycle?
Spend Some Time Here
1. Prepare a list of similarities and differences
between SPARC-UltraSPARC and Intel
processors.
2. What are the advantages of providing the
L2 cache of UltraSPARC outside the chip
package?
3. Is there any advantage of making lowest eight
registers of UltraSPARC as global registers?
Justify your answer.
4. What purpose does the register window serve
in UltraSPARC?
5. Why separate oating point registers are
offered in UltraSPARC?
6. What is the difference between physical
registers and logical registers of
UltraSPARC?
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462 Computer Architecture and Organization
7. How does instruction grouping logic helps
in speeding up the execution in case of
UltraSPARC?
8. UltraSPARC is a RISC processor and main-
tains an uniform width of instruction format,
which is 32-bit. What are its advantages and
disadvantages?
9. How UltraSPARC manages to load 32-bit
immediate data within its registers using its
32-bit instruction format?
10. How any call-address is generated by
UltraSPARC?
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