472 Computer Architecture and Organization
C.7 DATA TYPES OF POWER PC
The data types, recognized by Power PC, may be broadly classi ed in three types, namely integer type,
oating point type and string type. The integer type data may be of
R 8-bits (byte)
R 16-bits (half-word)
R 32-bits (word) and
R 64-bits (double-word).
The half-words and words may be treated either as signed or unsigned integers. Double words (64-bit
values) are taken as unsigned and used as address for memory pointing. The oating point data may be
either single or double precision type, in accordance with IEEE 754 format.
SUMMARY
Power PC adopts a super-scalar RISC architecture with n -stage pipeline to execute three instructions
per cycle. Earlier versions of Power PC were 32-bit, and later it was changed to 64-bit with backward
compatibility. It was designed in collaboration with Apple, IBM and Motorola, known as AIM and
the design was derived from IBM’s POWER architecture implemented in IBM’s RISC System/6000
workstation.
Internally, Power PC offers separate L1 cache for instruction and data and a uni ed L2 cache. With
two oating point unit and two integer unit along with a branch processing unit it is capable of execut-
ing along three different pipelines. Most of the general purpose registers of Power PC are 64-bit and
there are 32 64-bit registers for integer unit and another 32 64-bit registers for oating point unit. The
condition register within branch processing unit is 32-bit and divided into eight nibbles to accommodate
various set of conditions. The 32-bit register XER of the integer processing unit offers a byte counter for
string load/store operation and three 1-bit ags for indicating carry and over ow conditions.
Like all other true RISC processors, Power PC also offers a compact instruction set with minimum
number of instructions related with external memory communications. Instruction set of Power PC may
be divided into six functional groups, namely Load/Store, Integer arithmetic, Floating point, Logical
and Shift, Branch oriented and Cache Management. Power PC allows three or even four-register opera-
tions through some instructions.
Power PC operates on three independent pipeline for integer, oating point and branch processing
type instructions with a maximum of six stages devoted to oating point pipeline and a minimum of two
stages for branch processing pipeline. Integer operations and load/store type instructions are taken care
of by the same pipeline composing of four and ve stages respectively.
POINTS TO REMEMBER
R Power PC offers multiply and then add type single instruction.
R Current machine status of Power PC is available in MSR register, which helps to respond against
external interrupts.
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