Power PC 473
REVIEW QUESTIONS
Target the Correct Option
1. The acronym Power PC stands for
(a) Processor operated with ef cient registers
and pseudo-computing
(b) Performance oriented whirlpool engine
related processing component
(c) Performance optimization with enhanced
RISC – performance computing
(d) None of these
2. The L1 cache of Power PC is a
(a) uni ed cache (c) either of these
(b) split cache (d) none of these
3. The 64-bit version of Power PC offers
(a) 64-bit registers (c) both of these
(b) 32-bit registers (d) none of these
4. The number of 64-bit general purpose reg-
isters for oating point operation of Power
PC is
(a) 32 (c) 65
(b) 33 (d) none of these
5. Which register of Power PC offers the byte
count facility?
(a) MSR (c) FPSCR
(b) Count (d) None of these
6. What is the specialty of bits 0 to 3 of condi-
tion register of Power PC?
(a) It accommodates all four ags
(b) It accommodates the status of results of
integer operations
(c) It re ects the number of pending iterations
(d) None of these
7. Apart from the Load/Store instruction set,
which other instruction sets contain memory
related instructions?
(a) Floating point instruction set
(b) Cache management instruction set
(c) Both of these
(d) None of these
8. How many registers are involved in the mul-
tiply and add instruction of the oating point
instruction group?
(a) 4 (c) 2
(b) 3 (d) None of these
9. For which pipeline of Power PC decoding is
not executed at stage 2?
(a) Integer pipeline
(b) Floating point pipeline
(c) Branch processing pipeline
(d) None of these
10. How many stages are necessary for oating
point pipeline to execute any instruction?
(a) 6 (c) 2
(b) 4 (d) None of these
Find in Few Seconds
1. Which group did design Power PC?
2. What is the cache memory con guration of
Power PC?
3. Describe the register set available in Power PC.
4. How the XER register of Power PC helps in
programming?
Z03_GHOS1557_01_SE_C18_App_C.indd 473Z03_GHOS1557_01_SE_C18_App_C.indd 473 4/29/11 5:42 PM4/29/11 5:42 PM
474 Computer Architecture and Organization
Spend Some Time Here
5. What is the purpose of condition register?
6. What is the specialty of the shift instruction
of Power PC?
7. What are the differences between integer
multiply and oating point multiply instruc-
tions of Power PC?
8. What are the steps executed during Stage 2 of
branch processing pipeline of Power PC?
9. What is the difference between integer pipe-
line and load/store pipeline?
10. What is the purpose of address generation
stage of load/store pipeline of Power PC?
1. Behind every success there were some failures
and Power PC is no exception. Discuss about
the failures and success of Power PC evolution.
2. Why the size of the L1 instruction cache is
enhanced in later version of Power PC, main-
taining the size of L1 data cache unchanged?
3. What is the purpose of exception register of
Power PC?
4. Which register of Power PC accommodates
the conditional ags and how?
5. What are the differences between branch
processing registers and other registers of
Power PC?
6. What is the difference between summary
overfl ow and overfl ow ags?
7. What are the utilities of the cache manage-
ment instructions of Power PC?
8. How Power PC maintains uniformity with
non-uniform number of stages in its three
pipelines?
9. Compare Power PC pipeline with Ultra-
SPARC pipeline.
10. What would have been the dif culties had
Power PC provided only one pipeline instead
of three?
Z03_GHOS1557_01_SE_C18_App_C.indd 474Z03_GHOS1557_01_SE_C18_App_C.indd 474 4/29/11 5:42 PM4/29/11 5:42 PM
..................Content has been hidden....................
You can't read the all page of ebook, please click here login for view all page.