Intel Core2Duo 479
PROCHOT Indicates that the processor is hot and exceeded the maximum safe operating temperature.
THERMTRIP An indication (output) that the temperature has crossed beyond safe limit for the silicon
wafer and the processor is automatically shutting down itself.
BNR Block next request
DBI0 – DBI3 To be used for data bus inversion. DBI0 controls D0 – D15, DBI1 controls D16 – D31,
DBI2 controls D31 – D47 and DBI3 controls D48 – D63.
DBR Debug request. Necessary at debugging stage.
DEFER This input is to be generated by an external device to indicate the processor that some transac-
tion is yet to be completed.
DSTBP0 – DSTBP3 Data strobe signals.
GTLREF0 – GTLREF1 These two inputs are to determine signal reference levels.
LINT0, LINT1 These are local APIC interrupts. If APIC is disabled, LINT0 becomes INTR (maskable
interrupt) and LINT1 becomes NMI (non maskable interrupt). INTR and NMI are backward compatible
with Pentium processors.
LOCK Indicates to the system that a transaction must occur automatically.
PECI Platform Environment Control Interface (PECI) is a proprietary one-wire bus interface.
PSI This is an output signal for processor power status indicator.
TCK Test clock input for the processor.
TDI Input signal representing Test Data In and necessary for JTAG interface.
TDO Output signal representing Test Data Out and necessary for JTAG interface.
TMS is an input signal for Test Mode Select and is a JTAG speci cation support signal.
TRDY is an input for the processor to indicate that the target is ready to receive a write or implicit write back.
As the reader might have observed, Core2Duo offers quite a few signals for debugging as well as power
management. These power management signals are bene cial when the processor is used for laptops
and when the laptop runs on its battery power supply. We shall now discuss a few details related to this
power management aspect.
D.4 LOW-POWER STATES AND POWER MANAGEMENT
In low-power state diagram of Core2Duo illustrated in Figure D.3 , we observe that the processor offers
a total of eight states. They are:
R Normal state
R Extended HALT or HALT state
R Extended HALT Snoop or HALT Snoop state
R Stop-Grant state
R Extended Stop-Grant or Stop-Grant Snoop state
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480 Computer Architecture and Organization
R Sleep state
R Deep Sleep state, and
R Deeper Sleep state.
Figure D.3 Low power state diagram of Core2Duo (Courtesy: Intel Corporation)
Normal state
(Normal execution)
Extended HALT or HALT state
(BCLK running
Snoops and interrupts allowed)
Extended HALT Snoop or HALT
Snoop state
(BCLK running
Service snoops to caches)
Extended Stop Grant or
Stop Grant Snoop State
(BCLK running
Service snoops to caches)
Deeper Sleep State
BCLK can be stopped
Snoops or interrupts not allowed
PECI not available
Deep Sleep State
BCLK can be stopped
Snoops or interrupts not allowed
PECI not available
Sleep State
BCLK running
Snoops or interrupts not allowed
PECI not available
Stop grant state
(BCLK running
Snoops and interrupts allowed)
From the normal state, the processor enters within the Stop-Grant state if STPCLK is low. The proces-
sor regains its normal state from Stop-Grant state whenever STPCLK is changed to high. At this state if
any snoop event occurs then the processor would enter in the Extended Stop-Grant or Stop-Grant snoop
state and after completion of servicing the snoop event, resume back to Stop-Grant state. From the Stop-
Grant state the processor may enter within the Sleep state when SLP goes low. A high at SLP brings back
the processor from Sleep state to Stop-Grant state. The Sleep state may be converted to Deep Sleep state
and vice versa through the DPSLP signal. Similarly, the Deep Sleep state may be converted to Deeper
Sleep state (Can this be interpreted as the zero-dream state?) and vice versa using the DPRSTP signal.
From the normal state the processor may also switch to Extended HALT or HALT state through
HALT or MWAIT instruction generating HALT bus cycle. To come back to the normal state the proces-
sor would need any one of INIT, INTR, NMI, SMI, RESET or FSB interrupts. Just like the Stop-Grant
state, snoops and interrupts are allowed also during the Extended HALT or HALT state. Any eventual
snoop event would change the Extended HALT or HALT state to Extended HALT Snoop or HALT
Snoop state and after servicing the Snoop event, the old state would be resumed as shown by the arrow.
Figure D.4 Transition steps from Normal to Deeper Sleep state and related signals
Normal
state
Stop grant
state
Sleep
state
Deep sleep
state
Deeper sleep
state
STPCLK
SLP DPSLP
DPRSTP
= 0 = 0
= 0
= 0
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