482 Computer Architecture and Organization
and string variables. Signed and unsigned multiplication and division with integer as well as oating
point variables are also possible through its array of ALUs (FP and integer).
Unlike its previous NetBurst microarchitecture used for Pentium 4 or Pentium-D, Core microarchi-
tecture depends on lower clock speeds and better power management features. Core microarchitecture
depends more on better and more ef cient decoding, divided into predecode and decode modules. It
does not offer hyper-threading technology, available in Pentium 4. Moreover, unlike Pentium 4, it does
not offer any on chip L3 cache.
The Core microarchitecture used by Intel for Core2Duo processor has yielded solo-, dual- and quad-
cored processors so far. This is single instruction and multiple data (SIMD) supporting architecture for
which proper sequencing of instruction stream is essential. This has been made possible by appropriate
memory handling features available in this architecture. The processor uses a 14-stage pipeline for its
general operations. Core2Duo is capable of out-of-order execution and also supports execute disable bit
capability to stop execution when unwanted boundary crossing is detected by the processor. This helps
in keeping away the virus actions without the need of any antivirus software protection. All these are
supported by the rich instruction set of the processor which we are about to discuss.
D.6 INSTRUCTION SET
Core2Duo is a CISC processor with some RISC features. Its CISC features are illustrated by its rich instruc-
tion set which we are about to discuss shortly. Regarding its RISC features, we cannot mention its instruc-
tion format which, because of the backward compatibility restrictions, is complex enough with respect to
any standard RISC instruction format. However, at the micro-coding level, it is equipped with most simpli-
ed instruction format ef cient enough to generate necessary control signals as per the system demands.
Its pipelines architecture along with multiple ALUs is another RISC feature. It offers a larger number of
internal registers as well as internal cache, which are also the basic characteristics of RISC processors.
Therefore, we may say (as indicated in chapter 5 itself) that is offers a RISC-like-CISC architecture, i.e., a
processor with very large instruction set but also offering the bene ts of standard RISC architecture.
Instructions of Core2Duo belong to IA – 64 instruction set architecture of Intel, supporting 64-bit
instruction format. The processor offers an extremely large set of instructions with adequate instructions
for data processing. To present a rough idea to the reader about the comprehensiveness of the instruction
set, only a few selected instruction mnemonics along with their very brief descriptions are presented
below without mentioning any instruction format dealing with variations of addressing modes and oper-
ands. Mnemonics are printed in bold followed by their brief descriptions.
ADC Add with carry
ADD Addition without carry
ADDPD Add packed double precision oating point values
ADDPS Add packed single precision oating point values
ADDSD Add scalar double precision oating point values
ADDSS Add scalar single precision oating point values
ADDSUBPD Add/Subtract packed double precision oating point values
ADDSUBPS Add/Subtract packed single precision oating point values
AND Logical ANDing operation
ANDPD Bit-wise logical AND of packed double precision oating point values
Z04_GHOS1557_01_SE_C19_App_D.indd 482Z04_GHOS1557_01_SE_C19_App_D.indd 482 4/29/11 5:44 PM4/29/11 5:44 PM
Intel Core2Duo 483
ANDPS Bit-wise logical AND of packed single precision oating point values
ANDNPD Bit-wise logical AND NOT of packed double precision oating point values
ANDNPS Bit-wise logical AND NOT of packed single precision oating point values
BLENDPD Blend packed double precision oating point values
BLENDPS Blend packed single precision oating point values
BLENDVPD Variable blend packed double precision oating point values
BLENDVPS Variable blend packed single precision oating point values
BSF Bit scan forward
BSR Bit scan reverse
BSWAP Byte swap
BT Bit test
BTC Bit test and complement
BTR Bit test and reset
BTS Bit test and set
BW/CWDE/CDQE Convert byte to word / Convert word to double word / Convert double word to
quad-word
CALL Call procedure
CLC Clear carry ag
CLD Clear direction ag
CLFLUSH Flush cache line
CLI Clear interrupt ag
CLTS Clear Task-switched ag in CRO
CMC Complement carry ag
CMOVcc Conditional move (cc = condition)
CMP Compare two operands
CMPPD Compare packed double precision oating point values
CMPPS Compare packed single precision
oating point values
CMPS Compare string operands
CMPSD Compare scalar double precision oating point values
CMPSS Compare scalar single precision oating point values
CMPXCHG Compare and exchange
CMPXCHG8B/CMPXCHG16B Compare and exchange bytes/words
COMISD Compare scalar ordered double precision oating point values and set EFLAGS
COMISS Compare scalar ordered single precision oating point values and set EFLAGS
CPUID CPU identi cation
CRC32 Accumulate CRC32 value
CVTDQ2PD Convert packed Dword integers to packed double precision FP values
CVTDQ2PS Convert packed Dword integers to packed single precision FP values
CVTPD2DQ Convert packed Double precision FP values to packed Dword integers
Z04_GHOS1557_01_SE_C19_App_D.indd 483Z04_GHOS1557_01_SE_C19_App_D.indd 483 4/29/11 5:44 PM4/29/11 5:44 PM
484 Computer Architecture and Organization
CVTPD2PI Convert packed Double precision FP values to packed Dword integers
CVTPD2PS Convert packed Double precision FP values to packed single precision FP values
CVTPI2PD Convert packed Dword integers to packed double precision FP values
CVTPI2PS Convert packed Dword integers to packed single precision FP values
CVTPS2DQ Convert packed single precision FP values to packed Dword integers
CVTPS2PD Convert packed single precision FP values to packed double precision FP values
CVTPS2PI Convert packed single precision FP values to packed Dword integers
CVTSD2SI Convert scalar double precision FP values to integer
CVTSD2SS Convert scalar double precision FP value to scalar single precision FP value
CVTSI2SD Convert Dword integer to scalar double precision FP value
CVTSI2SS Convert Dword integer to scalar single precision FP value
CVTSS2SD Convert scalar single precision FP value to scalar double precision FP value
CVTSS2SI Convert scalar single precision FP value to Dword integer
CVTTPD2DQ Convert with truncation packed double precsiion FP values to packed Dword integers
CVTTPD2PI Convert with truncation packed double precision FP values to packed Dword integers
CVTTPS2DQ Convert with truncation packed single precision FP values to packed Dword integers
CVTTPS2PI Convert with truncation packed single precision FP values to packed Dword integers
CVTTSD2SI Convert with truncation scalar double precision FP values to signed integer
CVTTSS2SI Convert with truncation scalar single precision FP values to Dword integer
CWD/CDQ/CQO Convert word to double word / Convert double word to quad word
DEC Decrement by 1
DIV Unsigned divide
DIVPD Divide packed double precision oating point values
DIVPS Divide packed single precision oating point values
DIVSD Divide scalar double precision oating point values
DIVSS Divide scalar single precision oating point values
DPPD Dot product of packed double precision oating point values
DPPS Dot product of packed single precision oating point values
EMMS Empty MMX technology state
ENTER Make stack frame for procedure parameters
EXTRACTPS Extract packed single precision
oating point value
FXRSTOR Restore X87FPU, MMX, XMM and MXCSR state
FXSAVE Save FPU, MMX technology and SSE state
HADDPD Packed double FP horizontal add
HADDPS Packed single FP horizontal add
HLT Halt
HSUBPD Packed double FP horizontal subtract
HSUBPS Packed single FP horizontal subtract
Z04_GHOS1557_01_SE_C19_App_D.indd 484Z04_GHOS1557_01_SE_C19_App_D.indd 484 4/29/11 5:44 PM4/29/11 5:44 PM
Intel Core2Duo 485
IDIV Signed divide
IMUL Signed multiply
IN Input from port
INC Increment by 1
INS/INSB/INSW/INSD Input from port to string
INSERTPS Insert packed single precision oating point value
INT n/INT0/INT 3 Call to interrupt procedure
INVD Invalidate internal caches
INVLPG Invalidate TLB entry
IRET/IRETD Interrupt return
Jcc Junp if condition is met (cc = condition)
JMP Jump (unconditional)
LAR Load access rights byte
LDDQU Load unaligned integer 128 bits
LDMXCSR Load MXCSR register
LDS/LES/LFS/LGS/LSS Load far pointer
LEA Load effective address
LEAVE High level procedure exit
LFENCE Load fence
LGDT/LIDT Load global/interrupt descriptor table register
LLDT Load local descriptor table register
LMSW Load machine status word
LOCK Assert LOCK signal pre x
LODS/LODSB/LODSW/LODSD/LODSQ Load string
LOOP/LOOPcc Loop according to ECX counter (cc = condition)
LSL Load segment limit
LTR Load task register
MASKMOVDQU Store selected bytes of double quad-word
MASKMOVQ Store selected bytes of quad-word
MAXPD Return maximum packed double precision oating point values
MAXPS Return maximum packed single precision oating point values
MAXSD Return maximum scalar double precision oating point value
MAXSS Return maximum scalar single precision
oating point value
MFENCE Memory fence
MINPD Return minimum packed double precision oating point values
MINPS Return minimum packed single precision oating point values
MINSD Return minimum scalar double precision oating point value
MINSS Return minimum scalar single precision oating point value
Z04_GHOS1557_01_SE_C19_App_D.indd 485Z04_GHOS1557_01_SE_C19_App_D.indd 485 4/29/11 5:44 PM4/29/11 5:44 PM
486 Computer Architecture and Organization
MONITOR Set up monitor address
MOV Move (operand)
MOVAPD Move aligned packed double precision oating point values
MOVAPS Move aligned packed single precision oating point values
MOVBE Move data after swapping bytes
MOVD/MOVQ Move double word / Move quad-word
MOVDDUP Move one double FP and duplicate
MOVDQA Move aligned double quad-word
MOVDQU Move unaligned double quad-word
MOVDQ2Q Move quad-word from XMM to MMX technology register
MOVHLPS Move packed single precision oating point values high to low
MOVHPD Move high packed double precision oating point value
MOVHPS Move high packed single precision oating point values
MOVLHPS Move packed single precision oating point values low to high
MOVLPD Move low packed double precision oating point value
MOVLPS Move low packed single precision oating point values
MOVMSKPD Extract packed double precision oating point sign mask
MOVMSKPS Extract packed single precision oating point sign mask
MOVNTDQA Load double quad word non-temporal aligned hint
MOVNTDQ Store double quad-word using non-temporal hint
MOVNTI Store double word using non-temporal hint
MOVNTPD Store packed double precision oating point values using non-temporal hint
MOVNTPS Store packed single precision oating point values using non-temporal hint
MOVNTQ Store quad-word using non-temporal hint
MOVQ Move quad word
MOVQ2DQ Move quad-word from MMX technology to XMM register
MOVS/MOVSB/MOVSW/MOVSD/MOVSQ Move data from string to string
MOVSD Move scalar double precision oating point value
MOVSHDUP Move packed single FP high and duplicate
MOVSLDUP Move packed single FP low and duplicate
MOVSS Move scalar single precision oating point values
MOVSX/MOVSXD Move with sign extension
MOVUPD Move unaligned packed double precision oating point values
MOVUPS Move unaligned packed single precision oating point values
MOVZX Move with zero extend
MPSADBW Compute multiple packed sums of absolute difference
MUL Unsigned multiply
MULPD Multiply packed double precision oating point values
MULPS Multiply packed single precision oating point values
MULSD Multiply scalar double precision oating point values
Z04_GHOS1557_01_SE_C19_App_D.indd 486Z04_GHOS1557_01_SE_C19_App_D.indd 486 4/29/11 5:44 PM4/29/11 5:44 PM
..................Content has been hidden....................
You can't read the all page of ebook, please click here login for view all page.