492 Computer Architecture and Organization
POINTS TO REMEMBER
R Core2Duo uses Core microarchitecture and is totally different from Dual Core processor, which uses
NetBurst microarchitecture.
R It offers 6 MB L2 cache and no on-chip L3 cache.
R Core2Duo is designed around super-scalar architecture for SIMD environment.
REVIEW QUESTIONS
Target the Correct Option
1. Which architecture was used for Intel
Core2Duo?
(a) NetBurst (c) Nehalem
(b) Core (d) None of these
2. The size of L2 cache available in E8000 series
of Core2Duo is
(a) 2 MB (c) 6 MB
(b) 3 MB (d) none of these
3. Core2Duo is a
(a) CISC processor
(b) RISC processor
(c) RISC type CISC processor
(d) none of these
4. Core2Duo L2 cache is
(a) direct mapped
(b) 8-way set associative
(c) 2-way set associative
(d) none of these
5. The number of pins in the Land Grid Array
package of Core2Duo is
(a) 775 (c) 64
(b) 256 (d) none of these
6. The INIT signal of Core2Duo
(a) initializes the processor
(b) resets the oating point registers
(c) clears L1 and L2 caches
(d) none of these
7. For Core2Duo, INTR and NMI interrupt sig-
nals are generated by external hardware signals
designated as
(a) LINT0 and LINT1
(b) REQ0 and REQ1
(c) BCLK0 and BCLK1
(d) None of these
8. To enter into the Sleep state from its normal
state, Core2Duo must pass through
(a) Extended Halt or Halt state
(b) Extended Stop-Grant or Stop Grant Snoop
state
(c) Stop-Grant state
(d) none of these
9. If STPCLK is asserted low, then Core2Duo
changes its state from
(a) Normal state to Stop Grant state
(b) Deep sleep state to Deeper sleep state
(c) Extended Halt state to Stop Grant state
(d) none of these
10. The instruction set of Core2Duo belongs to
(a) X-86 instruction set of Intel
(b) IA-32 instruction set architecture of Intel
(c) IA-64 instruction set architecture of Intel
(d) none of these
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Intel Core2Duo 493
Find in Few Seconds
1. What are the differences between Intel
Core2Duo and Intel Dual Core processors?
2. What are the application areas of Core2Duo?
3. Out of series E7000 and E8000 of Core2Duo,
which one offers higher clock speed?
4. Is Core2Duo backward compatible with
Intel8086 processor?
5. What is the frequency of FSB of Core2Duo?
6. How pins are designated in 775-pin land
package of Core2Duo?
7. What is the maximum size of physical mem-
ory directly addressable by Core2Duo?
8. What is the purpose of A20M signal of
Core2Duo?
9. What are the differences between three sleep
modes of Core2Duo?
10. Is it possible for Core2Duo to handle all types
of variables like byte, word, double words
and quad-words?
Spend Some Time Here
1. What is the difference between processor and
processor-core ?
2. What are major differences between NetBurst
and Core microarchitecture?
3. Core microarchitecture of Intel is the succes-
sor of NetBurst microarchitecture of Intel.
Which Intel microarchitecture’s successor is
NetBurst microarchitecture?
4. Why L3 cache was not provided within
Core2Duo?
5. What is meant by out-of-order execution?
6. Is there any difference between NMI and
INTR of Core2Duo and 8086?
7. Does the processor Core2Duo save any power
when it is in its Stop Grant state? Justify your
answer.
8. Core2Duo has a common L2 cache for both
cores? Why is it not having a common micro-
code ROM for both of its cores?
9. What is the advantage of predecoding in
Core2Duo?
10. Does Core2Duo offer multiply and then add
type instruction?
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