MIPS R4000 495
permutations and combinations, the new school of thought, branding them as RISC people , concluded
that an ideal faster processor should have
R Simple and minimum number of instructions for uniform instruction-set format resulting in
quicker and ef cient instruction decoding,
R Larger number of CPU registers to minimize time-consuming memory transactions,
R Hardware rather than software method of instruction decoding
R Only simpler load and store instructions to interact with external memory, avoiding complex
addressing modes,
R Larger on-chip cache memory to store instructions and data, and
R Pipelined architecture for multistage processing.
To prove the point, certain designs were physically implemented to demonstrate the ef ciency of
this RISC approach. In early 80s, at Berkeley, David Patterson and Carlo Sequin developed a VLSI
chip to call it RISC-I. Almost at the same time, around 1981 at Stanford University, John Hennessy
developed another silicon wafer on the same line of architecture, designating it as MIPS. Both of these
RISC processors were highly appreciated and became commercial success and today they are known as
UltraSPARC and MIPS Rx000 , respectively.
E.2 GENERAL ARCHITECTURE
MIPS processor, just like Intel processors, has several versions during its evolution from early to later
stages. Earlier models of MIPS R-series processors were 32-bit, like MIPS R2000 and MIPS R3000.
MIPS R4000 is a 64-bit RISC processor. At later dates we nd other models like MIPS R4400 or MIPS
R10000 and so on. Apart from its transition from 32-bit to 64-bit, there is not much of a difference in the
internal architecture of MIPS processors, which, right from its inception, was a clean RISC processor.
External memor
y
and I/O
interfacing
ALU and other
processing
modules
General purpose
register array
Local control
module
System bus
MMU and
system control
coprocessor
Figure E.1 General architecture of MIPS processors
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