496 Computer Architecture and Organization
Figure E.1 presents an over-simpli ed general architecture of MIPS R4000 processor. Note that the
processor is divided into two basic modules, the CPU and its register set along with the local control
module as one part and Memory Management Unit (MMU) with system control co-processor being
the other part (shaded area in Figure E.1 ). The structure of the CPU is left as simple as possible so that
adequate logic circuits might be accommodated within the other module of co-processor and MMU.
This system control co-processor is the unique feature of MIPS R×000 processors.
E.3 EXTERNAL SIGNALS
Schematically external signals of MIPS R4000 are shown in Figure E.2 . As we can observe, signals are
grouped as per their functional similarities, like
R Clock/Control interface
R Initialization interface
R System interface
R Secondary cache interface
R Interrupt interface
R JTAG (Joint Test Action Group) interface.
MIPS R4000
Clock/Control interface
System interface
Secondary cache interface
Initialization
interface
Interrupt
interface
JTAG
interface
SCData(0-127)
SCDChk(0-15)
SCTag(0-24)
SCTChk(0-6)
SCAddr(1-17)
SCAPar(0-2)
SCOE
SCWr(w,x,y,z)
SCDCS
SCTCS
SCAddr0
(w,x,y,z)
SysAD(0-63)
SysADC(0-7)
SysCMD(0-8)
SysCmdP
Validln
ValidOut
ExtRqst
Release
RdRDY
WrRdy
IvdAck
IvdErr
VccP
VccSense
VssSense
TClock(0-1)
RClock(0-1)
MasterClock
MasterOut
SyncOut
Syncln
lOOut
lOln
Fault
Status0-7
[for R4400 only]
VssP
JTDl
JTDO
JTCK
JTMS
Int0
NMI
ModeClock
Reset
ColdReset
ModeIN
VCCOk
Int1 - Int5
Figure E.2 External signals of MIPS processors (Courtesy: MIPS Technologies, Inc.)
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