MIPS R4000 497
For example, the power input, clock input and some essential processor controlling signals are pre-
sented under the Clock/Control interface. Note that eight status signals are available only in R4400
model of the processor.
The reader’s attention may be drawn to a few signals of R4000, for example, two system-reset sig-
nals Reset and ColdReset. In general, we are accustomed with only one reset input signal. However,
MIPS R4000 allows three different types of reset, namely:
R Power-on reset
R Cold reset
R Warm reset.
Power-on reset is executed when the processor is activated by turning on its power supply. All inter-
nal modules of the processor are initialized in this case. If the ColdReset signal is asserted (goes low),
then also the complete processor is initialized or the effect is identical with power-on reset. If Reset is
activated by making this input low, it simply restarts the processor preserving the processor’s internal
state . In general, for other processors, a power-on reset (by turning the processor’s power supply off
and then on) reinitializes the processor completely. In case of R4000, the same effect may be achieved
without switching the power off and then on, by activating the ColdReset signal. The function of Reset
of R4000 is identical with that of other processors.
The system interface signals are provided for external device interfacing with R4000. Through
SysAD(0-63), it offers 64-bit address signals and 64-bit data signals in multiplexed form. The second-
ary cache interface signals offer necessary communication interface between R4000 and the external
secondary cache. This interface consists of 128 data lines through SCData(0-127) and 18-bit address
line through SCAddr(1-17) along with SCAddr0(w,x,y,z). As a matter of fact, SCAddr0(w,x,y,z) repre-
sents four outputs of the same signal, i.e., least signi cant bit of the address bus for secondary cache. All
these four outputs carry identical signals and provided for enhanced current requirements. One interest-
ing feature of MIPS R4000 processor is that its secondary cache may be either a uni ed cache or a split
cache, which is software programmable through boot-mode settings at the time of booting.
MIPS R4000 offers seven external interrupt inputs through its interrupt interface signals. One of these
signals NMI is meant for non-maskable interrupt input and logically ORed with bit 6 of the interrupt register
of the processor. Other interrupt signals (Int0 and Int1-Int5) are maskable and logically ORed, accordingly
with the interrupt register. JTAG interface signals help in offering the JTAG boundary scan mechanism.
E.4 INTERNAL ARCHITECTURE
A detailed internal architectural diagram of MIPS R4000 is shown in Figure E.3 . Note that the processor
contains separate integer and oating point units with dedicated register sets for each unit. The oating
point ALU can perform addition, multiplication and division operations with oating point numbers
apart from calculating the square root of any oating point number. The unit also has a pipeline bypass
module, whose functions we shall discuss later in this appendix.
As shown in Figure E.3 , MIPS R4000 offers two types of cache memories, designated as Primary
cache (P-Cache), and Secondary cache (S-Cache). The primary cache is an on-chip split-cache divided
into instruction cache and data cache. The secondary cache is expected to be externally interfaced with
the processor through the secondary cache interface signals illustrated at the left side of Figure E.2 .
The remaining portion of the processor accommodates the memory management unit with its dedicated
register set, Translation Look-aside Buffers (TLB) and other control registers and control units, shown
within the CPO module.
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498 Computer Architecture and Organization
MIPS R4000 offers an 8-stage pipeline for its instruction execution. This pipeline control module
takes care of memory management unit along with oating point as well as integer unit, depicted at the
bottom of Figure E.3 . In Section E.8, we shall have detailed discussions on MIPS pipeline issues.
System control Data cacheS-cache control P-cache control Instruction cache
64-bit system bus
CPU registers
ALU
Load aligner/
store driver
Integer multiplier/
divider
Address unit
PC incrementer
Central processing unit
FPU registers
Pipeline bypass
FP multiplier
FP divider
FP Add, convert
and
Square root
Floating point unit
Pipeline control
CPO
Exception/
control
registers
Memory
management
registers
Translation
Look-aside
Buffer
(TLB)
Figure E.3 Detailed internal architecture of MIPS R4000 (Courtesy: MIPS
Technologies, Inc.)
Figure E.4 Functional block diagram of floating point unit (Courtesy: MIPS
Technologies, Inc.)
Data cache
Floating point register file
Floating point
Bypass
Pipeline
Chain
FP
addition
+
Squareroot
unit
FCU
Control
FP
multiplication
unit
FP
division
unit
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