MIPS R4000 507
SUMMARY
MIPS processors were originated at Stanford University by John Hennessey during 1981, as a result of a
new approach of processor architectural design, branded as RISC or Reduced Instruction Set Computer.
MIPS R4000 is a 64-bit RISC processor with super-scalar architecture having on-chip L1 split-cache
and provision for off-chip L2 cache to be externally interfaced.
For external interfacing, the processor offers 64 address and 64 data signals in multiplexed form. For an
external secondary cache interfacing it provides another 128 data lines with separate 18-bit address lines.
There are seven external hardware interrupt inputs including one non-maskable interrupt or NMI. It pro-
vides two separate system reset signals and a JTAG interface along with necessary power and clock inputs.
MIPS offers 32 general purpose registers apart from a program counter and a pair of registers exclu-
sively for multiplication and division operations, designated as HI and LO. All registers of MIPS are
64-bit and in 32-bit mode only their lower 32 bits are utilized.
Like all other RISC processors, the number of instructions for MIPS is also maintained as minimum
and optimum. In total there are 67 mnemonics divided into eight functional groups. Instructions are
available for both signed as well as unsigned operations involving numbers. Condition ags are not
available in MIPS and the re ection of result of any arithmetic or logical operation is stored in a register
for any eventual conditional branching.
MIPS offers an uniform 32-bit instruction format with only three types, namely: I-type, J-type and
R-type. It accommodates 3-register addressing mode and most signi cant six bits of the instruction contains
the opcode. Its pipeline architecture offers eight-stage pipeline, which is uniform for all type of instructions.
Using the TLB located within its MMU having fully set associative memory for 48 page-pairs’
details, the processor converts virtual address to physical address. Exception processing is carried out
for TLB misses, arithmetic over ows, I/O interrupts and system calls.
POINTS TO REMEMBER
R MIPS R4000 processor is designed around RISC architecture with 64 address and 64 data lines and
eight-stage pipeline.
R It allows an external secondary cache programmable as uni ed or split during its booting.
R MIPS does not offer any condition ag and the refection of any arithmetic operation is stored within
a register for eventual conditional branching operation.
REVIEW QUESTIONS
Target the Correct Option
1. The L1 cache of MIPS R4000 processor
is
(a) split-cache (c) both of these
(b) uni ed cache (d) none of these
2. The reset signal of MIPS processors are des-
ignated as
(a) Reset (c) both of these
(b) ColdReset (d) none of these
3. The maximum size of external main memory
addressable by MIPS R4000 would be
(a) 2
32
bytes (c) 2
128
bytes
(b) 2 64 bytes (d) none of these
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508 Computer Architecture and Organization
Find in Few Seconds
4. The external hardware interrupt signals
offered by MIPS R4000 processor would be
(a) NMI only (c) NMI and INT0-INT5
(b) NMI and INT0 (d) none of these
5. The number of address lines (SCAddr)
offered by MIPS R4000 processor to interface
its external secondary cache would be
(a) 17 (c) 22
(b) 18 (d) none of these
6. The number of general purpose registers of
MIPS would be
(a) 8 (c) 64
(b) 16 (d) none of these
7. How many conditional ags are available in
MIPS?
(a) 5 (c) 27
(b) 12 (d) None of these
8. All instructions of MIPS are ____ - bit
wide and its most signi cant _____ bits are
reserved for opcode.
(a) 32, six (c) 128, ten
(b) 64, eight (d) none of these
9. What is the maximum number of registers that
may be accommodated within one instruction
of MIPS?
(a) 2 (c) 4
(b) 3 (d) none of these
10. Which operation is performed by the branch-
type instructions of MIPS at the WB (write
back) stage of the pipeline?
(a) TLB updating
(b) Jump address calculation
(c) No operation
(d) None of these
1. What was the origin of MIPS processors?
2. How many types of reset options are provided in
MIPS R4000 processor? Brie y describe those.
3. Apart from CPU and its registers, what is
the other important module available within
MIPS R4000 processor?
4. What is the specialty of the general purpose
register r0 of MIPS?
5. How MIPS implements conditional branch-
ing instructions?
6. Through which type instructions MIPS com-
municate with external main memory?
7. What is the purpose of I-type instruction for-
mat of MIPS?
8. How the branch address is calculated by
MIPS?
9. What are the different stages of MIPS pipeline?
10. For register to register operation type instruc-
tions, draw the relevant pipeline stages of
MIPS processor.
Spend Some Time Here
1. In general only one reset input is provided by
any processor. What is the necessity of the
second reset input in MIPS processors?
2. If the external main memory of MIPS R-series
processors has 64 data lines, why its external
secondary cache has 128 data lines?
3. What would be the maximum size of secondary
cache for MIPS R4000 processor, assuming it
to be a uni ed cache?
4. What is the utility of offering a string of zeros
(null) through the general purpose register r0
of MIPS?
5. What advantage was gained by MIPS by not
offering any condition ags?
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MIPS R4000 509
6. MIPS reserves its most signi cant six bits of
any instruction for the opcode. In that case
how it can offer 67 mnemonics as 2
6
= 64
only?
7. How uniform is the instruction format of
MIPS? Justify your answer.
8. Does the branch address of MIPS is depen-
dent upon its present value of the program
counter? If yes, then which type of jump it
might be designated as?
9. Why instruction or data is fetched in two parts
by the pipeline of MIPS?
10. What is the uniqueness of MIPS R4000 pro-
cessor with respect to other similar RISC
processors?
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