ACK signal, 248
Address signal, 19
ADSTB signal, 222
ALU design, 10
ALU output, 271
ALU registers
Analog to digital converter (ADC), 15
AND gate, truth table for, 18
AND operator, 30
Apple Mac. Server, 9
Arbitration bus, 261
Arithmetic circuits, 38
half-adder, 38
truth table, 38
Arithmetic-logic unit (ALU), 3, 95
ARM microcontroller, 449
Array processor, 404-405
schematic of, 405
Associative cache, 214
Asynchronous ripple counter, 46
timing diagram of, 47
ATmega8 microcontroller, 416, 418
architecture of, 418
ag-bit allotment, 420
program memory, 419
ATMEL AVR
architecture of, 416
pins and signals, 416
AVR core, 417
Babbage, Charles, 4
Bandwidth, 238
BBC MICRO, 7
Binary numbers, 443
Binary point, 80–81
3-bit biased two’s complement, 79
4-bit ALU, 54
Boolean algebra
circuit design, 35
fundamental identities of, 32
Bus arbitration, 261–262
Bus interface unit (BIU), 113
Cache directory, 210
Central processing unit (CPU), 16
CISC processor, 482
Colour printing, 437
Complex instruction set computing (CISC), 2, 10
Computer, 2
architectural features of, 3
asynchronous data communication, 240–241
classi cation, 8–11, 240
device drivers, 253–254
DMA, 251–253
historical background, 4–8
IAS, 5
input/output structure of, 238–239
instruction decode, 19
instruction execute, 20
instruction fetch, 19
internal features of, 16
interrupt controller (8259), 249–251
interrupt driven I/O, 246–249
mechanical, 3
memory, 3, 19
micro-architecture, 23–24
motherboard, 15
operating system, 9
operational concepts, 18
OS, 346–347
processor clock, 18
processors, 3
program ow control, 21
programmed I/O (polling), 244–246
schematic representation of, 3, 254
serial and parallel communications, 241–244
spectrum, 8
standard I/O interfaces (BUSES), 254–261
time-line of improvements, 4
Computer architecture, 2
Computer arithmetic
addition and subtraction, 59–63
Booth’s algorithm, 64–72
division algorithms, 72–73
division of signed integers, 73–77
oating-point arithmetic and unit operations, 85–90
oating-point number representation, 77–85
introduction, 58
multiplication algorithms, 63–64
pipelined ALU, 90–91
Computer generated feedback (CGF), 237
Computer-generated results (CGR), 237
Index
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538 Index
Computer organization, 2
Computer peripherals
display, 437–438
keyboard, 430–432
mouse, 433–434
printers, 434–437
touch pads, 438
Computer system bus structure
external, 21
internal, 21–22
Communication techniques
asynchronous data, 240
classi cation of, 240
timing diagram for asynchronous
communication, 240
Conducted tour, 15
Control data Corporation (CDC), 6
Control unit (CU), 302–303
2-bus system, 335
control signal requirements, 313
control signals, 317, 323
controlling system, 310–311
data alte rnatives of,
data ow and timing diagram, 336–341
data path design, 312
execute cycle, 308
fetch Cycle, 303–306
owchart, 309
hardware implementation, 315–316
inputs and outputs, 311
instruction cycle, 309–310
internal data paths, 311–312
interrupt cycle, 308–309
interrupt handling by two-bus system, 333–334
latching mechanism of registers, 314
latching signals, 314–315
micro-operations, 303
one-bus system, 332
operand Fetch, 307
processor control, 310
signal requirements, 313–314
signals for micro-operation, 322, 330
study of control signal requirements, 313
three bus system, 331
timing diagram for by one through ALU, 320
timing diagram for MAR and MBR, 319
timing diagram for MBR into IR, 319
timing diagram for using B-Bus, 322
timing diagram for using C-Bus, 321
timing diagram for Z to PC, 320
timing diagram PC to MAR, 318
Control signals, 271
Control unit (CU), 3
Conversion techniques, 444–446
binary to decimal, 446
binary to hexadecimal, 446
decimal to binary, 445–446
CPU-bound processes, 350
Crossbar networks, 395
CRT display, 437–438
Current window pointer (CWP), 452
Daisy chaining, 262
Data
bit-wise designation of, 153
Data path design, 269–270
register organization, 270
DC characteristics, 94
Decimal numbers systems, 442–443
Decoder, 35–36
2-to-4 decoder, 36
Designer’s model, 108
Desktops, 9
D ip- ops, 267
Device drivers, 253–254
Digital equipment corporation (DEC), 6
Digital to analog converter (DAC), 15
Digital logic circuits
a rithmetic circuits, 38
background, 29
basic latch, 41
Boolean algebra, 29
Boolean identities, 19
Boolean operators, 30
clock signal, 40
clocked S-R ip- op, 43–44
combinational circuits, 36
counters, 46
D ip- op, 44
decoder, 36
f ull-adder, 39
J-K ip- op, 44–45
logic gates, 32–35
m ultiplexer, 37
n-Bit Adder, 39
registers, 45
scope, 29
sequential circuits, 40
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Index 539
S-R latch, 42–43
switch analogy, 28
T ip- op, 45
TTL logic levels, 28
Digitizer, 15
Direct addressing mode, 157–158
Direct mapped cache, 209
Division algorithm
illustration of, 74–77
locations involved, 73–74
one-bit left-shift operation for, 74
DMA controller, 239
schematic of hardware for, 222–223
schematic of signals of, 252
DMA technique, 10
Dot-matrix printer, 435–437
DPSLP signal, 481
DRAM bit, 216
DRAM refreshing, 216s
Dual in-line package (DIP), 16, 416
Dynamic RAM (DRAM), 215
Electronic numerical integrator and computer (ENIAC), 4
Embedded controllers, 411
general architecture of, 415
Embedded systems, 411
classi cation of embedded, 413
example of, 426
instrumentation, 413
keyboard, 432
mouse, 434
power supply, 412
processing power, 412
system speci cations, 426–427
types and classi cations, 412
wireless, 413
Execution unit (EU), 113
Fault tolerant computing, 406–407
Fault tolerant system, 408
Fetch cycle
registers arrangements, 304
sequence of, 306
First-come- rst-served (FCFS), 354
Five 1-bit ags, 109
Flat panel display, 438
Floating-point addition/subtraction, owchart for, 87
Floating-point ALU, 90
Floating-point division, owchart for, 89
Floating-point multiplication, owchart for, 88–89
Flynn’s classi cation, 392–393
Four processes, salient characteristics of, 352
Front Side Bus (FSB) frequency, 477
Full-Adder, schematic for full-adder, 39
GPIB/HPIB/IEEE488
schematic representation of, 260
HALT snoop state, 480
Hard disc drive (HDD), 16
Hard disc, 216
Hexadecimal numbers, 443–444
Hypercube networks, 396
Hypercube, 395
Immediate addressing mode, 156
I/O devices, 238
I/O processor, 262–263
Implicit addressing mode, 160
Indexed addressing mode, 160
Indirect addressing mode, 158
Inkjet printer, 436
Input–output module, 3
Instruction cycle, owchart for, 99, 103, 309
Instruction fetch
address decoding, 191
chip select input, 100
control signals, 317
device selection, 101
memory decoder, 101
timing diagram for, 100
8051 instruction set, 172
rst-byte format of, 173
format of, 173
8085 instruction set, 163–164
format and elds of, 165–166
8086 instruction set, 168–169
format of, 170
variations of rst-byte format of, 171
variations of second byte format of, 171
Instruction set design, 184–194
Integer ALU, 90
Integrated circuits, 6–7
Intel Corporation, 6
Intel Core2Duo processor, 475
difference between dual core, 475–476
footprint of, 476
front side bus (FSB) frequency, 471
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540 Index
Intel Core2Duo processor (Cont.)
functional grouping of, 477
IA – 64 instruction set architecture of Intel, 482
important signals, 477–479
instruction set, 482–491
internal architecture, 481–482
low power state diagram of, 480
low-power states and power management, 479–481
MWAIT instruction, 480
pipeline characteristics of, 383
RISC-like-CISC architecture, 383
salient features of, 476–477
schematic functional grouping of, 477
transition steps from, 480
Intel’s core microarchitecture, 475
Intel dual core processor, 475
Intel’s NetBurst microarchitecture, 475
Intel 8051 microcontroller
designer’s model, 125
pin assignments, 125
pins and external signals, 125
Intel 8085 microprocessor, 109
Intel 8086 microprocessor
20-bit address, 116
arithmetic, 121
control transfer, 122
data transfer, 121
designer’s model, 114
internal architecture, 115–116
logical, 122
memory space of, 118
pin assignments, 113–114
processor control, 122
signal sequence, 119
simpli ed timing diagram of, 124
string manipulation, 122
vector details, 123
Intel 80386 processor
allowable segments of, 137
data assessment, 226
external signals, 132
ags, 136
input/output signals, 133–134
internal architecture and registers, 134
memory banks of, 138
memory handling, 136
MMU of, 225
timing diagram for, 138
two-stage paging scheme of, 386
Intel 8237 DMA controller, 251–253
Intel pentium 4 processor, 138–139
internal architecture of, 141
multiple ALU of, 142
pentium 4 integer register set, 144
register array of, 142
scheduler and branch table buffer, 143
Interrupt controller (8259)
8259 with cascading, 250–251
cascade con guration
schematic diagram, 249
without cascading, 250
Interrupt service routine (ISR), 106
Interrupt, 102
ISR, See Interrupt service routine
Jet-type printer, 436
Jumper cables, 4
Jumper connections, 233
Keyboard, 2-D layout of, 432
Language
8085 instruction set, 168–174
addressing modes, 155–156
assembler, 179–181
assembly language programming, 174–179
compiler, 151
example, 194
FORTRAN program, 150
functions and characteristics of instructions,
152–155
high level, 150–151
instruction formats and elds, 161–163
intel 80386 processor, 182–183
intel pentium 4 processor, 184
machine, 151
Laptops, 9
Large scale integration (LSI), 6
Laser printer, 437
LCD screen, 237
Leibniz, 4
Logic gates
NOT, 49
NOR, 35, 42
XOR, 27, 54
NAND, 33–34
XNOR, 34, 54, 55, 286
OR, 33
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Index 541
Machine cycle and T-states, 101–102
interrupt, 102
schematic diagram, 102
Magnetic tape drives, 15
Memory circuits, 47–51
Memory decoding, 229
individual segments, 232
issues of, 231–232
principle of, 230–231
segments, 232
types of, 231
Memory devices, 96
Memory reading, 19
Memory system
cache memory, 204–214
classi cation, 198
computer memory tree, 199
intel 80386 memory organization, 224–228
main memory, 214–
memory characteristics, 201–202
memory hierarchy, 203
memory management, 221–224
pentium 4 data types, 229
pentium 4 memory organization, 228–229
read/write memory (RAM), 200
read-only memory (ROM), 200–201
secondary memory, 216–218
virtual memory, 218–224
Microcontrollers
architecture of, 414
rotation sensing, 433
speed sensing, 433
8085 microprocessor, 110
16-bit program counter of, 118
memory allotment, 111
OUT port instruction, 112
Microprocessors or processors, 10
transistors/IC and timeline of, 7
Motherboard, diagram, 17
Multibus, 261
Multiplexer, 35, 37
schematic, 37
truth table, 37
Multiprocessors
I/O modules, 394
structure of, 393–394
Network topologies, 394–395
mesh, 396
multi-stage, 397–398
ring, 398–399
tree, 397
Neumann architecture, 108
Non-maskable interrupt (NMI), 107
Number systems
Octal numbers, 444
ODD, See Optical disc drive
Operating system
contiguous memory, 362–363
evolution of, 347
life-cycle of a process, 348–349
LINUX, 9
memory management issues, 362
multi-tasking environment, 348
paging, 363
process and its control, 347
purpose of, 347
swapping, 362
thread, 359
Window, 9
Optical disc drive (ODD), 16
Optical mouse, 433–434
Opto-mechanical Mouse, 433–434
OR operator, representation of, 31
Oscillator and Watchdog Timer, 417–418
Palmtops, 9
Paper and Pencil Method, 72–73
Parallel Processing, 392
Pascal, 3
Pen drives, 1
Pentium 4
integer register set, 144
multiple ALU of, 142
register array of, 142
scheduler and branch table buffer in, 143
Pentium 4 pipeline, 383
schematic of, 386
stages of, 386
Piezoelectric method, 436
Pin assignments, 108
Pipelined ALU, 90
Pipeline, multiple instruction, multiple data stream
(MIMD), 2
Pipelining
automobile factory, 368–369
concepts, 368
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