542 Index
Pipelining (Cont.)
controls and data paths, 381–382
out-of order execution, 384–385
register renaming, 385
speculative execution, 385–386
strategy, 369
structural hazards, 279–381
Port pins
DC characteristics of, 422
Power PC
background, 463–464
branch oriented instructions, 469
branch processing, 471–472
cache management instructions, 469
cache memory for, 465
data types of, 472
xed point, 467
instruction set, 467–469
internal architecture, 464–465
introduction, 463
pipeline stages for, 470–471
register set of, 465–467
schematic diagram, 464
schematic representation of, 471
Pre-processing table, 51–52
Process control block (PCB), 349–350
CPU-bound and I/O-bound processes, 350–351
ef ciency of, 351
movements of, 350
scheduling issues, 350
types of scheduling, 351
Processors
20-bit address in 8086, 116
5-stage pipeline operation, 371
8-bit processor, 151
address bus, 96
architecture and organization, 94–98
architecture, 374
arithmetic type instructions, 154–155
carry and zero, 154
control bus, 96
data bus, 96
data dependency, 375
data ow mechanism, 98
data type transfer instructions, 154
decimal adjust, 153
ef ciency of, 370–371
external signals of, 96
fetch-cycle, sequence of, 306–307
ag register of 8086, 117
function of, 95–96
hazards, types of, 374
I/O wait, 377
I-64 micro-architecture, 140
imachine cycle, 102
instruction cycle, 99, 102
instruction hazards, 377
INTEL 80386 processor, 132–144
INTEL 8051 microcontroller, 124–129
INTEL 8085 microprocessor, 107–113
INTEL 8086 microprocessor, 113–124
interrupts, 106–107
logical type instructions, 155
memory bank addressing, 119–120
memory location, 97
multi-stage, 370
NetBurst, 140
operation, 99–102
performance, 372
pipelined operation of, 370
processor stalls, 373
RAM allocation details, 126
register eld variation for, 162
register set, 102–106
register-to-register architecture, 104
risc and cisc processors, 129–132
role of, 162
solution by, 376–377
stack organization, 104
stalling, 372–373
timing diagrams, 112, 123–124
T-state correlation, 102
Program counter, 18–19
Program memory and stack area, 111
Programmed data processor-1 (PDP-1), 6
Program parallelism
cache coherence, 402
load calculation of, 401
multiple execution units, 404
subprograms division, 400
super-scalar architecture, 403
super-scalar operation, 402
two execution modules, 403
Process switching, 357–358
Programmable peripheral interface (PPI), 17
Punched cards, 3
QWERT keyboard, 2
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Index 543
RAM and ROM
RD signal, 247
Real-time systems, 414
analog processing, 414
networking, 414
Reduced instruction set computing (RISC), 2, 10
Relative addressing mode, 159
Ring networks
mixed topology, 400
single bus, 399–400
RISC processors, 129, 163
Round Robin algorithm, 354–355
SC processors, 316
Scanner, 15
Selector-descriptor tables, 225–226
Semaphores, 359–
critical section, 360–361
owchart for two processes, 361–362
need of, 359
program segment of, 360
Scheduling
rst come rst served (FCFS), 354–355
non–pre-emptive priority, 355–356
pre-emptive priority, 356–357
priority-based scheduling, 351, 356
round robin scheduling (RR), 351, 358
shortest job rst (SJF), 351, 354
Scienti c notation scheme, 79
binary number, 82
number density, 84
way of expression, 80
SCSI bus, 259
Shortest job rst (SJF)
non–pre-emptive, 352–353
pre-emptive, 353–354
Small computer system interface (SCSI), 259
Small scale integration (SSI), 6
SPARC and UltraSPARC processors
design history, 450
functional diagram of, 451
functional overview, 450–451
RISC characteristics, 450
SPARC and UltraSPARC register set
arithmetic instructions, 457
Boolean instructions, 458
instruction format, 455–456
instruction set, 456–457
internal architecture, 453–454
load and store instructions, 457
miscellaneous instructions, 459
nine-stage pipeline of, 454–455
program branching instructions, 459
shift and rotate instructions, 458
special features, 452–453
window example of, 452
Stack Pointer, 104
4-state branch prediction algorithm, 379
CI2-state algorithm, state-diagram for, 378–379
Status register (SREG)
communication, 424–425
cost-effectiveness, 425
design issues, 423
device selection, 423–424
organizational issues, 422
power saving features, 421
stack pointer and system stack, 420–421
system reset, 421–422
STB signal, 257
Switching mode power supply (SMPS), 16
System programming, 151
Threads, 358–359
Touch pads, 1
Transistors, 6
Tree networks
fat tree, 397
three-way tree, 397
TRS-radio shack, 7
Turing, Alan, 5
Thermal method, 436
Touch pads, 438
Trace Cache Fetch, 387
Universal serial bus (USB), 256–259
classi cation and types of, 258
communication, 258
data packets, 258
handshake packet, 258
logo and structure of, 257
root-hub, 257
special packets, 258
token packets, 258
Universal synchronous asynchronous receiver
transmitter (USART), 17
Urgent signal, 308
Vacuum tubes, 4
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544 Index
Vector processor, 405–406
Vectored and Non-Vectored Interrupts, 106
Very large scale integration (VLSI), 6
chip, 7
TRS-radio shack, 7
Virtual memory, 218
VME Bus, 261
Watch dog timer (WDT), 416
WR signal, 247
XY-plotter, 15
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