Fundamentals of Digital Logic Circuits 47
Table 3.6, we nd that this condition would invert the previous output with each falling edge of the
clock pulse.
The left-most ip- op represents least signi cant digit counter through its output Q
0
obtained from Q.
Note that this Q output is also connected with the clock input of the next J-K ip- op, in cascade. There-
fore, every falling edge, generated from Q
0
activates the next ip- op and so on. This mechanism, i.e.,
the over ow (ripple) from one bit changes the next bit, generated the name ‘ripple counter’. Figure 3.24
shows the timing diagram for such a ripple counter, with clock signal at top and other four counter output
signals (Q
0
– Q
3
) below it.
This type of counter is designated as asynchronous counters as there exists some propagation
delay in clock inputs of one ip- op to another. This delay is cumulative and is maximum at the last
ip- op. To eliminate this problem in case of synchronous counters, extra circuits are incorporated
with this.
The counter shown in Figure 3.23 is designed to count up (increment its content at each clock pulse).
To convert it to a down counter, the clock inputs of J-K ip- ops to be derived from Q¯ instead of Q
output of the previous ip- ops.
3.8 MEMORY CIRCUITS
It is already pointed out that a ip- op can act as a basic storage unit for digital logic information.
Memories or read-write memories (RAM) are a combination of these storage cells arranged according
to the requirements. However, a RAM chip does not contain only ip- ops but some other circuits also
for data propagation and address decoding.
Flip- ops are not necessary to construct any read-only memory (ROM) as the data is stored
permanently in such a case. Here, instead of ip- ops, diode-fuses are used to store information of
each bit.
Figure 3.24 Timing diagram of asynchronous ripple counter
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