Computer Arithmetic 77
To start the rst cycle, a left-shift of 1-bit is performed with RQ locations jointly. This produces 1111
in R and 0110 in Q as a 0 is inserted at the LS bit of Q. At this stage, the sign of location V and sign of
location R are same, R is replaced by R − V, i.e., 0001. As the old sign of R is changed by this subtrac-
tion, R is restored to its original value of 1111. C is decremented from 4 to 3, to complete the rst cycle.
The second cycle begins with one-bit left-shift of RQ jointly, inserting a 0 at LS bit of Q. This
transforms R to 1110 and Q to 1100, generating identical signs for R and V locations. Therefore, R is
replaced by R − V, which would be 0000 in this case. As the previous sign of R is changed by this sub-
traction at this point, R must be restored to its original value before subtraction (but after the left-shift),
which makes R as 1110 again. Location C is then decremented to 2 and we may enter in the third cycle.
The left-shift of RQ locations at the starting of third cycle makes R as 1101 and Q as 1000, as a 0
is inserted at LS bit of Q. At this point, we compare R with V and conclude that they are of same sign,
demanding a replacement of R by the value R − V. This changes R to 1111 maintaining the previous sign
of R unchanged. This is because the sign of R has not changed by subtraction, we have to set the LS
bit of Q as 1, which makes Q as 1001. We then decrement C by one, to make it 1 to end the third cycle.
The fourth and nal cycle starts with one-bit left-shift of RQ locations keeping R as 1111 and chang-
ing Q to 0010. As R and V have same signs, R is replaced by R − V, i.e., 0001. The change of sign of
R forces us to bring back R to its previous value of 1111. Location C is decremented to 0 at this point,
indicating the end of the division operation. Location Q holds the quotient, i.e., 0010 or decimal 2.
R holds the remainder in form of 1111, i.e., −1 in decimal when expressed in two’s complement form,
agreeing with the correct answer.
4.7 FLOATING-POINT NUMBER REPRESENTATION
So far we have restricted our discussions within the integer range. However, considering reality, we nd
that decimal arithmetic demands the usage of fractional numbers also. This is the reason for expressing
various decimal numbers by incorporating a decimal point, which we designate as real numbers to dif-
ferentiate from integers.
4.7.1 Signed-magnitude Representation
One straight-forward method is to express the integer (before the decimal point) part and fractional (after
the decimal point) part in two different locations, leaving aside one-bit as the sign bit for the integer part.
For the sake of example, let us assume that we are using 8-bit system. We leave aside the most signi cant
bit as sign bit. The next three bits are used to express the integer part. The last four bits are used to represent
the fractional part. Schematically, this is shown in Figure 4.19 (a), using +6.4 as an example case.
In this example case of representation, we nd that the non-fractional part, occupying bits 4, 5 and 6
can accommodate any value between 0 and 7. On the other hand, the fractional part, represented by least
signi cant four bits (0 to 3) can show any value between 0 and 9. Why is it so? This is because, although
with 4 bits we can accommodate a range of 0 to 15, however, for decimal representation, it falls short.
Either we should show between 0 and 9 (one place after decimal) or we must accommodate between 0
and 99 (two places after decimal). As with four bits we cannot accommodate beyond 15, therefore, we
restrict our fractional representation within one place after decimal.
Therefore, the maximum positive and negative number that we may express using this scheme would
be +7.9 and −7.9 (in the last case the sign bit would have 1). The smallest positive number we may repre-
sent would be +0.1 and the smallest negative number would be −0.1. As usual, for the signed-magnitude
scheme, we have two representations of zero, namely +0 and −0 [Figure 4.19 (c)]. In Figure 4.19 (b),
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