Contents xiii
6.3 Functions and Characteristics of Instructions 152
6.3.1 Data Move Type 152
6.3.2 Arithmetic and Logical Type 153
6.3.3 Program Flow Control Type 153
6.4 Addressing Modes 155
6.4.1 Immediate 156
6.4.2 Direct 157
6.4.3 Register Direct 157
6.4.4 Register Indirect 158
6.4.5 Relative 159
6.4.6 Implicit 159
6.4.7 Indexed 160
6.5 Instruction Formats and Fields 161
6.5.1 Role of Processor 162
6.5.2 Role of Instruction Set 162
6.5.3 Relation of Format and Field 163
6.6 8085 Instruction Set 163
6.6.1 Format and Fields 164
6.6.2 Discussions 167
6.7 8086 Instruction Set 168
6.7.1 Format and Fields 170
6.7.2 Discussions 172
6.8 8051 Instruction Set 172
6.8.1 Format and Fields 173
6.8.2 Discussions 174
6.9 Assembly Language Programming 174
6.9.1 Why Assembly Language Programming? 175
6.9.2 Assembly Language Program Format 176
6.9.3 Assembler Directives 177
6.9.4 Data Transfer and Manipulations 178
6.9.5 Loops and Loop Control 178
6.9.6 Program Branching 179
6.9.7 Subroutine Calls 179
6.10 Assembler 179
6.10.1 Two-pass Assembler 180
6.10.2 One-pass Assembler 180
6.10.3 Editor, Loader, Linker and Debugger 181
6.10.4 Macro 181
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xiv Contents
6.11 Intel 80386 Processor 182
6.11.1 80386 Instruction Set 182
6.11.2 Special Features 183
6.12 Intel Pentium 4 Processor 184
6.13 Solved Example 184
Summary 194
Points to Remember 195
Review Questions 195
7. The Memory System 198
Chapter Objectives 198
7.1 Introduction 198
7.2 Memory Classifi cation 198
7.2.1 Read Only Memory (ROM) 200
7.2.2 Read/Write Memory (RAM) 200
7.3 Memory Characteristics and Hierarchy 201
7.3.1 Access Time 201
7.3.2 Cost of Storage per Bit 202
7.3.3 Affordable Convenient Size 202
7.3.4 Memory Hierarchy 202
7.4 Cache Memory 204
7.4.1 Background of Cache Introduction 204
7.4.2 The Idea of Cache 206
7.4.3 How Does Cache Work? 206
7.4.4 Classifi cation of Cache 207
7.4.5 Levels of Cache 207
7.4.6 Cache in Intel Processors 207
7.4.7 Cache Hit and Hit Rate 208
7.4.8 Storing Results in Cache 208
7.4.9 Direct Mapped Cache 209
7.4.10 Solved Examples 211
7.4.11 Set Associative Cache 213
7.4.12 Fully Associative Cache 214
7.4.13 Replacement Algorithms 214
7.5 Main Memory 215
7.5.1 Dynamic RAM (DRAM) 215
7.5.2 DRAM Refreshing 216
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Contents xv
7.6 Secondary Memory 216
7.6.1 Hard Disc 216
7.6.2 Optical Disc 217
7.6.3 Magnetic Tape 218
7.7 Virtual Memory 218
7.7.1 Overlay 218
7.7.2 How Virtual Memory Works? 219
7.7.3 Paging in Virtual Memory 219
7.7.4 Virtual Memory in Intel Processors 220
7.8 Memory Management 221
7.8.1 DMA 221
7.8.2 Steps for a File Reading Operation using DMA 223
7.9 Intel 80386 Memory Organization 224
7.9.1 Physical and Logical Address 224
7.9.2 Selector-descriptor Tables 225
7.9.3 Protection in Multi-tasking Environment 226
7.9.4 Paging and Page Tables of 80386 227
7.10 Pentium 4 Memory Organization 228
7.10.1 Pentium 4 Data Types 229
7.11 Memory Decoding 229
7.11.1 Principle of Decoding 230
7.11.2 Types of Decoder 231
7.11.3 Common Issues of Memory Decoding 231
Summary 233
Points to Remember 234
Review Questions 235
8. Input/Output Organization 237
Chapter Objectives 237
8.1 Introduction 237
8.2 Basic Input/Output Structure of Computers 238
8.2.1 Interfacing and Communication Techniques 238
8.2.2 Classifi cation of Communication 240
8.3 Asynchronous Data Communication 240
8.3.1 Examples of Asynchronous Communication 240
8.4 Serial and Parallel Communications 241
8.4.1 Format of Serial Data Transfer 242
8.4.2 USART 242
8.4.3 Intel 8251 USART 243
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xvi Contents
8.5 Programmed I/O (Polling) 244
8.5.1 Sending Data Out 244
8.5.2 Receiving Data In 245
8.5.3 Intel 8255 PPI 245
8.6 Interrupt Driven I/O 246
8.6.1 Strobed Input Mode 246
8.6.2 Strobed Output Mode 247
8.6.3 Bidirectional Data Transfer Mode 248
8.6.4 Advantage of Interrupt Driven I/O 248
8.7 Interrupt Controller (8259) 249
8.7.1 8259 Without Cascading 250
8.7.2 8259 with Cascading 250
8.8 DMA 251
8.8.1 Intel 8237 DMA Controller 251
8.9 Device Drivers 253
8.10 Standard I/O Interfaces (Buses) 254
8.10.1 Genesis of Interfacing Buses 255
8.10.2 Universal Serial Bus (USB) 256
8.10.3 Small Computer System Interface (SCSI) 259
8.10.4 GPIB/HPIB/IEEE488 260
8.10.5 VME Bus 261
8.10.6 Multibus 261
8.11 Bus Arbitration 261
8.12 I/O Processor 262
8.13 Solved Example 263
Summary 263
Points to Remember 264
Review Questions 264
9. Microprogramming and Microarchitecture 267
Chapter Objectives 267
9.1 Introduction 267
9.1.1 Latching Data Available Within a Register 267
9.1.2 Data Flow Control from or to a Register 268
9.1.3 Need of Data Path Design 268
9.2 Problem of Allowing Data-fl ow 268
9.2.1 What is Expected? 268
9.2.2 Visualizing Data-fl ow and Registers 269
9.2.3 Data Path Design 269
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Contents xvii
9.2.4 Control Signal Requirements 271
9.2.5 Control Signals for Four General Purpose Registers (R0–R3) 272
9.2.6 Control Signals for Accumulator 273
9.2.7 Need of Microinstructions 274
9.2.8 Microinstructions for the Example Problem 275
9.3 Instruction Cycles of a Processor 277
9.4 Hardwired Control 278
9.4.1 Working of Hardwired Control 278
9.4.2 Advantages of Hardwired Control 279
9.4.3 Disadvantages of Hardwired Control 279
9.5 Programmed Control 280
9.5.1 Working of Programmed Control 280
9.5.2 Advantages of Programmed Control 280
9.5.3 Disadvantages of Programmed Control 280
9.6 Sequencing and Execution of Microinstructions 281
9.6.1 Example 1 (Load Accumulator by RO) 281
9.6.2 Example 2 (Save Accumulator in RO) 282
9.6.3 Example 3 (Add Accumulator with RO) 282
9.7 Solved Example 283
9.8 Utilizing System Clock 288
9.9 Processor Data Path Design 291
9.9.1 One Data Path (C-Bus) 292
9.9.2 Two Data Paths (B-Bus and C-Bus) 294
9.9.3 Three Data Paths (A-Bus, B-Bus and C-Bus) 295
9.10 Solved Example 295
Summary 297
Points to Remember 297
Review Questions 298
10. Control Unit Operation 301
Chapter Objectives 301
10.1 Introduction 301
10.2 Control Unit (CU) 302
10.3 Micro-operations 303
10.3.1 Fetch Cycle 303
10.3.2 Indirect Cycle (Operand Fetch) 307
10.3.3 Execute Cycle 308
10.3.4 Interrupt Cycle 308
10.3.5 Instruction Cycle 309
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