106 Computer Architecture and Organization
next instruction (18F3H) on stack-top and loads the program counter by the address of the subroutine
224BH. The reader may ask how does the processor know about the address of the subroutine? Well,
the address of the subroutine is included within the call instruction itself. The control is then transferred
automatically to the subroutine, which terminates with a Return instruction. During the execution of this
Return instruction, the processor always reloads the program counter from stack-top and, in this case, it
loads the program counter by the value 18F3H, which it had saved over the stack. Therefore, the control is
now automatically transferred to the next instruction after the call instruction, and the execution proceeds
sequentially thereafter. Stack is also essential for service interrupts, which we are about to discuss now.
5.6 INTERRUPTS
In all processors some input pin(s) are provided through which external devices can send signals to the
processor to draw its immediate attention. This attention may be necessary to receive a byte of data or
to terminate a process or similar features related with the external device – which is sending the exter-
nal signal. The major point is, it must be recognized as an urgent request and the processor must leave
everything whatsoever it was performing and must service the attention-drawing device immediately.
These inputs of the processor are designated as interrupt inputs and the procedure through which the
immediate need is ful lled is known as interrupt handling . The number of available interrupt inputs
varies from processor to processor. The minimum number is two while the maximum may be ve or
more. It may be noted that after servicing any interrupt, the processor must resume its original work,
which was left half-way because of the interrupt. This is achieved through the usage of the system stack.
5.6.1 Interrupt Service Routine (ISR)
To service any interrupt, the processor must execute a special routine developed to cater the need of the
interrupting device. These service routines are known as interrupt service routines (ISR) and terminated
by a RETURN (or similar) instruction. Before branching to the proper interrupt service routine, as it is
customary for the processor to store the address of the next executable instruction on the stack-top, the
execution of the RETURN instruction at the termination of ISR brings back the program control to its
original point, which it had left at the time of receiving the interrupt. In other words, an interrupt may
be visualized as an external hardware signal forcing the processor to execute a speci c subroutine, i.e.,
the ISR of the interrupting external device.
5.6.2 Vectored and Non-vectored Interrupts
Interrupts may be vectored or non-vectored, depending upon the provision of their pre-de ned branch-
ing address. If the branching address of the interrupt, where its ISR to be located is pre-de ned, then
the interrupt is designated as a vectored interrupt. On the other hand, if the interrupt is not assigned any
such pre-de ned branching address for its ISR, it would be taken as a non-vectored interrupt. In case of
a non-vectored interrupt, the branching address is to be supplied by the interrupting device itself.
5.6.3 Enabling, Disabling and Masking of Interrupts
In general, interrupts may be enabled or disabled by software commands. Furthermore, in some proces-
sor, they may also be masked or unmasked. Generally, after system reset, all interrupts are disabled.
They may be enabled by the programmer through some software command(s), according to the require-
ment. No external interrupt signal would be acknowledged if the interrupt is disabled.
Whenever any interrupt is acknowledged by the processor and branching for its ISR takes place, the
processor automatically disables that interrupt to ensure that further successive branching for that interrupt
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