Processor Basics 123
Continuing with our discussions on interrupt vector table of 8086, we nd that the lowest ve inter-
rupt types (Type 0 to Type 4) are pre-de ned (Figure 5.24 ). Sources of these interrupts are indicated in
Figure 5.24 . The next 27 interrupts (Type 5 to Type 31) are reserved by Intel (later used in 386). The
highest 224 interrupts (Type 32 to Type 255) are available for the programmer.
Let us now take Type 0 interrupt as an example case and see how 8086 handles its interrupts. If 8086
faces any situation of division by zero at the time of executing any division instruction (DIV or IDIV),
then automatically this interrupt is generated by 8086 itself.
To process this interrupt, 8086 decrements its SP by 2 and places (pushes) its 16-bit ag register on
the stack-top. Next, it clears both IF and TF ags of the ag register. The SP is again decremented by
2 and CS register is saved on the stack-top. SP is again decremented by 2 and IP register is saved on
the stack-top. CS is then loaded from memory location 00002H and 00003H. IP is then loaded from
memory location 00000H and 00001H. Control is then automatically transferred to the pre-de ned ISR,
whose base and offset address were stored in those memory locations. Note that 8086 automatically
saves its ag register but does not automatically save its accumulator. This has to be done, if necessary,
by the programmer within the ISR. Every ISR must be terminated by the IRET instruction.
For the purpose of processing external interrupt signals from multiple numbers of external devices
interfaced with 8086, one 8259 interrupt controller has to be interfaced with 8086. This 8259 would
use the INTR input to generate an external interrupt and subsequently 8086 would send two interrupt
acknowledge signals by making INTA low, twice. At the second INTA low duration, 8259 must send the
relevant interrupt type to 8086 and branching would be performed, as explained before. In Chapter 8,
details of 8259 interrupt controller is discussed.
5.8.10 Timing Diagrams
Before concluding our discussions on 8086, let us take a quick look at its timing diagrams. However,
instead of going for a detailed one, we shall study a simpli ed timing diagram, as presented in Figure 5.25 .
For a detailed timing diagram, manufacturer’s data sheet should be referred.
Figure 5.24 8086 interrupt vector details
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