Processor Basics 129
Interrupts may be individually enabled or disabled and there is a mechanism to disable all interrupts
simultaneously. Note that there is no non-maskable interrupt in 8051. Interrupt service routines of 8051
must be terminated by a RETI instruction, which enables further interrupts. Every interrupt has its
default priority, which may be modi ed dynamically by the program through the IP SFR.
External interrupts of 8051 may be programmed as either low level or falling edge sensitive. Timers
may be programmed in any one of the four modes available. In 8051, timer counters are incremented
(counts up), and whenever there is an over ow from FFFFH to 0000H, internal interrupts are generated.
In the case of serial communication, Timer 1 may be used as the baud rate generator .
5.9.9 Special Features
One of the special features of 8051 is its power management provisions. Through its PCON SFR (not
bit addressable) 8051 allows itself to switch into idle mode or sleep mode . During these power sav-
ing modes, processor clock is cut-off from certain internal modules of 8051, resulting in lesser power
demand. During this phase, port outputs remain unchanged and internal RAM locations retain their
original data. An external reset signal is necessary to come out from the sleep mode, while any interrupt
or reset would bring the processor out of its idle mode.
5.10 RISC AND CISC PROCESSORS
Every processor is designed to execute a set of instructions. Moreover, when used in computers, where
high-level languages are used, these instructions become more complex to make the compiler’s duty
simpler. A compiler translates any program written in high-level language to machine-understandable-
language or simply machine language. An increase in the number of complex instructions within the
instruction set of any processor would make the instruction decoding more complex and time-consuming.
It may be observed that in the late 1970s and early 1980s, the trend of processor was to incorporate
more and more complex instruction set. Furthermore, maintaining of backward compatibility with pre-
vious processors had been an added burden to the architectural design of these processors. All these
resulted in a different view point of the basic processor-design philosophy. Some designers started
thinking whether the incorporation of complex instruction set really enhances the throughput of the
processor or not. After all, the nal speed of execution is the key point for any processor and ‘faster and
faster’ is the buzz-word of the computer industry.
After conducting a considerable amount of analysis and research, designers understood the fact that,
although the complex instructions help the compilers in one way, in reality, they are not so widely
used by the processor. It is the simpler instructions that are executed more number of times than their
complex counterparts. The second point that came up is the relative speed of processor and memory.
Although both are on the path of improvement, the memory remains a slower device to communicate,
with respect to the execution speed of the processor.
5.10.1 Introduction of RISC Processors
RISC processor was initiated in Berkeley around 1980 by a small group of designers, who started design-
ing a new type of processors with reduced number of instruction set, avoiding all complex instructions.
Simpler instructions consume lesser time to be executed. Moreover, the memory access was limited to
data load and data store instructions only. It means that ‘ increment the content of a memory location by
one ’ type instructions are also avoided. To reduce the memory accessing time, larger number of registers
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130 Computer Architecture and Organization
was provided within the processor itself. Finally, pipeline architecture was adopted to make the instruc-
tion execution faster. The designers started designating these processor types as reduced instruction
set computing (RISC) processor. They designated other existing conventional processors as complex
instruction set computing (CISC) processor.
Although we cannot generate very accurate speci cations and there are always some grey areas or
‘fuzzy’ states in the demarcation, in general terms, common RISC processors have the following special
characteristics.
R Reduced and restricted number of instructions, e.g., within 50
R Simpler instructions, avoiding complex instructions
R Lesser number of addressing modes, mostly restricted to 5 or so
R Simple and uniform instruction format so that most instructions may be executed within one
machine cycle
R Larger number of registers within the processor to reduce external memory access time
R Pipeline architecture
Schematically, the difference between RISC and CISC is illustrated through Figure 5.29 . From the pool
of three processors, which we have discussed in earlier sections, it may be indicated that the architecture
of 8051 microcontroller is closer to RISC architecture, while the architecture adopted for 8086 might
be designated closer to CISC. Note that it does not mean that CISC processors do not adopt the pipe-
line architecture, or some other features of RISC. We should always remember that the basic objective
behind the RISC architecture is to make the processor work faster (even with the same clock speed).
Although we have introduced or elaborated some of these characteristics of RISC, the above character-
istics are discussed in a comprehensive manner in following text.
Figure 5.29 Schematic comparison between RISC and CISC architectures
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Processor Basics 131
5.10.2 Simple and Reduced Number of Instructions
It was already discussed that complexity of instruction decoding part of any processor increases with
the number of instructions to be decoded by it. Simpler structure of the instruction decoder enhances the
performance of any processor. Therefore, in RISC processors, the number of instructions is restricted
to a bare minimum. Strictly speaking, even multiply and divide type instructions are also considered as
complex instructions and only add and subtract type instructions are allowed in classical RISC architec-
ture. Some schools of thought indicate that even the subtract instruction is unnecessary for RISC as it
can be implemented by two’s complement addition (this idea is a controversial one).
Although these concepts still remain classical, the trend is to incorporate more and more complex
instructions within the instruction set and still designate the architecture as a RISC one. When asked
about the reason of the existence of complex instructions in a so-called RISC architecture, the answer is
always ‘because of the customer-demand ’ !
5.10.3 Lesser Addressing Modes
Addressing mode is the way in which a target data may be located. This would be discussed in details in
Chapter 6. However, we may point out at this stage that more addressing modes also make the instruc-
tion decoding more complicated. Moreover, all addressing modes may not be necessary or not used
very frequently. Provision of this type of rarely used addressing modes does not make the instruction
decoding an ef cient one.
5.10.4 Uniform Instruction Format
Instruction format is another aspect, which would be elaborately discussed in Chapter 6. Presently, it
may be pointed out that non-uniformity in the instruction length (number of bytes) forces the processor
for a poor performance. If all instructions are of uniform length, say 4-bytes, then the processor can skip
the decoding of how many bytes to be fetched for this instruction part. As an example case, the reader
may be advised to compare the instruction formats of 8085 and 8051 presented in Chapter 6.
5.10.5 More Registers
As indicated before, a memory oriented processor is to constantly access external memory even for sim-
pler operations, e.g., add two numbers and store. This external memory access is more time-consuming
than having all necessary operands within the processor itself, in its register set. The same set of internal
registers also may be used to store the results.
Although the optimum number of CPU registers is still a matter of debate, most RISC architecture
offers 32 or more internal registers within the processor. On the other hand, a CISC processor would
offer about six to eight internal registers for processor’s operand and result storage purpose.
5.10.6 Pipeline Architecture
In Chapter 12, we shall have a detailed discussion about pipeline architecture. However, at present it may
be indicated that the pre-fetching instruction bytes during decoding and execution of ongoing instruc-
tions speeds up the processing. Further ef ciency might be achieved by concurrent fetching, decoding,
operand fetching, execution and result storage operations. Therefore, adopting the pipeline architecture
became a must for any RISC processor. Incidentally, it is also adopted by most CISC processors.
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