Processor Basics 137
Figure 5.34 Maximum allowable segments of 80386 (in real mode) (Note that the
unused area is shaded)
registers (CS, DS, SS and ES) are still 16-bit wide (Figure 5.31 ). The method by which the 20-bit
physical address was generated by 8086 (Section 5.8.2 and Figure 5.20 ) is also applicable in the case of
80386. The only difference is that the offset registers are 32-bit wide.
One major difference in memory addressing between 8086 and 80386 is that in case of 8086, there
could have been a maximum of four memory segments available simultaneously for the processor as
there were four segment registers in 8086, namely CS, DS, SS and ES. On the other hand, in 80386,
the processor can operate with a maximum of six segments within its memory as there are a total of six
segment registers. Two new segment registers introduced in 80386 are GS and FS ( Figure 5.34 ), which
may be used to hold any base address. Note that GS and FS are data segment resisters.
The total physical memory of 4 GB is divided into four banks, namely Bank 0, Bank 1, Bank 2 and
Bank 3, each one containing 1 GB memory and organized as 1 GB ⫻ 8-bits (refer Figure 5.35 ). To
access 8-bit data, any one of these four banks may be accessed. If 16-bit data is necessary, then either
the combination of Bank 0 and Bank 1 or the combination of Bank 2 and Bank 3 need to be accessed.
For accessing 32-bit data, all four banks need to be simultaneously accessed. This had been possible
with the introduction of bank enabling signals BE0-BE3 (Figure 5.30 ). Recall that in the case of 8086,
it was the case of odd bank and even bank.
5.11.4 Timing Diagram
It was already indicated that 80386 divides its clock input through its CLK2 pin by two to generate its
internal clock. Therefore, every T-state of 80386 includes two oscillations of the external clock source,
as shown in the timing diagram in Figure 5.36 .
M05_GHOS1557_01_SE_C05.indd 137M05_GHOS1557_01_SE_C05.indd 137 4/29/11 5:07 PM4/29/11 5:07 PM
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