Processor Basics 143
Figure 5.40 Scheduler and branch table buffer in Pentium 4
(16 kB)
(512 kB)
To achieve all these duty allocation, Pentium 4 is equipped with a scheduler, rename/allocation unit
and branch target buffer. As both conditional as well as unconditional branching operations change the
next opcode fetch address, advance prediction of such branching helps the pre-fetch operation block
to pre-fetch the correct stream of instructions. We shall discuss more about this branch prediction in
Chapter 12. However, at present, let us note that inside Pentium 4, we can nd the scheduler and other
related modules, as indicated in Figure 5.40 .
At this stage the reader’s attention is drawn to the types and sizes of all cache memories available in
Pentium 4, as shown in the diagram (Figure 3.40). A large sized L3 cache of 1 MB is placed within the
processor to store both instruction as well as data words.
Pentium 4 offers a split-cache system (separate cache for instruction and data) for its L1 cache. The
size of data cache is 16 kB and that of instruction cache is 12 kB. Between these L1 and L3 caches, there
is a L2 cache of 512 kB. We shall discuss more about these memory details in Chapter 7.
5.12.3 Register Set
Integer registers of Pentium 4 processor are shown in Figure 5.41 . The areas with darker shade were
introduced in Pentium for 64-bit conversion. Areas with lighter shade were introduced in 80386 for
32-bit conversion (refer Figure 5.32 ). Areas without any shade represent registers available in 8086
(refer Figure 5.19 ). R8 through R15 are new registers for general purpose operations.
Apart from these general purpose registers, Pentium 4 contains several other registers, which we
shall introduce in later chapters as required.
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