144 Computer Architecture and Organization
SUMMARY
Processors are to be interfaced with external memory and I/O devices through its system bus com-
posed of address, data and control signals. Power, clock and reset are most common and minimum
inputs to make any processor functional. Continuously fetching, decoding and executing instruc-
tions are major duties of all processors. Every processor offers its own instruction set, composed
of arithmetic, logical, program branching and other necessary instructions. In general, they offer
a few external interrupt input pins and when any one of these pins are activated by a valid signal,
the processor branches to a pre-de ned address to execute the ISR of that interrupt, after saving the
return address on the stack-top. System stack is an area within system RAM where return address
for subroutine calls and other important data and register contents may be temporarily saved in
LIFO scheme.
Intel 8085 is an 8-bit microprocessor with 16 address lines and 8 data lines capable of directly
addressing externally interfaced 64 kB of memory. Fabricated around Princeton architecture, it needs an
external crystal, whose frequency is internally divided by two to generate its system clock. The lower 8
address lines are multiplexed with 8 data lines, which may be de-multiplexed by the falling edge of the
ALE signal. Intel 8085 offers I/O mapped I/O scheme through its IO/M signal, which goes low during
any memory cycle but stays high during any I/O cycle. Five vectored external hardware interrupt inputs
are offered as TRAP, RST7.5, RST6.5, RST5.5 and INTR. Its INTA output serves as the acknowledge
signal for INTR input only and may be used to receive the branching address for its ISR. 8085 offers all
necessary instructions like arithmetic, logical, program branching and so on.
Figure 5.41 Pentium 4 integer register set
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Processor Basics 145
Intel 8086 is a 16-bit processor with pipeline architecture, fabricated around Princeton architecture.
Internally, it is divided in two major units, known as bus interface unit (BIU) and execution unit (EU).
8086 offers 16 data lines and 20 address lines and capable of directly addressing 1 MB of external
memory using its address lines along with its BHE signal. The memory system is divided in odd and
even banks, selected by BHE and A0 signals, respectively. 8086 uses the base and offset register scheme
to generate 20-bit memory address using two 16-bit registers. This technique ensures that the bound-
ary of any program segment is not violated. After a reset, 8086 starts executing from memory address
FFFF0H. It provides two external interrupt inputs, NMI and INTR, and offers 256 types of interrupts
through its 1 kB interrupt vector table located between memory addresses 00000H and 003FFH. Wide
varieties of instructions are available in 8086 with signed and unsigned multiply and divide instructions,
string manipulation instructions, etc.
Intel 8051 is the 8-bit microcontroller of Intel MCS-51 family having many variations. It offers
4k program memory, 128-bytes of data memory, 4 8-bit I/O ports, two 16-bit timers and an USART
for serial communications. Internally, it is designed around Harvard architecture, which distinguishes
between program and data memory. It has four register banks, each with eight 8-bit registers along with
some special function registers (SFRs) e.g., A, B, PSW, SP, DPTR and so on. 8051 offers two external
interrupt inputs, whose activating signal type is programmable as either falling edge or low level. Provi-
sions are there to externally interface extra program and data memory within a total limit of 64 kB for
each type of memory. 8051 offers two power management modes for power saving when it is not fully
operational. A rich set of instructions are offered by 8051 with unsigned multiply and divide instruc-
tions. Bit-oriented instructions are also offered by this microcontroller, which helps in developing ef -
cient software for control operations.
With respect to the CISC architecture, RISC architecture based processors offer reduced number of
simpler instructions with lesser addressing modes and uniform instruction format. The number of CPU
registers is more so that lesser time is devoted by processor for external memory data transactions. In
general, pipeline architecture is adopted to make the processor execute faster.
Intel 80386 is the rst 32-bit processor from Intel and the rst processor to implement the idea of
cache memory, although to be externally interfaced. With 32 address lines it is capable of directly
addressing 4 GB of external memory space and has the capability of handling 64 TB of virtual
memory. Unlike 8086, its data lines are not multiplexed with address lines although it is backward
compatible with 8086. The smaller pipeline of 8086 is enhanced to a 3-stage pipeline in 80386 with
the provision of storing three decoded instructions in a queue for faster execution. The processor has
a barrel shifter within its ALU module. Its 32-bit register set are extended form of 16-bit register set
of 8086 and designated as EAX, EBX and so on. It can operate in real mode, protected mode and
virtual mode. In real mode operation, it functions like 8086 processor and its internal 32-bit registers
are truncated to 16-bit registers and the capability of addressing externally interfaced memory is
reduced to 1 MB only, the same size as addressed by 8086. Two 16-bit registers namely GS and FS
are included within its register set which were not available in 8086. These two registers are expected
to function like other similar segment registers. The processor is designed for multi-tasking operation
and offers several condition ags within its ag register. It supports paging memory system and can
handle page tables.
Pentium 4 is a superscalar processor from Intel offering 64 address lines and 64 data lines
which make it a full fledged 64-bit processor. Its 20-stage pipeline supports out-of-order execu-
tion, register renaming and speculative execution with improved branch prediction techniques
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