146 Computer Architecture and Organization
and additional features to support faster execution of calculations related with multimedia opera-
tions. Although, externally it is a CISC processor, internally it functions like a RISC processor
as its instructions are converted to RISC-like micro-codes before their execution. These micro-
codes are of very small numbers and speeds up the pipelined operation of the processor. Pentium
4 offers all three types of cache memory and its L1 cache is a split-cache, separate for holding
instruction and data.
POINTS TO REMEMBER
R Both 8085 and 8086 are fabricated around Princeton architecture, while 8051 around Harvard
architecture.
R Memory handling technique of 8086 is widely different from that of 8085.
R Unlike 8085, 8086 needs an interrupt vector table to nd the entry point of any of its 256 ISR.
R 8051 offers power management features to conserve the system’s power consumption.
R RISC processors have lesser number of simpler instructions with adequate internal registers within
the processor and adopts the pipeline architecture.
QUICKSAND CORNER
During my class hours one of my students asked
why I was citing examples from obsolete proces-
sors like 8085 or 8086. It is well-known that 8085
is no longer manufactured by any manufacturer
throughout the world. When I asked back which
processor I should adopt as example case, the
reply was Intel Celeron, the latest from Intel at
that time.
I appreciated the student’s frank suggestions
and enquired whether the difference between SR
ip- op and JK ip- op is known to him or not.
As there was no answer, I pointed out that certain
drawback of SR ip- op is eliminated in JK ip-
op, and unless we are clear about the drawbacks
of SR ip- op, the study of JK ip- op would not
be so meaningful.
Then I came to the point and explained that
although 8085 is an obsolete processor, as it is
still in syllabi, its study would de nitely bene t
any student. Furthermore, if one processor is thor-
oughly understood, other processors become eas-
ier to grasp. Finally, directly jumping to Celeron
or Pentium would be counter-productive unless
the basics and background are cleared.
Target the Correct Option
1. An instruction cycle means
(a) M1, M2, M3
(b) fetch, decode, execute
(c) get operands, add operands, store result
(d) none of these
2. For fetching an instruction byte, the processor
is to provide the external memory device
(a) address and read signals
(b) data and read signals
(c) address and write signals
(d) none of these
REVIEW QUESTIONS
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Processor Basics 147
1. How the processor communicates to the tar-
get device only, while multiple devices are
interfaced with the processor?
2. What are the methods available for instruc-
tion decoding to a processor?
3. How many read and write cycles are generated
by 8085 to execute the OUT port instruction?
4. Which types of signals are necessary to acti-
vate the external interrupts of 8085?
5. What purpose is served by the ALE signal in
8085, 8086 and 8051?
6. How the even and odd memory banks are
interfaced with 8086?
7. What is the function of TEST input of 8086?
8. Which purpose is served by the PSEN sig-
nal of 8051? Is it an input signal or an output
signal?
9. What output we may expect from port pins of
8051 just after a system reset?
10. Apart from Vcc, Vss, XTAL1, XTAL2,
RESET and EA, is there any other pin of 8051
to receive an input to make 8051 functional?
3. The number of external hardware interrupt
input pins offered by 8085 microprocessor
is
(a) 2 (c) 5
(b) 4 (d) none of these
4. Which of the following ags is not available
in 8085 but available in 8086?
(a) carry ag (c) trap ag
(b) zero ag (d) none of these
5. Which of the following interrupts of 8085 is
acknowledged by INTA?
(a) TRAP (c) RST6.5
(b) RST7.5 (d) none of these
6. The number of bytes in the queue of instruc-
tion pipeline for 8086 is
(a) 8 (c) 1
(b) 6 (d) none of these
7. If the MN/MX input of 8086 is connected
with system ground (GND) then 8086
(a) does not allow any interrupts
(b) assumes no processor to share the bus
(c) assumes the system bus to be shared
(d) none of these
8. To generate the system clock, 8086-based sys-
tem divides the frequency of external crystal by
(a) 3 (c) 12
(b) 2 (d) none of these
9. With accumulator, which of the following
registers of 8051 helps in multiply and divide
instruction execution?
(a) B (c) DPTR
(b) TMOD (d) none of these
10. Modes offered by 8051 for its power manage-
ment are designated as
(a) sleep and deep sleep
(b) sleep, deep sleep and dream
(c) stand by, sleep and deep sleep
(d) none of these
Find in Few Seconds
Spend Some Time Here
1. Explain why the system clock is most impor-
tant for functioning of any processor.
2. What are the advantages and disadvantages
of memory oriented and register oriented
processors?
3. Why there should be any provision of dis-
abling an interrupt?
4. Why the I/O address is duplicated at the
higher address bus during I/O cycle of
8085?
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5. What might have been the problem if 8086
did not provide any BHE or similar signal?
6. What is the importance of memory segmenta-
tion in 8086?
7. What might have been the problem if 8086
was designed to address 1 M words (double
bytes) of memory directly?
8. Can you visualize the 8086 processor without
its ALE signal? Justify your answer.
9. How 8051 controls its power requirements?
10. Using internet, make a list of family members
of 8051.
148 Computer Architecture and Organization
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