Contents xxiii
Appendix-B. SPARC and UltraSPARC 449
Objectives 449
B.1 Introduction 449
B.2 Background 449
B.2.1 RISC Characteristics 450
B.2.2 Design History 450
B.3 Functional Overview 450
B.4 SPARC and UltraSPARC Register Set 451
B.4.1 Special Features 452
B.5 Internal Architecture 453
B.6 Pipelining 454
B.7 Instruction Format 455
B.8 Instruction Set 456
Summary 459
Points to Remember 460
Review Questions 460
Appendix-C. Power PC 463
Objectives 463
C.1 Introduction 463
C.2 Background 463
C.3 Internal Architecture 464
C.4 Register Set of Power PC 465
C.5 Power PC Instruction Set 467
C.6 Pipeline of Power PC 470
C.6.1 Branch Processing by Power PC 471
C.7 Data Types of Power PC 472
Summary 472
Points to Remember 472
Review Questions 473
Appendix-D. Intel Core2Duo 475
Objectives 475
D.1 Difference Between Dual Core and Core2Duo 475
D.2 Salient Features of Core2Duo 476
D.3 A Few Important Signals 477
D.4 Low-power States and Power Management 479
D.5 Internal Architecture 481
D.6 Instruction Set 482
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xxiv Contents
Summary 491
Points to Remember 492
Review Questions 492
Appendix-E. MIPS R4000 494
Objectives 494
E.1 Introduction 494
E.2 General Architecture 495
E.3 External Signals 496
E.4 Internal Architecture 497
E.5 Register Set 499
E.6 MIPS R-Series Instruction Set 499
E.7 Instruction Format 503
E.8 Pipeline 504
E.9 Memory Management 505
E.10 Exception Processing of MIPS R4000 506
Summary 507
Points to Remember 507
Review Questions 507
Appendix-F. Project Bank 510
Answers for Target the Correct Option 522
Glossary 524
Acronyms 533
Bibliography 535
Index 537
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