Instruction Set and Assembly Language Programming 163
other hand, for a RISC processor with lesser number of instruction types, lesser number of bits would be
required to encode the instructions. For the sake of example, the reader may compare the simple instruc-
tion format of 8051 designed like a RISC processor with the complex instruction format of 8086, designed
as a CISC processor — both presented at the end of this chapter. The complexity of instruction format of
8086 is further enhanced in processors like 80386 and Pentium 4 to make those backward compatible.
6.5.3 Relation of Format and Field
Format and eld specify two different aspects of any instruction. Field speci es the number of bits necessary
to accommodate a particular parameter, e.g., an operand’s address. The format of an instruction speci es
number and order of these elds, including the opcode, which is generally placed at the beginning of the
instruction. As an example case, we may refer to Figure 6.9(b). The processor might be offering 32 internal
registers and in that case the eld of ‘reg’ would need 5 bits of space. Remaining bits would be allowed for
the ‘opcode’ part. However, if the processor offers only eight internal registers, then 3 bits instead of 5 would
be suf cient to specify the target register. The same characteristics are illustrated through Figure 6.10.
We now discuss about the instruction set related with the three processors, which have been intro-
duced in Chapter 5, namely, 8085, 8086 and 8051. Subsequently, we shall discuss about two advanced
processors, 80386 and Pentium 4.
6.6 8085 INSTRUCTION SET
The 8-bit processor 8085 (introduced around 1976) offers 246 opcodes for its 80 instructions, which
may be divided into ve major groups, as follows:
R Data transfer (10 instructions)
R Arithmetic (17 instructions)
R Logical (12 instructions)
R Program branching (29 instructions), and
R Machine control (12 instructions).
All instructions of these groups are presented in Table 6.5 . Note that 8085 was designed to be back-
ward compatible with its earlier version, 8080, and offers only two new instructions, RIM and SIM,
which were not included in 8080. As we have already indicated, maintaining this backward compatibil-
ity is sometimes a major challenge in the architectural design of a new processor.
Data transfer Arithmetic Logical Program branching Machine control
MOV ADD ANA JMP PUSH
XCHG ADC ORA JNZ POP
MVI SUB XRA JZ XTHL
LXI SBB CMP JNC SPHL
LDAX DAD RLC JC OUT
STAX INR RRC JPO IN
LHLD INX RAL JPE DI
(Continued)
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164 Computer Architecture and Organization
Data transfer Arithmetic Logical Program branching Machine control
SHLD DCR RAR JP EI
LDA DCX ANI JM NOP
STA DAA ORI PCHL HLT
CMA XRI CALL SIM
STC CPI CNZ RIM
CMC CZ
ADI CNC
ACI CC
SUI CPO
SBI CPE
CP
CM
RET
RNZ
RZ
RNC
RC
RPO
RPE
RP
RM
RST
Table 6.5 8085 instruction set
6.6.1 Format and Fields
A detailed study of format and elds of 8085 instruction set would enlighten specially those who are
new to the subject. The reason behind this is the fact that 8085 is comparatively a simpler processor with
only a few instructions and with relatively an uncomplicated instruction format. As a matter of fact, only
the rst byte of any of its instructions contains the opcode. If there are successive bytes, they contain
either data or address. Format and eld details of all 8085 instructions are presented in Figure 6.11. We
nd that a total of 12 formats are found and the length of instructions vary between one and three bytes,
with the opcode as its rst byte, as already indicated. In many cases some portion of the rst byte is used
for operand indication. Leaving that part, the opcode portions of rst byte in all cases are lightly shaded,
indicating the location of opcode. Note that in some cases, a 2-bit eld marked as ‘rp’ is used to indicate
a register pair. In 8085, rp denotes BC, DE or HL register pairs or SP, the stack pointer.
Figure 6.11 (a) shows the simplest format of all, where the 8-bit opcode speci es the action to be
implemented by the processor. The operand, if any, is implicit in these cases, like accumulator for
instructions CMA (complement accumulator), DAA (decimal adjust accumulator), RAL (rotate accu-
mulator left through carry), RAR (rotate accumulator right through carry), RLC, RRC or the carry ag
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Instruction Set and Assembly Language Programming 165
for instructions CMC (complement carry), STC (set carry), and so on. Some instructions are related with
processor control, e.g., EI (enable interrupt), DI (disable interrupt), HLT (halt the processor) and NOP (no
operation). All these are one byte instructions.
The second group, indicated in Figure 6.3 (b), is also for one-byte instructions. However, in this
category, an accumulator is one of the two operands and the other may be as indicated through ‘reg’
eld (register direct type addressing mode). This ‘reg’ eld is of three bits occupying least signi cant
three bits and most signi cant, 5 bits of the instruction byte, is left to accommodate the opcode. The
three bits of ‘reg’ eld may specify any one of the register A, B, C, D, E, H, L and M. The last one is
an external memory location whose address must be within HL register pair (this one would be register
indirect addressing mode). The task of these instructions is to add (ADD), add with carry (ADC), sub-
tract (SUB), subtract with borrow (SBB), logically AND (ANA), OR (ORA), XOR (XRA) or compare
(CMP) the indicated operand with the accumulator. It may be pointed out that as the accumulator is a
part of the operand set indicated by three bits’ con guration, operations like subtract A from A or add
A with A may also be implemented by these set of instructions. One instructive point is that if 8085 had
been equipped with only four registers , then this ‘reg’ eld would have been of two bits instead of three
bits. Incidentally, this is very similar to the next format.
Figure 6.11 (c) shows an instruction format applicable only for two instructions, LDAX and STAX.
Instruction LDAX loads accumulator from external memory content (byte) whose address is within a
register pair. This register pair might be either BC or DE. Instruction STAX performs exactly the oppo-
site, i.e., storing the accumulator content to a memory location speci ed by the register pair (BC or DE).
Figure 6.11 Format and fields of 8085 instruction set
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166 Computer Architecture and Organization
As only two pairs are allowed, bit 4 of this instruction is used to indicate that to the processor. The
remaining bits (0 to 3 and 5 to 7) are used for the opcode.
Register pairs are also involved in instructions, e.g., INX (increment register pair by one), DCX
(decrement register pair by one), PUSH (store register pair over stack), POP (restore register pair from
stack) and DAD (add register pair with HL register pair). The allowed register pairs in these cases are
BC, DE, HL and SP or AF. To accommodate four pairs of registers, a 2-bit eld (bits 4 and 5) is set aside
for instruction format depicted in Figure 6.11 (d). The remaining part of the byte is left for the opcode.
The next instruction format, shown in Figure 6.11 (e), handles three types of instructions. INR is
increment by one and DCR is decrement by one. In both cases, any one of seven registers (A, B, C, D, E,
H or L) or a memory location M, whose address is presently within HL register pair, may be speci ed to
hold the operand. Another instruction, RST, also allowed the same format. However, RST is the restart
instruction, which may be taken as a software interrupt instruction. This RST instruction varies from
RST0 to RST7 and this 0 – 7 has to be accommodated within three bits of the instruction byte, namely
bit 3 – 5. These integers (0 – 7) helps in calculating the jump address for these restart instructions. In the
other two cases (INR and DCR) the same three bits hold the code of target register.
A question may arise, that what is the use of re-structuring the instruction format shown in Figure 6.11(b),
which also deals with identical set of register along with a memory locating indicating register pair? As a
matter of fact, there is no difference between the two instruction-formats shown in the part Figure 6.11(b)
and (e). At this stage, this may be indicated as the answer that the backward compatibility introduces for
various special issues in any processor design and that 8085 was backward compatible with 8080.
We have eight conditional return (from subroutine) instructions in 8085. These eight instructions are
accommodated within the instruction format shown in Figure 6.11 (f). Note that within this one-byte
opcode, bits 3 to 5 specify one of the eight branch conditions.
The last format for one byte instructions, shown in Figure 6.11 (g), was allowed for MOV instruction.
This one byte instruction can copy a byte from any register or memory location (indicated by HL pair) to
any register or memory location, with one exception. From memory to memory copy is not allowed. That
is the reason for 63 possibilities (variations) of this instruction against a maximum of 64 possibilities avail-
able for eight types of source locations and eight types of destination locations.
The next two instruction formats are two bytes in length. The second byte in both cases contains
the immediate data. For MVI instruction shown in Figure 6.11(i), this immediate data has to be loaded
within one of the eight registers (or memory location indicated by HL), as indicated through bits 3 – 5
of the rst byte of the instruction. Remaining part of the rst byte contains the opcode. However, the
operand location in the instruction format shown in Figure 6.11 (h) is implicit and in most cases it is the
This may be more prominent in 8051 instruction set format, where only four format types
are necessary to accommodate all 255 instructions as compared to 246 of 8085. When one
compares between Figure 6.11 and Figure 6.16, one can note that the instruction set of
8051 is better than 8085 and the number of general purpose registers is also more in the
case of 8051. This clearly indicates that a fresh architectural design without the burden of
any backward compatibility makes the instruction format more efficient and optimum.
F
O
O
D
F
O
R
T
H
O
U
G
H
T
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Instruction Set and Assembly Language Programming 167
accumulator. Only IN and OUT instructions deal with the input or output ports, addressed by the second
byte of the instruction. Note that in 8085 port addresses are 8-bit, while memory addresses are 16-bit.
The last three instruction types have 3-byte format. The second and third bytes in these cases contain
either the target address, LSB followed by MSB, or 16-bit data. 8085 offers only one instruction, LXI, to
load 16-bit data to a register pair, indicated in bits 4 and 5 of the rst byte of the instruction, as shown in
Figure 6.11 (l). Observe the similarity of this eld (bits 4 and 5) with the format shown in Figure 6.11 (d),
as the register pairs are also identical in both cases.
Figure 6.11 (k) shows the format for eight conditional jump and eight conditional call instructions.
Note that in both cases 16-bit address is speci ed by second and third bytes of the instruction. The
conditions are speci ed through bits 3 – 5 of the rst byte of the instruction, identical with one byte
conditional return instruction shown in Figure 6.11 (f).
Instructions that do not demand any operand (CALL or JMP) or have implicit addressing mode (like
LDA or STA) but need the help of 16-bit target address, are placed in the group shown in Figure 6.11 (j).
In this case, instruction LHLD or SHLD, respectively, loads or stores register pair HL to or from the
indicated memory address.
6.6.2 Discussions
At present, we do not have either the need or the scope for a detailed discussion on all instructions of
8085. However, we point out certain interesting facts related with these instructions after this explana-
tion of all instruction formats adopted by 8085, presented in Section 6.6.1.
At a rst glance at Table 6.5 , the reader might conclude that 8085 offers more instructions for program
branching than data transfer (29 vs 10). However, if we pick up the MOV instruction from data transfer
group, then we nd that this instruction offers 63 variations. The format of this move instruction is
MOV destination register, source register.
We already know from Chapter 5 (Figure 5.15) that 8085 offers seven general purpose 8-bit registers,
namely A, B, C, D, E, H and L. Each one of these seven registers might be a source or a destination. More-
over, any memory location addressed by the HL register pair might also be a source or destination for the
MOV instruction. All these resulted in 63 variations of MOV instruction. Of course, instructions like MOV
A, A are also included within this set of 63 instructions, which are of no use (except to kill time of the pro-
cessor in the same way as the NOP instruction). However, this scheme had made the data transfer within the
processor (or its outside) more ef cient, as all MOV instructions are single byte instructions consuming one
machine cycle for its execution. Only the memory oriented MOV instructions demand two machine cycles.
On the other side, inclusion of so many conditional CALL and conditional return instructions in the
instruction set of 8085 seems to be counter-productive. A study on the usage of these instructions might
have indicated that they are used in a very limited manner within any program body. This might be the
reason of excluding these conditional CALL and conditional return instructions from the instruction set
of 8086 ( Table 6.6 ) – the successor of 8085. If we compare instruction sets of 8085 and 8051 ( Table 6.7 ),
then we may also observe the identical trend.
The above discussions clarify one of the main design considerations for the instruction set of any pro-
cessor. In general, there is always an upper limit of the number of instructions (opcodes or machine codes)
for any processor. For example, being an 8-bit processor, 8085 had an upper limit of 256 instructions as it
used only the rst byte of all instructions as the opcode. The second and third bytes of all 2-byte and 3-byte
instructions of 8085 contained either data (8-bit or 16-bit) or address (16-bit). To make the instruction set
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