184 Computer Architecture and Organization
6.12 INTEL PENTIUM 4 PROCESSOR
Through its Pentium processors, Intel has introduced several new instructions, which are presented
in Table 6.9 . Note that these instructions help the operating system to perform the duty more easily.
For example, the instruction CMPXCHG8B is capable of exchanging 8 bytes in one cycle, which
helps to speed up the maintenance of linked lists. Instructions like CPUID help in maintaining the
security features.
Instruction Brief description
CMPXCHG8B Compare and exchange 8 bytes at a time
CPUID After execution of this instruction make the CPU identi cation
codes available in registers EAX, EBX, ECX and EDX
RDMSR Read model speci c register
RDTSC Read Time Stamp Counter
RSM Return from system management interrupt
WRMSR Write in model speci c register
Table 6.9 New instructions for Pentium
6.13 SOLVED EXAMPLE
Designing the instruction set of any processor is a professional project, demanding knowledge and com-
plete attention of the design-team. The boundary conditions of this type of project vary widely. Many
assumptions undertaken at different stages of the design process need to be veri ed for their validity and
might have to be cleared by other designing groups.
In this solved example, the reader is placed in a similar situation but with a simpler problem, offer-
ing lesser dif culties. However, like all other design-based problems, the present solution, steps and
assumptions leading to it may not be considered as unique.
Problem 6.1
Design the instruction set of a 4-bit microcontroller, proposed to be used only for table calculators.
Make all necessary assumptions for it.
Solution 6.1
The following assumptions are made regarding solution:
1. Processor would be designed around Harvard architecture, treating program and data memory,
separately.
2. 2K nibbles of internal program memory.
3. 16 internal RAM locations, each of the four bits, excluding internal registers and system stack.
4. Separate stack of 16 nibbles at a xed location without any SP accessible by the program developer.
5. Two register banks, any one selectable at any time through software.
6. Each register bank with eight registers including one accumulator and one ag register.
7. All registers are 4-bit wide.
M06_GHOS1557_01_SE_C06.indd 184M06_GHOS1557_01_SE_C06.indd 184 4/29/11 5:09 PM4/29/11 5:09 PM
Instruction Set and Assembly Language Programming 185
8. PC not accessible to the program developer except loading it.
9. Eight 4-bit bidirectional I/O ports.
10. Interrupts are not taken into account.
11. No internal timers.
12. RISC architecture.
Figure 6.19 Basic assumptions regarding (a) Ports (b) Internal architecture and
(c) Internal registers and flags of the 4-bit microcontroller
These assumptions are depicted in Figure 6.19 . From these assumptions certain conclusions may be
drawn, as follows:
(i) To address 2K program memory, the PC must be of 11 bits. We may provide a PC of 12 bits
(3 nibbles) so that at a later stage program memory size may be extended to 4K without any
other change.
(ii) During subroutine calls, three nibbles to be placed on the stack top and at the time of executing
return instruction, three nibbles to be loaded in PC from stack top. Therefore, with a 16-nibble
stack, a maximum of ve subroutine nesting would be allowed, with no other additional usage
of the stack. If other registers are saved, the depth of this nesting would be reduced.
(iii) Opcode for all instruction would be two nibbles in length. For immediate data, one more nibble
would be added with it. For addressing data memory, one extra nibble is suf cient. For jump
and call instructions, direct address of program memory would be placed in last three nibbles of
5-nibble opcodes.
Instruction Selection
The total number of instructions may be restricted to 32. Only two instructions would be provided to
communicate with on chip data memory for loading and storing accumulator. Taking these points into
consideration, the following data move instructions may be offered:
1. Move immediate to register (eight instructions) for immediate loading of any one of eight registers of
currently selected register bank. This would need three nibbles, last nibble containing immediate data.
2. Move accumulator to memory (one instruction) for storing accumulator in directly addressed
data memory location. Three nibble instruction with data memory address in third nibble.
M06_GHOS1557_01_SE_C06.indd 185M06_GHOS1557_01_SE_C06.indd 185 4/29/11 5:09 PM4/29/11 5:09 PM
186 Computer Architecture and Organization
3. Move memory to accumulator (one instruction) for loading from memory. Three-nibble instruc-
tion; third nibble would contain data memory address.
4. Copy from register to register (56 instructions) for general purpose data transaction. Source and
destination cannot be the same location. This would be 2-nibble instruction with source and
destination register address consuming six bits at the end.
5. Push register on stack top (eight instructions) to save any one of eight registers of currently
selected bank on stack top. This would take two nibbles, with register code in last three bits.
6. Pop register from stack (eight instructions) the opposite of push instruction. This would take two
nibbles.
7. Read from addressed port to accumulator (one instruction). Three nibble opcode with port
address at last nibble.
8. Write accumulator to port (one instruction). Three nibble opcode with port address at last nibble.
9. Select the other register bank (one instruction) to exchange all eight registers. Two nibble
opcode.
10. Exchange accumulators (one instruction) between active and passive accumulators. Two nibble
opcode.
11. Exchange ag registers (one instruction) between active and passive ag registers. Two nibble
opcode.
12. Interchange contents of accumulator and indicated register except accumulator (seven instruc-
tions). Two nibble opcode.
Next comes the selection of arithmetic instructions. Here, we follow true RISC architecture and offer
instructions for add with register, add immediate, increment by 1 and decrement by 1. No subtraction
instruction is provided as it may be implemented by two’s complement addition. Moreover, adding
immediate data is applicable only for accumulator. Note that add without carry instruction is not pro-
vided as it may be implemented by clearing the carry ag before using add with carry instruction. Based
on these considerations, following arithmetic instructions are offered:
1. Add accumulator and indicated register with carry (eight instructions). Two-nibble opcode.
2. Add immediate data with accumulator with carry (one instruction). Three-nibble instruction with
immediate data in third nibble.
3. Increment register content by 1 (seven instructions) not applicable for ag register. Two-nibble
opcode.
4. Decrement register content by 1 (seven instructions) not applicable for ag register. Two-nibble
opcode.
For logical instruction set, rotate accumulator is a must and all four rotate type instruction, i.e.,
rotate left or right and circular or through carry should be provided. Operations for AND, OR are
necessary between accumulator and any other register. For immediate data, only accumulator is suf-
cient. Note that XOR operation may be implemented through other logical operations. Therefore,
no instruction for XOR operation is provided. Instructions for complementing all eight registers and
carry ag and also clearing carry ag are accommodated. The scope of complementing any register
would make subtraction operation easier in two’s complement addition technique. Following logical
instructions may be provided:
M06_GHOS1557_01_SE_C06.indd 186M06_GHOS1557_01_SE_C06.indd 186 4/29/11 5:09 PM4/29/11 5:09 PM
Instruction Set and Assembly Language Programming 187
1. Rotate accumulator left through carry (one instruction) with 2-nibble opcode.
2. Rotate accumulator right through carry (one instruction) with 2-nibble opcode.
3. Rotate accumulator left circular (one instruction) with 2-nibble opcode.
4. Rotate accumulator right circular (one instruction) with 2-nibble opcode.
5. Logically AND accumulator with indicated register (eight instructions) with 2-nibble
opcode.
6. Logically AND accumulator with immediate data (one instruction) with 3-nibble opcode.
7. Logically OR accumulator with indicated register (eight instructions) with 2-nibble opcode.
8. Logically OR accumulator with immediate data (one instriction) with 3-nibble opcode.
9. Complement indicated register (eight instructions) with 2-nibble opcode.
10. Complement carry ag (one instruction) with 2-nibble opcode.
11. Clear carry ag (one instruction) with 2-nibble opcode.
Program branching instructions are kept at a minimum. Two conditional jump instructions, jump
if carry is set and jump if zero, are suf cient. Jump if no carry and jump if not zero may be indirectly
implemented by the previous two instructions. One unconditional jump and one unconditional call
instruction with an unconditional return instruction complete the instruction set. Note that in rst four
instruction, complete branching address is necessary for which three extra nibbles would be required,
making the instruction length as ve nibbles. The return instruction would be of two nibbles only. Fol-
lowing branching instructions are offered:
1. Jump if carry is set (one instruction) would branch to the indicated address if carry ag of active
ag register is set. This would need ve nibbles, with last three nibbles having direct address for
branching.
2. Jump if zero (one instruction) would check the Z ag condition before branching. Therefore
operations with other registers also may derive adequate branching condition. Five nibble
opcode with direct address at last 3 nibbles.
3. Jump unconditional (one instruction) with 5-nibble opcode. Branch address in last 3-nibbles.
4. Unconditional call (one instruction) with 5-nibble opcode. Branch address in last 3-nibbles.
5. Unconditional return (one instruction) with 2-nibble opcode.
Mnemonics of all 32 instructions are presented with their brief descriptions and number of variations
within parenthesis. Number of nibbles, cycles, syntax example and opcodes are provided after that.
Data Move and Load Instructions
MIR Move immediate to register (eight instructions)
Description: The indicated register would be loaded with immediate data of 4-bit. No ags are affected.
These are 3-nibble instructions with the third nibble containing immediate data.
Syntax: MIR U, data(4)
Nibbles: 3 Cycles: 3 Flags: none
3210
1110
3210
0rr r
3210
dddd
M06_GHOS1557_01_SE_C06.indd 187M06_GHOS1557_01_SE_C06.indd 187 4/29/11 5:09 PM4/29/11 5:09 PM
188 Computer Architecture and Organization
MAM Move accumulator to memory (one instruction)
Description: Copy content of accumulator (4-bit) to memory location indicated by direct addressing
mode. No ags are affected.
Syntax: MAM addr(4)
Nibbles: 3 Cycles: 4 Flags: none
3210
1110
3210
1001
3210
aaaa
MMA Move memory to accumulator (one instruction)
Description: Copy content of directly addressed memory location to accumulator. No ags are affected.
Syntax: MMA addr(4)
Nibbles: 3 Cycles: 4 Flags: none
3210
1110
3210
1010
3210
aaaa
CRR Copy from register to register (56 instructions)
Description: Content of a 4-bit source register copied to another 4-bit destination register using register
direct addressing mode. No ags are affected.
Syntax: CRR U, W
Nibbles: 2 Cycles: 2 Flags: none
3210
00ss
3210
srrr
PUSH Push register on stack top (eight instructions)
Description: Content of indicated register (4-bit) is placed on stack top. SP is then incremented by one.
No ags are affected.
Syntax: PUSH F
Nibbles: 2 Cycles: 3 Flags: none
3210
0100
3210
0rr r
POP Pop register from stack top (eight instructions)
Description: The stack pointer is decremented by one and then the content of the stack top is copied to
the indicated register. No ags are affected except in case of popping to Flag register (F).
Syntax: POP V
Nibbles: 2 Cycles: 3 Flags: none (except POP F)
3210
0100
3210
1rr r
RPA Read from port address to accumulator (one instruction)
Description: Content of the addressed port is copied to accumulator. No ags are affected.
Syntax: RPA addr(4)
M06_GHOS1557_01_SE_C06.indd 188M06_GHOS1557_01_SE_C06.indd 188 4/29/11 5:10 PM4/29/11 5:10 PM
..................Content has been hidden....................
You can't read the all page of ebook, please click here login for view all page.