234 Computer Architecture and Organization
To optimize between cost and speed, a smaller part of SRAM is accommodated within primary
memory, designated as cache memory. Depending upon its location, cache is designated as L1 cache,
L2 cache or L3 cache. L1 cache is placed within the same wafer with the processor. L2 cache is accom-
modated within the same package of the processor but not within the same wafer. L3 cache is placed
in between main memory composed of DRAM and the processor. Cache memory is used to store only
instructions and data frequently used by the processor. Therefore, cache contains only a smaller por-
tion of main memory and it may be mapped using any one of three mapping techniques, namely direct
mapping, set associative mapping and fully associative mapping. In general, it is achieved through the
cache directory by the cache controller. In earlier processors from Intel, there was no provision of cache
memory, which was initialized from Intel 80486 microprocessor.
The size of main memory of any computer is limited by the number of address lines available from
that processor. Moreover, not all available area of this space are always occupied by memory devices.
Using the techniques like overlays and swapping, even a program larger than the size of main memory
may be executed by the processor. Virtual memory is another technique, which allows the software
developer to think of the available main memory as a larger contiguous space, which may not be in real-
ity. In this case, paging plays a critical role and only those pages that need their presence within the main
memory for execution are accommodated within main memory by the memory manager.
DMA is a method of direct communication of data between main memory and some other peripheral
devices like a disc controller or a port. During DMA operation, instead of CPU, the DMA control-
ler takes the control of system bus and generates necessary address and control signals. Data sets are
directly communicated between memory and peripheral device synchronizing these address and control
signals. The processor regains the control of the system bus after completion of DMA operation.
Intel 80386 was the rst processor from Intel to offer cache memory, although external in nature. The
32-bit logical address of 80386 is broken in three parts to get the access of physical memory through
three steps. The base address of page directory available in register CR3 is added with most signi cant
ten bits of the logical address to generate the entry point at the directory table. The directory table gives
a page table address, which is added with middle 10 bits of the logical address to get the base address of
the relevant page of the main memory. The least signi cant 12 bits of the logical address is now used to
get the accurate entry point (physical address) of the targeted page. The processor also offers adequate
protection features to implement multi-tasking environment.
Memory management features of Pentium 4 are more or less identical with that of 80386, with the excep-
tion of the page size, which is 4 kB for 80386 and 4 MB for Pentium 4. Furthermore, Pentium 4 offers ade-
quate data types for easier handling of information and faster processing of MMX technology instructions.
POINTS TO REMEMBER
R EEPROMs may be erased byte-wise but FLASH is erased as a whole.
R No processor can execute any program directly from disc, unless it is copied to main memory.
R SRAM is much faster than DRAM but more expensive.
R The read/write head for hard disc drive does not touch the magnetic surface during operation, unlike
oppy disc read/write head.
R Virtual memory creates an illusion of existence of very large and contiguous memory space to the
software developer.
R During DMA operation DMA controller outputs address and control signals only.
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