The Memory System 235
Information in data sheets of processors from all
manufacturers indicate that during DMA the pro-
cessor carries on its own internal activities. In this
case, we have to read between the lines to under-
stand the reality. If the processor is without any
L1 or L2 cache (like 8086 or 80386), then for all
practical purposes no productive internal activity
of the processor is possible
This is because of the fact that, for any type
of productive activity, the processor must fetch
instructions from external memory, which cannot
be performed during the on-going DMA operation.
However, in modern processors, we nd L1 and
L2 caches within the processor. Does it mean
that the DMA operation and the processor opera-
tion would go on concurrently in these cases?
The answer is yes and no. If the execution of any
instruction demands an operand that is not avail-
able within data cache (cache miss), then further
operations of the processor must be terminated as
the main memory can not be accessed due to ongo-
ing DMA operation. The situation would remain
identical if the instruction cache is unable to sup-
ply the next executable instruction. Therefore, the
DMA operation may or may not allow the uninter-
rupted operation of the concerned processor.
REVIEW QUESTIONS
Target the Correct Option
1. The EPROMs may be distinguished from
other ICs by the
(a) circular window at the top of its package
(b) number of its pins
(c) shape of its package
(d) none of these
2. L3 cache, if any, of computers is composed of
(a) DRAM (c) either of these
(b) SRAM (d) none of these
3. Primary memory is that memory which may
be located within the
(a) processor (c) computer
(b) motherboard (d) none of these
4. The ‘instruction cache’ is a part of
(a) uni ed cache (c) L3 cache
(b) split cache (d) none of these
5. Which one of the following Intel processors
offer L3 cache?
(a) 80486 (c) Itanium
(b) Pentium 4 (d) none of these
6. TAG-RAM is available within
(a) cache directory (c) processor
(b) cache memory (d) none of these
7. In hard discs, for the purpose of storage, each
side of a platter is subdivided into several
(a) pages and lines (c) tracks and sectors
(b) bits and bytes (d) none of these
8. In optical discs, logic levels 1 and 0 are rep-
resented by
(a) lands and pits (c) dark and light
(b) tracks and sectors (d) none of these
9. The DMA procedure is initiated by
(a) peripheral device (c) processor
(b) DMA controller (d) none of these
10. During DMA operation, the DMA controller
outputs
(a) address, data and control signals
(b) address and data signals
(c) address and control signals
(d) none of these
QUICKSAND CORNER
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236 Computer Architecture and Organization
1. Due to the improvement of technology, modern
processors can work faster. Then why not this
technological improvement is re ected in mod-
ern memory devices, which are still very slow
as compared with the speed of the processors?
2. What is meant by ‘locality of reference’ and
what is its relation with cache memory?
3. What is the advantage of offering cache at dif-
ferent levels?
4. Why the main memory is divided into pages,
sets and lines for implementation of cache?
5. What are the advantages and disadvantages
between LRU and LFU replacement algorithms?
6. What is the difference between a hard disc
and a oppy disc as far as their read/write
heads are concerned?
7. How data is written within optical discs and
how is it read?
8. Why 3-state bus buffers are essential for
DMA implementation?
9. Why the address bus is bi-directional in DMA
controllers?
10. Is it possible to suddenly terminate the on
going DMA operation before the completion
of all data transfer? Justify your answer.
Take Some Time Here
Find in Few Seconds
1. What is the difference between
(i) a ROM and a PROM,
(ii) an EPROM and EEPROM
(iii) FLASH and EEPROM?
2. Identify usage of these types of memory
devices by marking a tick either in second or
in third column of the following table.
Type Primary Secondary
Optical disc
CPU registers
L2 cache
Floppy disc
L3 cache
Main memory
Magnetic tapes
Hard disc
L1 cache
3. What is meant by ‘access time’ and how does
it vary?
4. What are the differences between L1 cache,
L2 cache and L3 cache?
5. What is the difference between ‘uni ed cache’
and ‘split cache’? Give examples.
6. What is meant by ‘mapping’? In how many
ways mapping may be implemented? What is
the role of cache directory in mapping?
7. What is the difference between set-associative
mapping and fully-associative mapping? Can
we implement 3-way set associative cache?
8. How virtual memory can offer more memory
than it is really present in the system to the
software developer?
9. Why a DMA controller has bidirectional
address bus?
10. What is the correlation between HOLD input
and HLDA output of 8085 microprocessor?
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