B

MIPS Instructions

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This appendix summarizes MIPS instructions used in this book. Tables B.1–B.3 define the opcode and funct fields for each instruction, along with a short description of what the instruction does. The following notations are used:

ent [reg]:   contents of the register

ent imm:    16-bit immediate field of the I-type instruction

ent addr:   26-bit address field of the J-type instruction

ent SignImm:  32-bit sign-extended immediate
       = {{16{imm[15]}}, imm}

ent ZeroImm:  32-bit zero-extended immediate
       = {16’b0, imm}

ent  Address:  [rs] + SignImm

ent [Address]: contents of memory location Address

ent BTA:    branch target address1
       = PC + 4 + (SignImm << 2)

ent JTA:    jump target address
       = {(PC + 4)[31:28], addr, 2’b0}

ent label:   text indicating an instruction location

Table B.1 Instructions, sorted by opcode

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Table B.2 R-type instructions, sorted by funct field

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Table B.3 F-type instructions (fop = 16/17)

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1 The BTA in the SPIM simulator is PC + (SignImm << 2) because it has no branch delay slot. Thus, if you use the SPIM assembler to create machine code for a real MIPS processor, you must decrement the immediate field of each branch instruction by 1 to compensate.

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