Digital Electronics
Before we begin, I’ll warn you that there is a lot of information in this chapter, and it may be difficult to absorb all this at once. Some information is present largely for historical interest and to provide a better understanding of how complex digital systems such as microcontrollers work. My advice is to skim to your heart’s content, and pull out whatever information you find practical. The basic principles are still the same, but if you find that your design uses more than three ICs, you probably could be using a microcontroller (the subject of Chapter 13).
12.1 The Basics of Digital Electronics
Until now, we have mainly covered the analog realm of electronics—circuits that accept and respond to voltages that vary continuously over a given range. Such analog circuits included rectifiers, filters, amplifiers, simple RC timers, oscillators, simple transistor switches, and so on. Although each of these analog circuits is fundamentally important in its own right, these circuits lack an important feature: they cannot store and process bits of information needed to make complex logical decisions. To incorporate logical decision-making processes into a circuit, you need to use digital electronics.
FIGURE 12.1
12.1.1 Digital Logic States
In digital electronics, there are only two voltage states present at any point within a circuit. These voltage states are either high or low. The voltage being high or low at a particular location within a circuit can signify a number of things. For example, it may represent the on or off state of a switch or saturated transistor, one bit of a number, whether an event has occurred, or whether some action should be taken.
The high and low states can be represented as true and false statements, which are used in Boolean logic. In most cases, high equals true and low equals false. However, this does not need to be the case—you could make high equal to false and low equal to true. The decision to use one convention over the other is a matter left ultimately to the designer. In digital lingo, to avoid people getting confused over which convention is in use, the term positive true logic is used when high equals true, while the term negative true logic is used when high equals false.
In Boolean logic, the symbols 1 and 0 are used to represent true and false, respectively. Now, unfortunately, 1 and 0 are also used in electronics to represent high and low voltage states, where high equals 1 and low equals 0. As you can see, things can get a bit confusing, especially if you are not sure which type of logic convention is being used: positive true or negative true logic. In Section 12.3, you will see some examples that deal with this confusing issue.
The exact voltages assigned to high or low voltage states depend on the specific logic IC that is used (as it turns out, digital components are IC-based). As a general rule of thumb, +5 V is considered high, while 0 V (ground) is considered low. However, as you will see in Section 12.4, this does not need to be the case. For example, some logic ICs may interpret a voltage from +2.4 to +5 V as high and a voltage from +0.8 to 0 V as low. Other ICs may use an entirely different range.
12.1.2 Number Codes Used in Digital Electronics
Binary
Because digital circuits work with only two voltage states, it is logical to use the binary number system to keep track of information. A binary number is composed of two binary digits, 0 and 1, which are also called bits (for example, 0 = low voltage and 1 = high voltage). By contrast, a decimal number such as 736 is represented by successive powers of 10:
73610 = 7 × 102 + 3 × 101 + 6 × 100
Similarly, a binary number such as 11100 (2810) can be expressed as successive powers of 2:
111002 = 1 × 24 + 1 × 23 + 1 × 22 + 0 × 21 + 0 × 20
The subscript tells which number system is in use (X10 = decimal number and X2 = binary number). The highest-order bit (leftmost bit) is called the most significant bit (MSB), while the lowest-order bit (rightmost bit) is called the least significant bit (LSB). Methods used to convert from decimal to binary and vice versa are shown in Fig. 12.2.
FIGURE 12.2
It should be noted that most digital systems deal with 4, 8, 16, or 32 bits at a time. The decimal-to-binary conversion example given here has a 7-bit answer. In an 8-bit system, you would need to put an additional 0 in front of the MSB (for example, 01101101). In a 16-bit system, nine additional 0s would need to be added (for example, 0000000001101101).
As a practical note, the easiest way to convert a number from one base to another is to use a calculator. For example, to convert a decimal number into a binary number, type in the decimal number (in base 10 mode) and then change to binary mode (which usually entails a second function key). The number will now be in binary (1s and 0s). To convert a binary number to a decimal number, start out in binary mode, type in the number, and then switch to decimal mode.
Octal and Hexadecimal
Two other number systems used in digital electronics include the octal and hexadecimal systems. In the octal system (base 8), there are 8 allowable digits: 0, 1, 2, 3, 4, 5, 6, and 7. In the hexadecimal system (base 16), there are 16 allowable digits: 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, A, B, C, D, E, and F. Here are examples of octal and hexadecimal numbers with decimal equivalents:
2478 (octal) = 2 × 82 + 4 × 81 + 7 × 80 = 16710 (decimal)
2D516 (hex) = 2 × 162 + D (=1310) × 161 + 9 × 160 = 72510 (decimal)
Of course, binary numbers are the natural choice for digital systems, but since these binary numbers can become long and difficult to interpret by our decimal-based brains (a result of our ten fingers), it is common to write them out in hexadecimal or octal form.
Unlike decimal numbers, octal and hexadecimal numbers can be translated easily to and from binary. This is because a binary number, no matter how long, can be broken up into 3-bit groupings (for octal) or 4-bit groupings (for hexadecimal). You simply add zero to the beginning of the binary number if the total numbers of bits is not divisible by 3 or 4. Figure 12.3 should paint the picture better than words.
FIGURE 12.3
Today, the hexadecimal system has essentially replaced the octal system. The octal system was popular at one time, when microprocessor systems used 12-bit and 36-bit words, along with a 6-bit alphanumeric code, which are all divisible by 3-bit units (1 octal digit). Today, microprocessor systems mainly work with 8-bit, 16-bit, 20-bit, 32-bit, or 64-bit words, which are all divisible by 4-bit units (1 hex digit). In other words, an 8-bit word can be broken down into 2 hex digits, a 16-bit word into 4 hex digits, a 20-bit word into 5 hex digits, and so on.
Hexadecimal representation of binary numbers pops up in many memory and microprocessor applications that use programming codes (for example, within assembly language) to address memory locations and initiate other specialized tasks that would otherwise require typing in long binary numbers. For example, a 20-bit address code used to identify one of a million memory locations can be replaced with a hexadecimal code (in the assembly program) that reduces the count to five hex digits. Note that a compiler program later converts the hex numbers within the assembly language program into binary numbers (machine code), which the microprocessor can use. Table 12.1 shows a conversion table.
TABLE 12.1 Decimal, Binary, Octal, Hex, BCD Conversion Table
Binary-coded decimal (BCD) is used to represent each digit of a decimal number as a 4-bit binary number. For example, the number 15010 in BCD is expressed as follows:
To convert from BCD to binary is vastly more difficult, as shown in Fig. 12.4. Of course, you could cheat by converting the BCD into decimal first and then convert to binary, but that does not show you the mechanics of how machines do things with 1s and 0s. You will rarely need to do BCD-to-binary conversion, so I will not dwell on this topic.
FIGURE 12.4
BCD is commonly used when outputting to decimal (0–9) displays, such as those found in digital clocks and multimeters. BCD will be discussed in Section 12.3.
Sign-Magnitude and 2’s Complement Numbers
Up to now, we have not considered negative binary numbers. How do you represent them? A simple method is to use sign-magnitude representation. In this method, you simply reserve a bit, usually the MSB, to act as a sign bit. If the sign bit is 0, the number is positive; if the sign bit is 1, the number is negative (see Fig. 12.5).
FIGURE 12.5
Although the sign-magnitude representation is simple, it is seldom used, because adding requires a different procedure than subtracting (as you will see in the next section). Occasionally, you will see sign-magnitude numbers used in display and analog-to-digital applications, but you will hardly ever see them in circuits that perform arithmetic.
A more popular choice when dealing with negative numbers is to use 2’s complement representation. In 2’s complement, the positive numbers are exactly the same as unsigned binary numbers. A negative number, however, is represented by a binary number, which when added to its corresponding positive equivalent results in zero. In this way, you can avoid two separate procedures for doing addition and subtraction. You will see how this works in the next section. A simple procedure outlining how to convert a decimal number into a binary number and then into a 2’s complement number, and vice versa, is outlined in Fig. 12.5.
Decimal, Sign-Magnitude, 2’s Complement Conversion Table
Arithmetic with Binary Numbers
Adding, subtracting, multiplying, and dividing binary numbers, hexadecimal numbers, and other representations can be done with a calculator set to that particular base mode. But that’s cheating, and it doesn’t help you understand the mechanics of how it is done. The mechanics become important when designing the actual arithmetical circuits. Here are the basic techniques used to add and subtract binary numbers.
Adding binary numbers is just like adding decimal numbers. Whenever the result of adding one column of numbers is greater than one digit, a 1 is carried over to the next column to be added.
FIGURE 12.6
Subtracting binary numbers is not as easy as it looks. It is similar to decimal subtraction but can be confusing. For example, you might think that if you were to subtract a 1 from a 0, you would borrow a 1 from the column to the left. No! You must borrow a 10 (210). It becomes a headache if you try to do this by hand. The trick to subtracting binary numbers is to use the 2’s complement representation that provides the sign bit, and then just add the positive number with the negative number to get the sum. This method is often used by digital circuits because it allows both addition and subtraction, without the headache of needing to subtract the smaller number from the larger number.
FIGURE 12.7
American Standard Code for Information Interchange (ASCII) is an alphanumeric code used to transmit letters, symbols, numbers, and special nonprinting characters between computers and computer peripherals (such as printers and keyboards). ASCII consists of 128 different 7-bit codes.
Codes from 000 0000 (or hex 00) to 001 1111 (or hex 1F) are reserved for nonprinting characters or special machine commands like ESC (escape), DEL (delete), CR (carriage return), and LF (line feed). Codes from 010 0000 (or hex 20) to 111 1111 (or hex 7F) are reserved for printing characters like a, A, #, &, {, @, and 3. Tables 12.2 and 12.3 show the ASCII nonprinting and printing characters.
In practice, when ASCII code is sent, an additional bit is added to make it compatible with 8-bit systems. This bit may be set to 0 and ignored, it may be used as a parity bit for error detection (Section 12.3.8 covers parity bits), or it may act as a special function bit used to implement an additional set of specialized characters.
TABLE 12.2 ASCII Nonprinting Characters
Before moving on to the next section, let’s take a brief look at three important items: clock timing, parallel transmission, and serial transmission.
Most digital circuits require precise timing to function properly. Usually, a clock circuit that generates a series of high and low pulses at a fixed frequency is used as a reference on which to base all critical actions executed within a system. The clock is also used to push bits of data through the digital circuitry. The period of a clock pulse is related to its frequency by T = 1/f. So, if T = 10 ns, then f = 1/(10 ns) = 100 MHz.
FIGURE 12.8
Serial Versus Parallel Representation
Binary information can be transmitted from one location to another in either a serial or parallel manner. The serial format uses a single electrical conductor (and a common ground) for data transfer. Each bit from the binary number occupies a separate clock period, with the change from one bit to another occurring at each falling or leading clock edge; the type of edge depends on the circuitry used.
Figure 12.9 shows an 8-bit (10110010) word that is transmitted from circuit A to circuit B in 8 clock pulses (0–7). In computer systems, serial communications are used to transfer data between keyboard and computer, as well as to transfer data between two computers via a telephone line.
FIGURE 12.9
Parallel transmission uses separate electrical conductors for each bit (and a common ground). In Fig. 12.9, an 8-bit string (01110110) is sent from circuit A to circuit B. As you can see, unlike serial transmission, the entire word is transmitted in only one clock cycle, not eight clock cycles. In other words, it is eight times faster. Parallel communications are most frequently found within microprocessor systems that use multiline data and control buses to transmit data and control instructions from the microprocessor to other microprocessor-based devices (such as memory and output registers).
Logic gates are the building blocks of digital electronics. The fundamental logic gates include the INVERT (NOT), AND, NAND, OR, NOR, exclusive OR (XOR), and exclusive NOR (XNOR) gates. Each of these gates performs a different logical operation. Figure 12.10 provides a description of what each logic gate does and gives a switch and transistor analogy for each gate.
FIGURE 12.10
AND, NAND, OR, and NOR gates often come with more than two inputs (this is not the case with XOR and XNOR gates, which require two inputs only). Figure 12.11 shows a four-input AND, an eight-input AND, a three-input OR, and an eight-input OR gate. With the eight-input AND gate, all inputs must be high for the output to be high. With the eight-input OR gate, at least one of the inputs must be high for the output to go high.
FIGURE 12.11
12.2.2 Digital Logic Gate ICs
The construction of digital gates is best left to the IC manufacturers. In fact, making gates from discrete components is highly impractical in regard to both overall performance (power consumption, speed, drive capacity, and so on) and overall cost and size.
As we mentioned in the introduction to this chapter, the use of individual logic ICs has almost completely been superseded by the use of microcontrollers. However, one or two logic ICs are still often used together in simple applications.
There are a number of technologies used in the fabrication of digital logic. The two most popular technologies include transistor-transistor logic (TTL) and complementary MOSFET (CMOS) logic. TTL incorporates bipolar transistors into its design, while CMOS incorporates MOSFET transistors. Both technologies perform the same basic functions, but certain characteristics (such as power consumption, speed, and output drive capacity) differ. There are many subfamilies within both TTL and CMOS. These subfamilies, as well as the various characteristics associated with each subfamily, will be discussed in greater detail in Section 12.4.
A logic IC, be it TTL or CMOS, typically houses more than one logic gate (for example, a quad two-input NAND, hex inverter, and so on). Each of the gates within the IC shares a common supply voltage that is implemented via two supply pins: a positive supply pin (+VCC or +VDD) and a ground pin (GND). The vast majority of TTL and CMOS ICs are designed to run off a +5-V supply. (This does not apply for all the logic families, but I will get to that in Section 12.4.)
Generally speaking, input and output voltage levels are assumed to be 0 V (low) and +5 V (high). However, the actual input voltage required and the actual output voltage provided by the gate are not set in stone. For example, the 74xx TTL series will recognize a high input from 2.0 to 5 V and a low from 0 to 0.8 V, and will guarantee a high output from 2.4 to 5 V and a low output from 0 to 0.4 V. However, for the CMOS 4000B series (VCC = +5 V), recognizable input voltages range from 3.3 to 5 V for high and 0 to 1.7 V for low. Guaranteed high and low output levels range from 4.9 to 5 V and 0 to 0.1 V, respectively. Again, I will discuss specifics later in Section 12.4. For now, let’s just get acquainted with what some of these ICs look like, as shown in Figs. 12.12 and 12.13. The CMOS devices listed in the figures include 74HCxx and 4000(B). The TTL devices shown include the 74xx, 74Fxx, and 74LS.
FIGURE 12.12
FIGURE 12.13
12.2.3 Applications for a Single Logic Gate
Before we jump into the heart of logic gate applications that involve combining logic gates to form complex decision-making circuits, let’s take a look at a few simple applications that require the use of a single logic gate.
An enable/disable gate is a logic gate that acts to control the passage of a given waveform. The waveform—say, a clock signal—is applied to one of the gate’s inputs, while the other input acts as the enable/disable control lead. Enable/disable gates are used frequently in digital systems to enable and disable control information from reaching various devices. Figure 12.14 shows two enable/disable circuits: the first uses an AND gate, and the second uses an OR gate. NAND and NOR gates are also frequently used as enable gates.
In the upper part of the figure, an AND gate acts as the enable gate. When the input enable lead is made high, the clock signal will pass to the output. In this example, the input enable is held high for 4 μs, allowing 4 clock pulses (where Tclk = 1 μs) to pass. When the input enable lead is low, the gate is disabled, and no clock pulses make it through to the output.
Below, an OR gate is used as the enable gate. The output is held high when the input enable lead is high, even as the clock signal is varying. However, when the enable input is low, the clock pulses are passed to the output.
FIGURE 12.14
Waveform Generation
By using the basic enable/disable function of a logic gate, as illustrated in the previous example, it is possible, with the help of a repetitive waveform generator circuit, to create specialized waveforms that can be used for the digital control of sequencing circuits.
An example waveform generator circuit is the Johnson counter. The Johnson counter will be discussed in Section 12.8. For now, let’s simply focus on the outputs. In Fig. 12.15, a Johnson counter uses clock pulses to generate different output waveforms, as shown in the timing diagram. Outputs A, B, C, and D go high for 4 μs (four clock periods) and are offset from each other by 1 μs. Outputs 
, 
, 
, and 
produce waveforms that are complements of outputs A, B, C, and D, respectively.
, , , and produce waveforms that are complements of outputs A, B, C, and D, respectively.
FIGURE 12.15
Now, there may be certain applications that require 4-μs high/low pulses applied at a given time, as the counter provides. However, what would you do if the application requires a 3-μs high waveform that begins at 2 μs and ends at 5 μs (relative to the time scale indicated in Fig. 12.15)? This is where the logic gates come in handy. For example, if you attach an AND gate’s inputs to the counter’s A and B outputs, you will get the desired 2- to 5-μs high waveform at the AND gate’s output: from 1 to 2 μs the AND gate outputs a low (A = 1, B = 0), from 2 to 5 μs the AND gate outputs a high (A = 1, B = 1), and from 5 to 6 μs the AND gate outputs a low (A = 0, B = 1). See the leftmost area of Fig. 12.16.
FIGURE 12.16
Various other specialized waveforms can be generated by using different logic gates and tapping different outputs of the Johnson shift counter. In Fig. 12.16, six other possibilities are shown.
12.2.4 Combinational Logic
Combinational logic involves combining logic gates together to form circuits capable of enacting more useful, complex functions. For example, let’s design the logic used to instruct a janitor-type robot to recharge itself (seek out a power outlet) only when a specific set of conditions is met. The “recharge itself” condition is specified as follows:
• When its battery is low (indicated by a high output signal from a battery-monitor circuit)
• When the workday is over (indicated by a high output signal from a timer circuit)
• When vacuuming is complete (indicated by a high voltage output from a vacuum-completion monitor circuit)
• When waxing is complete (indicated by a high output signal from a wax-completion monitor circuit).
Let’s also assume that the power-outlet-seeking routine circuit is activated when a high is applied to its input.
Two simple combinational circuits that perform the desired logic function for the robot are shown in Fig. 12.17. The two circuits use a different number of gates but perform the same function. Now, the question remains, how did we come up with these circuits? In either circuit, it is not hard to predict which gates are needed. You simply exchange the word and present within the conditional statement with an AND gate within the logic circuit, and exchange the word or present within the conditional statement with an OR gate within the logic circuit. Common sense takes care of the rest.
FIGURE 12.17
However, when you begin designing more complex circuits, using intuition to figure out what kind of logic gates to use and how to join them together becomes exceedingly difficult. To make designing combinational circuits easier, a special symbolic language called Boolean algebra is used, which uses only true and false variables. A Boolean expression for the robot circuit would appear as follows:
E = (B + T) + VW
This expression amounts to saying that if B (battery-check circuit’s output) or T (timer circuit’s output) is true, or V and W (vacuum and waxing circuit outputs) are true, then E (enact power-outlet circuit input) is true.
Note that the word or is replaced by the symbol +, and the word and is simply expressed in a way similar to multiplying two variables together (placing them side by side or using a dot between variables). Also note that the term true in Boolean algebra is expressed as a 1, and false is expressed as a 0. Here, we are assuming positive logic, where true equals high voltage. Using the Boolean expression for the robot circuit, we can come up with some of the following results (the truth table in Fig. 12.17 provides all possible results):
E = (B + T) + VW |
|
E = (1 + 1) + (1 · 1) = 1 + 1 = 1 |
(battery is low, time to sleep, finished with chores = go recharge) |
E = (1 + 0) + (0 · 0) = 1 + 0 = 1 |
(battery is low = go recharge) |
E = (0 + 0) + (1 · 0) = 0 + 0 = 0 |
(hasn’t finished waxing = don’t recharge yet) |
E = (0 + 0) + (1 · 1) = 0 + 1 = 1 |
(has finished all chores = go recharge) |
E = (0 + 0) + (0 · 0) = 0 + 0 = 0 |
(hasn’t finished vacuuming and waxing = don’t recharge yet) |
The robot example showed you how to express AND and OR functions in Boolean algebraic terms. But what about the negation operations (NOT, NAND, and NOR) and the exclusive operations (XOR and XNOR)? How do you express these in Boolean terms?
• For a NOT condition, place a line over the NOT’ed variable or variables.
• For a NAND expression, place a line over an AND expression.
• For a NOR expression, place a line over an OR expression.
• For exclusive operations, use the symbol ⊕.
Figure 12.18 shows a rundown of all the possible Boolean expressions for the various logic gates.
FIGURE 12.18
Like conventional algebra, Boolean algebra has a set of logic identities that can be used to simplify the Boolean expressions and thus make circuits more compact. These identities go by names such as the commutative law of addition, associate law of addition, and distributive law. Instead of worrying about what the various identities are called, simply make reference to the list of identities provided on the next page. Most of these identities are self-explanatory, although a few are not so obvious, as you will see in a minute. The various circuits in Fig. 12.19 show some of the identities in action.
FIGURE 12.19
Let’s find the initial Boolean expression for the circuit in Fig. 12.20, and then use the logic identities to come up with a circuit that requires fewer gates.
The circuit shown here is expressed by the following Boolean expression:
out = (A + B)
+ + BC
+ + BCThis expression can be simplified by using Identity 5:
(A + B) = A + B
= A + BThis makes:
out = A + B + = BC
+ B + = BCUsing Identities 17 (B = 0) and ( + 0 = ), you get:
= 0) and ( + 0 = ), you get:out = A + 0 + + BC = A + BC +
+ 0 + + BC = A + BC + Factoring a from the preceding term gives:
from the preceding term gives:out = (A + 1) + BC
(A + 1) + BCUsing Identity 10, you get:
out = (1) + BC = + BC
(1) + BC = + BCFinally, using Identity 21, you get the simplified expression:
out = + C
+ CNotice that A is now missing. This means that the logic input at A has no effect on the output and therefore can be omitted. From the reduction, you get the simplified circuit in the bottom part of the figure.
FIGURE 12.20
Now let’s take a look at a couple of not-so-obvious logic identities: those that involve the XOR (Identity 22) and XNOR (Identity 23) gates. The leftmost section in Fig. 12.21 shows equivalent circuits for the XOR gate. In the lower two equivalent circuits, Identity 22 is proved by Boolean reduction. Equivalent circuits for the XNOR gate are shown in the rightmost section of the figure. To prove Identity 23, you can simply invert Identity 22.
FIGURE 12.21
De Morgan’s Theorem (Identities 18 and 19)
To simplify circuits containing NANDs and NORs, you can use an incredibly useful theorem known as De Morgan’s theorem. This theorem allows you to convert an expression having an inversion bar over two or more variables into an expression having inversion bars over single variables only. De Morgan’s theorem (Identities 18 and 19) is as follows:
The easiest way to prove that these identities are correct is to use Fig. 12.22, noting that the truth tables for the equivalent circuits are the same. Note the inversion bubbles present on the inputs of the corresponding leftmost gates. The inversion bubbles mean that before inputs A and B are applied to the base gate, they are inverted (negated). In other words, the bubbles are simplified expressions for NOT gates.
FIGURE 12.22
Why do you use the inverted-input OR gate symbol instead of a NAND gate symbol? Or why would you use the inverted-input AND gate symbol instead of a NOR gate symbol? This is left up to the designer to choose whatever symbol seems most logical to use. For example, when designing a circuit, it may be easier to think about ORing or ANDing inverted inputs than to think about NANDing or NORing inputs. Similarly, it may be easier to create truth tables or work with Boolean expressions using the inverted-input gate. It is typically easier to create truth tables and Boolean expressions that do not have variables joined under a common inversion bar. Of course, when it comes time to construct the actual working circuit, you probably will want to convert to the NAND and NOR gates because they do not require additional NOT gates at their inputs.
Bubble Pushing
A shortcut method for forming equivalent logic circuits, based on De Morgan’s theorem, is to use what’s called bubble pushing.
Bubble pushing involves the following tricks:
• Change an AND gate to an OR gate or change an OR gate to an AND gate.
• Add inversion bubbles to the inputs and outputs where there were none, while removing the original bubbles.
That’s it. You can prove to yourself that this works by examining the corresponding truth tables for the original gate and the bubble-pushed gate, or you can work out the Boolean expressions using De Morgan’s theorem. Figure 12.23 shows examples of bubble pushing.
FIGURE 12.23
Universal Capability of NAND and NOR Gates
NAND and NOR gates are referred to as universal gates because each alone can be combined together with itself to form all other possible logic gates. The ability to create any logic gate from NAND or NOR gates is obviously a handy feature. For example, if you do not have an XOR IC handy, you can use a single multigate NAND gate (such as 74HC00) instead. Figure 12.24 shows how to wire NAND or NOR gates together to create equivalent circuits of the various logic gates.
FIGURE 12.24
AND-OR-INVERTER Gates
When a Boolean expression is reduced, the equation that is left over typically will be of one of the following two forms: product of sums (POS) or sum of products (SOP). A POS expression appears as two or more OR'ed variables AND'ed together with two or more additional OR'ed variables. An SOP expression appears as two or more AND'ed variables OR'ed together with additional AND'ed variables. Figure 12.25 shows two circuits that provide the same logic function (they are equivalent), but the circuit to the left is designed to yield a POS expression, while the circuit to the right is designed to yield a SOP expression.
FIGURE 12.25
Which circuit is best for design: the one that implements the POS expression or the one that implements the SOP expression? The POS design shown here would appear to be the better choice because it requires fewer gates. However, the SOP design is nice because it is easy to work with the Boolean expression. For example, which Boolean expression in Fig. 12.25 (POS or SOP) would you rather use to create a truth table? The SOP expression seems the obvious choice.
A more down-to-earth reason for using an SOP design has to do with the fact that special ICs called AND-OR-INVERTER (AOI) gates are designed to handle SOP expressions. For example, the 74LS54 AOI IC shown in Fig. 12.26 creates an inverted SOP expression at its output, via two two-input AND gates and two three-input AND gates NOR'ed together. A NOT gate can be attached to the output to get rid of the inversion bar, if desired. If specific inputs are not used, they should be held high, as shown in the example circuit in Fig. 12.26. AOI ICs come in many different configurations—check out the catalogs to see what’s available.
FIGURE 12.26
12.2.5 Keeping Circuits Simple (Karnaugh Maps)
We have just covered how using the logic identities can simplify a Boolean expression. This is important because it reduces the number of gates needed to construct the logic circuit. However, as I am sure you will agree, having to work out Boolean problems in longhand is not easy. It takes time and ingenuity. A simple way to avoid the unpleasant task of using your ingenuity is to get a computer program that accepts a truth table or Boolean expression, and then provides you with the simplest expression, and perhaps even the circuit schematic.
However, let’s assume that you do not have such a program to help you out. Are you stuck with the Boolean longhand approach? No. You can use a technique referred to as Karnaugh mapping. With this technique, you take a given truth table (or Boolean expression that can be converted into a truth table), convert it into a Karnaugh map, apply some simple graphic rules, and come up with the simplest (most of the time) possible Boolean expression for your final circuit. Karnaugh mapping works best for circuits with three to four inputs—below this, things usually do not require much thought anyway; beyond four inputs, things get quite tricky.
Here’s a basic outline showing how to apply Karnaugh mapping to a three-input system:
1. Select a desired truth table. Let’s choose the one shown in Fig. 12.27. (If you have only a Boolean expression, transform it into an SOP expression and use the SOP expression to create the truth table; refer to Fig. 12.26 to figure out how this is done.)
FIGURE 12.27
2. Translate the truth table into a Karnaugh map. A Karnaugh map is similar to a truth table but has its variables represented along two axes. Translating the truth table into a Karnaugh map reduces the number of 1s and 0s needed to present the information. Figure 12.27 shows how the translation is carried out.
3. After you create the Karnaugh map, proceed to encircle adjacent cells of 1s into groups of 2, 4, or 8. The more groups you can encircle, the simpler the final equation will be. In other words, take all possible loops.
4. Identify the variables that remain constant within each loop, and write out an SOP equation by OR'ing these variables together. Here, constant means that a variable and its inverse are not present together within the loop. For example, the top horizontal loop in Fig. 12.27 yields 
(the first term in the SOP expression), since ’s and ’s inverses (A and B) are not present. However, the C variable is omitted from this term because C and are both present.
(the first term in the SOP expression), since ’s and ’s inverses (A and B) are not present. However, the C variable is omitted from this term because C and are both present.5. The SOP expression you end up with is the simplest possible expression. With it, you can create your logic circuit. You may need to apply some bubble pushing to make the final circuit practical, as shown in Fig. 12.28.
FIGURE 12.28
To apply Karnaugh mapping to four-input circuits, you apply the same basic steps used in the three-input scheme. However, now you must use a 4 × 4 Karnaugh map to hold all the necessary information. Figure 12.28 shows an example of how a four-input truth table (or unsimplified four-variable SOP expression) can be mapped and converted into a simplified SOP expression that can be used to create the final logic circuit.
Figure 12.29 shows an example that uses an AOI IC to implement the final SOP expression after mapping. I’ve thrown in variables other than the traditional A, B, C, and D just to let you know you are not limited to them alone. The choice of variables is up to you and usually depends on the application.
FIGURE 12.29
Other Looping Configurations
Figure 12.30 shows examples of other looping arrangements used with 4 × 4 Karnaugh maps.
FIGURE 12.30
There are also useful online resources for exploring truth tables and minimizing logical expressions, such as these:
12.3 Combinational Devices
Now that you know a little something about how to use logic gates to enact functions represented within truth tables and Boolean expressions, it is time to take a look at some common functions that are used in the real world of digital electronics. As you will see, these functions are usually carried out by an IC that contains all the necessary logic.
As with almost everything discussed in this chapter, before using these ideas, you need to ask yourself if using a microcontroller would be more appropriate. However, many of the devices described here can be used with a microcontroller, especially when it comes to decoders. They can be a useful and low-cost solution for tasks such as driving more LEDs than there are pins on the microcontroller that you are using.
A word on IC part numbers before we begin. As with the logic gate ICs, the combinational ICs that follow will be of either the 4000 or 7400 series. It is important to note that an original TTL IC, like the 74138, is essentially the same device (usually with the same pinouts and function, but not always) as its newer counterparts, such as the 74F138, 74HC128 (CMOS), and 74LS138. The practical difference resides in the overall performance of the device (speed, power dissipation, voltage level rating, and so on). I will get into these gory details in a bit.
FIGURE 12.31
Multiplexers or data selectors act as digitally controlled switches. The term data selector appears to be the accepted term when the device is designed to act like an SPDT switch, while the term multiplexer is used when the throw count of the switch exceeds two, such as an SP8T. I will stick with this convention (although others may not).
A simple 1-of-2 data selector built from logic gates is shown in Fig. 12.32. The data select input of this circuit acts to control which input (A or B) gets passed to the output: When data select is low, input A passes while B is blocked. When data select is high, input B is passed while A is blocked. To understand how this circuit works, think of the AND gates as enable gates.
FIGURE 12.32
There are a number of different types of data selectors that come in IC form. For example, the 74LS157 quad 1-of-2 data selector IC, shown in Fig. 12.32, acts like an electrically controlled quad SPDT switch (or if you like, a 4PDT switch). When its select input is set high (1), inputs A1, A2, A3, and A4 are allowed to pass to outputs Q1, Q2, Q3, and Q4. When its select input is low (0), inputs B1, B2, B3, and B4 are allowed to pass to outputs Q1, Q2, Q3, and Q4. Either of these two conditions, however, ultimately depends on the state of the enable input.
When the enable input is low, all data-input signals are allowed to pass to the output; however, if the enable is high, the signals are not allowed to pass. This type of enable control is referred to as active-low enable, since the active function (passing the data to the output) occurs only with a low-level input voltage. The active-low input is denoted with a bubble (inversion bubble), and the outer label of the active-low input is represented with a line over it. Sometimes people omit the bubble and place a bar over the inner label. Both conventions are used commonly.
FIGURE 12.33
Figure 12.33 shows a 4-line-to-1-line multiplexer built with logic gates. This circuit resembles the 2-of-1 data selector shown in Fig. 12.32 but requires an additional select input to provide four address combinations.
In terms of ICs, there are multiplexers of various input line capacities. For example, the 74151 8-line-to-1-line multiplexer uses three select inputs (S0, S1, S2) to choose among one of eight possible data inputs (I0 to I7) to be funneled to the output. Note that this device actually has two outputs: one true (pin 5) and one inverted (pin 6). The active-low enable forces the true output low when set high, regardless of the inputs.
To create a larger multiplexer, you combine two smaller multiplexers together. For example, Fig. 12.34 shows two 8-line-to-1-line 74HC151s combined to create a 16-line-to-1-line multiplexer. Another alternative is to use a 16-line-to-1-line multiplexer IC like the 74HC150 shown in the figure. Check the catalogs to see what other kinds of multiplexers are available.
FIGURE 12.34
Finally, let’s take a look at a very useful device called a bilateral switch. An example bilateral switch IC is the 4066, shown to the far right in Fig. 12.32. Unlike the multiplexer, this device merely acts as a digitally controlled quad SPST switch or quad transmission gate. Using a digital control input, you select which switches are on and which switches are off. To turn on a given switch, apply a high level to the corresponding switch select input; otherwise, keep the select input low.
In Section 12.10, we will look at analog switches and multiplexers. These devices use digital select inputs to control analog signals. Analog switches and multiplexers become important when you start linking the digital world to the analog world.
A demultiplexer (or data distributor) is the opposite of a multiplexer. It takes a single data input and routes it to one of several possible outputs. A simple four-line demultiplexer built from logic gates is shown on the left side of Fig. 12.35. To select the output (A, B, C, or D) to which you want to send the input signal (applied at E), you apply logic levels to the data select inputs (S0, S1), as shown in the truth table.
FIGURE 12.35
Notice that the unselected outputs assume a high level, while the selected output varies with the input signal. An IC that contains two functionally separate four-line demultiplexers is the 74HC139, shown on the right side of Fig. 12.35. If you need more outputs, check out the 75xx154 16-line demultiplexer. This IC uses four data select inputs to choose from 1 of 16 possible outputs. Check out the catalogs to see what other demultiplexers exist.
A decoder is somewhat like a demultiplexer, but it does not route input data to a specific output via data select inputs. Instead, it simply uses the data select inputs to choose which output (or outputs) among many are to be made high or low. The number of address inputs, the number of outputs, and the active state of the selected output vary from decoder to decoder. The variance is based on what the decoder is designed to do. For example, the 74LS138 1-of-8 decoder shown in Fig. 12.36 uses a 3-bit address input to select which of eight outputs will be made low; all other outputs are held high. Like the demultiplexer in Fig. 12.35, this decoder has active-low outputs.
FIGURE 12.36
Now what exactly does it mean to say an output is an active-low output? It simply means that when an active-low output is selected, it is forced to a low logic state; otherwise, it is held high. Active-high outputs behave in the opposite manner. An active-low output is usually indicated with a bubble, although sometimes it is indicated with a barred variable within the IC logic symbol—no bubble included. Active-high outputs have no bubbles. Both active-low and active-high outputs are equally common among ICs.
By placing a load (for example, a warning LED) between +VCC and an active-low output, you can sink current through the load and into the active-low output when the output is selected. By placing a load between an active-high output and ground, you can source current from the active-high output and sink it through the load when the output is selected. The limits to how much current an IC can source or sink will be discussed in Section 12.4, and various schemes used to drive analog loads will be presented in Section 12.10.
Now let’s get back to the 74LS138 decoder and discuss the remaining enable inputs (
0,1,E2). For the 74LS138 to “decode,” you must make the active-low inputs 0 and 1 low, while making the active-high input E2 high. If any other set of enable inputs is applied, the decoder is disabled, making all active-low outputs high regardless of the selected inputs.
0,1,E2). For the 74LS138 to “decode,” you must make the active-low inputs 0 and 1 low, while making the active-high input E2 high. If any other set of enable inputs is applied, the decoder is disabled, making all active-low outputs high regardless of the selected inputs.Other common decoders include the 7442 BCD-to-DEC (decimal) decoder, the 74154 1-of-16 (hex) decoder, and the 7447 BCD-to-seven-segment decoder shown in Figure 12.37. Like the preceding decoder, these devices also have active-low outputs. The 7442 uses a binary-coded decimal input to select 1 of 10 (0 through 9) possible outputs. The 74154 uses a 4-bit binary input to address 1 of 16 (or 0 of 15) outputs, making that output low (all others high), provided the enables are both set low.
FIGURE 12.37
Now the 7447 is a bit different from the other decoders. With this device, more than one output can be driven low at a time. This is important because it allows the 7447 to drive a seven-segment LED display; to create different numbers requires driving more than one LED segment at a time. For example, in Fig. 12.38, when the BCD number for 5 (0101) is applied to the 7447’s inputs, all outputs except 
and 
go low. This causes LED segments a, c, d, f, and g to light up—the 7447 sinks current through these LED segments, as indicated by the internal wiring of the display and the truth table.
and go low. This causes LED segments a, c, d, f, and g to light up—the 7447 sinks current through these LED segments, as indicated by the internal wiring of the display and the truth table.
FIGURE 12.38
The 7447 also comes with a lamp test active-low input (
) that can be used to drive all LED segments at once to see if any of the segments are faulty. The ripple blanking input (
) and ripple blanking output (
) can be used in multistage display applications to suppress a leading-edge and/or trailing-edge zero in a multidigit decimal. For example, using the ripple blanking inputs and outputs, it is possible to take an eight-digit expression like 0056.020 and display 56.02, suppressing the two leading zeros and the one trailing zero. Leading-edge zero suppression is obtained by connecting the ripple blanking output of a decoder to the ripple blanking input of the next lower-stage device. The most significant decoder stage should have its ripple blanking input grounded. A similar procedure is used to provide automatic suppression of trailing zeros in the fractional part of the decimal.
) that can be used to drive all LED segments at once to see if any of the segments are faulty. The ripple blanking input () and ripple blanking output () can be used in multistage display applications to suppress a leading-edge and/or trailing-edge zero in a multidigit decimal. For example, using the ripple blanking inputs and outputs, it is possible to take an eight-digit expression like 0056.020 and display 56.02, suppressing the two leading zeros and the one trailing zero. Leading-edge zero suppression is obtained by connecting the ripple blanking output of a decoder to the ripple blanking input of the next lower-stage device. The most significant decoder stage should have its ripple blanking input grounded. A similar procedure is used to provide automatic suppression of trailing zeros in the fractional part of the decimal.12.3.3 Encoders and Code Converters
Encoders are the opposite of decoders. They are used to generate a coded output from a single active numeric input. To illustrate this in a simple manner, let’s take a look at the simple decimal-to-BCD encoder circuit shown in Fig. 12.39.
FIGURE 12.39
In this circuit, normally all lines are held high by the pullup resistors connected to +5 V. To generate a BCD output that is equivalent to a single selected decimal input, the switch corresponding to that decimal is closed. (The switch acts as an active-low input.) The truth table in Fig. 12.39 explains the rest.
Figure 12.40 shows a 74LS147 decimal-to-BCD (ten-line-to-four-line) priority encoder IC. The 74LS147 provides the same basic function as the circuit shown in Fig. 12.39, but it has active-low outputs. This means that instead of getting an LLHH output when 3 is selected, as in the previous encoder, you get HHLL. The two outputs represent the same thing (3); one is expressed in positive true logic, and the other (the 74LS147) is expressed in negative true logic. If you do not like negative true logic, you can slap inverters on the outputs of the 74LS147 to get positive true logic. The choice to use positive or negative true logic really depends on what you are planning to drive. For example, negative true logic is useful when the device that you wish to drive uses active-low inputs.
FIGURE 12.40
Another important difference between the two encoders is the priority that is used with the 74LS147 and not used with the encoder in Fig. 12.39. The term priority is applied to the 74LS147 because this encoder is designed so that if two or more inputs are selected at the same time, it will select only the larger-order digit. For example, if 3, 5, and 8 are selected at the same time, only the 8 (negative true BCD LHHH or 0111) will be output. The truth table in Fig. 12.40 demonstrates this; look at the “don’t care” or “X” entries. With the nonpriority encoder, if two or more inputs are applied at the same time, the output will be unpredictable.
The circuit shown in Fig. 12.41 provides a simple illustration of how an encoder and a decoder can be used together to drive an LED display via a 0 through 9 keypad. The 74LS147 encodes a keypad’s input into BCD (negative logic). A set of inverters then converts the negative true BCD into positive true BCD. The transformed BCD is then fed into a 7447 seven-segment LED display decoder/driver IC.
FIGURE 12.41
Figure 12.42 shows a 74148 octal-to-binary priory encoder IC. It is used to transform a specified single octal input into a binary 3-bit output code. As with the 74LS147, the 74148 comes with a priority feature, so if two or more inputs are selected at the same time, only the higher-order number is selected.
FIGURE 12.42
A high applied to the input enable (
) forces all outputs to their inactive (high) state and allows new data to settle without producing erroneous information at the outputs. A group signal output (
) and an enable output (
) are also provided to allow for system expansion. The output is active level low when any input is low (active). The output is low (active) when all inputs are high. Using the output enable along with the input enable allows priority coding of N input signals. Both and are active high when the input enable is high (device disabled).
) forces all outputs to their inactive (high) state and allows new data to settle without producing erroneous information at the outputs. A group signal output () and an enable output () are also provided to allow for system expansion. The output is active level low when any input is low (active). The output is low (active) when all inputs are high. Using the output enable along with the input enable allows priority coding of N input signals. Both and are active high when the input enable is high (device disabled).Figure 12.43 shows a 74184 BCD-to-binary converter (encoder) IC. This device has eight active-high outputs (Y1 – Y8). Outputs Y1 to Y5 are outputs for regular BCD-to-binary conversion, while outputs Y6 to Y8 are used for a special BDC code called nine’s complement and ten’s complement. The active-high BCD code is applied to inputs A through E. The 
input is an active-low enable input.
input is an active-low enable input.
FIGURE 12.43
A sample 6-bit BCD-to-binary converter and a sample 8-bit BCD-to-binary converter that use the 74184 are shown to the right in Fig. 12.43. In the 6-bit circuit, since the LSB of the BCD input is always equal to the LSB of the binary output, the connection is made straight from input to output. The other BCD bits are applied directly to inputs A through E. The binary weighing factors for each input are A = 2, B = 4, C = 8, D = 10, and E = 20. Because only 2 bits are available for the MSD BCD input, the largest BCD digit in that position is 3 (binary 11). To get a complete 8-bit BCD converter, you connect two 74184s together, as shown to the far right in Fig. 12.43.
Figure 12.44 shows a 74185 binary-to-BCD converter (encoder). It is essentially the same as the 74184, but in reverse. The figure shows 6-bit and 8-bit binary-to-BCD converter arrangements.
FIGURE 12.44
12.3.4 Binary Adders
If you find yourself needing to do arithmetic in logic, then that is a pretty sure sign that you need to use a microcontroller. However, that microcontroller will contain exactly the sort of logic that we describe here in its arithmetic logic unit (ALU), so it is instructive to see how it works under the hood.
With a few logic gates, you can create a circuit that adds binary numbers. The mechanics of adding binary numbers is basically the same as that of adding decimal numbers. When the first digit of a two-digit number is added, a 1 is carried and added to the next row whenever the count exceeds binary 2 (for example., 1 + 1 = 10, or = 0 carry a 1). For numbers with more digits, you have multiple carry bits.
To demonstrate how you can use logic gates to perform basic addition, start out by considering the half-adder circuits in Fig. 12.45. Both half-adders shown are equivalent; one simply uses XOR/AND logic, while the other uses NOR/AND logic. The half-adder adds two single-bit numbers A and B and produces a 2-bit number. The LSB is represented as Σ0, and the MSB, or carry bit, is represented as Cout.
FIGURE 12.45
The most complicated operation the half-adder can do is 1 + 1. To perform addition on a two-digit number, you must attach a full-adder circuit (shown in Fig. 12.45) to the output of the half-adder. The full-adder has three inputs: two to input the second digits of the two binary numbers (A1, B1), and another that accepts the carry bit from the half-adder (the circuit that added the first digits, A0 and B0, of the two numbers). The two outputs of the full-adder will provide the 2d-place digit sum Σ1 and another carry bit that acts as the third-place digit of the final sum. Now, you can keep adding more full-adders to the half-adder/full-adder combination to add larger numbers, linking the carry bit output of the first full-adder to the next full-adder, and so forth. To illustrate this point, a 4-bit adder is shown in Fig. 12.45.
A number of 4-bit full-adder ICs are available, such as the 74LS283 and 4008. These devices will add two 4-bit binary numbers and provide an additional input carry bit, as well as an output carry bit, so you can stack them together to get adders that are 8-bit, 12-bit, 16-bit, and so on. For example, Fig. 12.46 shows an 8-bit adder made by cascading two 74LS283 4-bit adders.
FIGURE 12.46
12.3.5 Binary Adder/Subtractor
Figure 12.47 shows how two 74LS283 4-bit adders can be combined with an XOR array to yield an 8-bit 2’s complement adder/subtractor. The first number X is applied to the X0 through X7 inputs, while the second number Y is applied to the Y0 through Y7 inputs.
FIGURE 12.47
To add X and Y, the add/subtract switch is thrown to the add position, making one input of all XOR gates low. This has the effect of making the XOR gates appear transparent, allowing Y values to pass to the 74LS283s’ B inputs (X values are passed to the A inputs). The 8-bit adder then adds the numbers and presents the result to the Σ outputs.
To subtract Y from X, you must first convert Y into 1’s complement form; then you must add 1 to get Y into 2’s complement form. After that you simply add X to the 2’s complemented form of Y to get X−Y. When the add/subtract switch is thrown to the subtract position, one input to each XOR gate is set high. This causes the Y bits that are applied to the other XOR inputs to become inverted at the XOR outputs—you have just taken the 1’s complement of Y. The 1’s complement bits of Y are then presented to the inputs of the 8-bit adder. At the same time, Cin of the left 74LS283 is set high via the wire (see Fig. 12.47) so that a 1 is added to the 1’s complement number to yield a 2’s complement number. The 8-bit adder then adds X and the 2’s complement of Y together. The final result is presented at the Σ outputs. In the figure, 76 is subtracted from 28.
12.3.6 Arithmetic Logic Units
An ALU is a multipurpose integrated circuit capable of performing various arithmetic and logic operations. To choose a specific operation to be performed, a binary code is applied to the IC’s mode select inputs. The 74181, shown in Fig. 12.48, is a 4-bit ALU that provides 16 arithmetic and 16 logic operations.
FIGURE 12.48
To select an arithmetic operation, the 74181’s mode control input (M) is set low. To select a logic operation, the mode control input is set high. Once you have decided whether you want to perform a logic or arithmetic operation, you apply a 4-bit code to the mode select inputs (S0, S1, S2, and S3) to specify which specific operation, as indicated within the truth table, is to be performed. For example, if you select S3 = 1, S2 = 1, S1 = 1, S0 = 0, while M = 1, then you get F0 = A0 + B0, F1 = A1 + B1, F2 = A2 + B2, F3 = A3 + B3. Note that the + shown in the truth table does not represent addition; it is used to represent the OR function. For addition, the tables use “plus.” Carry-in (N) and carry-out (CN + 4) leads are provided for use in arithmetic operations. All arithmetic results generated by this device are in 2’s complement notation.
N) and carry-out (CN + 4) leads are provided for use in arithmetic operations. All arithmetic results generated by this device are in 2’s complement notation.A digital comparator is a circuit that accepts two binary numbers and determines whether the two numbers are equal. For example, Fig. 12.49 shows a 1-bit and a 4-bit comparator. The 1-bit comparator outputs a high (1) only when the two 1-bit numbers A and B are equal. If A is not equal to B, then the output goes low (0). The 4-bit is basically four 1-bit comparators in one. When all individual digits of each number are equal, all XOR gates output a high, which in turn enables the AND gate, making the output high. If any two corresponding digits of the two numbers are not equal, the output goes low.
FIGURE 12.49
Now, say you want to know which number, A or B, is larger. The circuits in Fig. 12.49 will not do the trick. What you need instead is a magnitude comparator like the 74HC85 shown in Fig. 12.50. This device not only tells you if two numbers are equal, but also which number is larger. For example, if you apply a 1001 (910) to the A3A2A1A0 inputs and a second number 1100 (1210) to the B3B2B1B0 inputs, the A < B output will go high (the other two outputs, A > B and A = B, will remain low). If A and B were equal, the A = B output would have gone high, and so on. If you wanted to compare larger numbers—say, two 8-bit numbers—you simply cascade two 74HC85 comparators together, as shown on the right side of Fig. 12.50. The leftmost 74HC85 compares the lower-order bits, while the rightmost 74HC85 compares the higher-order bits. To link the two devices together, you connect the output of the lower-order device to the expansion inputs of the higher-order device, as shown. The lower-order device’s expansion inputs are always set low (IA < B), high (IA = B), and low (IA > B).
FIGURE 12.50
12.3.8 Parity Generator/Checker
Often, external noise can corrupt binary information (cause a bit to flip from one logic state to the other) as it travels along a conductor from one device to the next. For example, in the 4-bit system shown in Fig. 12.51, a BCD 4 (0100) picks up noise and becomes 0101 (or 5) before reaching its destination. Depending on the application, this type of error could lead to some serious problems.
FIGURE 12.51
To avoid problems caused by unwanted data corruption, a parity generator/checker system, like the one shown in Fig. 12.51, can be used. The basic idea is to add an extra bit, called a parity bit, to the digital information being transmitted. If the parity bit makes the sum of all transmitted bits (including the parity bit) odd, the transmitted information is of odd parity. If the parity bit makes the sum even, the transmitted information is of even parity. A parity generator circuit creates the parity bit, while the parity checker on the receiving end determines if the information sent is of the proper parity. The type of parity (odd or even) is agreed to beforehand, so the parity checker knows what to look for. The parity bit can be placed next to the MSB or the LSB, provided the device on the receiving end knows which bit is the parity bit and which bits are the data. The arrangement shown in Fig. 12.51 is designed with an even-parity error-detection system.
If you want to avoid building parity generators and checkers from scratch, use a parity generator/checker IC like the 74F280 9-bit odd-even parity generator/checker shown in Fig. 12.52. To make a complete error-detection system, two 74F280s are used: one acts as the parity generator, and the other acts as the parity checker. The generator’s inputs A through H are connected to the eight data lines of the transmitting portion of the circuit. The ninth input (I) is grounded when the device is used as a generator. If you want to create an odd-parity generator, you tap the Σodd output; for even parity, you tap Σeven. The 74F280 checker taps the main line at the receiving end and also accepts the parity bit line at input I. Figure 12.52 shows an odd-parity error-detection system used with an 8-bit system. If an error occurs, a high (1) is generated at the Σodd output.
FIGURE 12.52
12.3.9 A Note on Obsolescence and the Trend Toward Microcontroller Control
We have just covered most of the combinational devices you will find discussed in textbooks and listed within electronic catalogs. Many of these devices are still used. However, some devices, such as the binary adders and code converters, are obsolete.
Today, the trend is to use software-controlled devices such as microprocessors and microcontrollers to carry out arithmetic operations and code conversions. Before you attempt to design any logic circuit, I suggest jumping to Chapter 13, which covers microcontrollers.
Microcontrollers can be used to collect data, store data, and perform logical operations using the input data. They also can generate output signals that can be used to control displays, audio devices, stepper motors, servos, and so on. The specific functions a microcontroller is designed to perform depend on the program you store in its internal ROM-type memory.
Programming the microcontroller typically involves simply using a special programming unit provided by the manufacturer. The programming unit usually consists of a prototyping platform that is linked to a host computer (via a USB port) that is running a development environment. In the development environment, you typically write out a program in a high-level language such as C, or some other specialized language designed for a certain microcontroller, and then, with the press of a key, the program is converted into machine language (1s and 0s) and downloaded into the microcontroller’s memory.
In many applications, a single microcontroller can replace entire logic circuits composed of numerous discrete components. For this reason, it is tempting to skip the rest of this chapter and go directly to the chapter on microcontrollers. However, there are three basic problems with this approach:
• If you are a beginner, you will miss out on many important principles behind digital control that are most easily understood by learning how the discrete components work.
• Many digital circuits that you can build simply do not require the amount of sophistication a microcontroller provides.
• You may feel intimidated by the electronics catalogs that list every conceivable component available (even those that are obsolete). Knowing what’s out there and knowing what to avoid are also important parts of the learning process.
12.4 Logic Families
Before moving on to sequential logic, let’s touch on a few practical matters regarding the various logic families available and what kind of operating characteristics these families have. In this section, you will also encounter unique logic gates that have open-collector output stages and logic gates that have Schmitt-triggered inputs.
The key ingredient within any integrated logic device—a logic gate, a multiplexer, or a microprocessor—is the transistor. The kinds of transistors used within the IC, to a large extent, specify the type of logic family. The two most popular transistors used in ICs are bipolar and MOSFET transistors.
In general, ICs made from MOSFET transistors use less space due to their simpler construction, have very high noise immunity, and consume less power than equivalent bipolar transistor ICs. However, the high-input impedance and input capacitance of the MOSFET transistors (due to their insulated gate leads) result in longer time constants for transistor on/off switching speeds when compared with bipolar gates, and therefore typically result in a slower device. Over years of development, however, the performance gap between these two technologies has narrowed considerably.
Both the bipolar and MOSFET logic families can be divided into a number of subclasses. The major subclasses of the bipolar family include transistor-transistor logic (TTL), emitter-coupled logic (ECL), and integrated-injection logic (IIL or I2L). The major subclasses of the MOSFET logic include P-channel MOSFET (PMOS), N-channel MOSFET (NMOS), and complementary MOSFET (CMOS). CMOS uses both NMOS and PMOS technologies. The two most popular technologies are TTL and CMOS. The other technologies are typically used in large-scale integration devices, such as microprocessors and memories. There are new technologies popping up all the time, which yield faster, more energy-efficient devices. Some examples include BiCMOS, GaAS, SOS, and Josephson junction technologies.
FIGURE 12.53
As you have already learned, TTL and CMOS devices are grouped into functional categories that get placed into either the 7400 series (74F, 74LS, 74HC (CMOS), and so on) or 4000 CMOS series (or the improved 4000B series). Another series you will run into is the 5400 series. This series is essentially equivalent to the 7400 series (with the same pinouts and same basic logic function), but it is a more expensive chip because it is designed for military applications that require increased supply voltage tolerances and temperature tolerances. For example, a 7400 IC typically has a supply voltage range from 4.75 to 5.25 V with a temperature range from 0 to 70°C. A 5400 IC typically has a voltage range between 4.5 and 5.5 V and a temperature range from -55 to 125°C.
12.4.1 TTL Family of ICs
The original TTL series, referred to as the standard TTL series (74xx), was developed early in the 1960s. This series is still in use, even though its overall performance is inferior to the newer line of TTL devices, such as the 74LSxx, 74ALSxx, and 74Fxx. The internal circuitry of a standard TTL 7400 NAND gate, along with a description of how it works, is provided next.
The TTL NAND gate is divided into three basic sections: multi-emitter input, control section, and totem-pole output stage. In the multi-emitter input section, a multi-emitter bipolar transistor Q1 acts like a two-input AND gate, while diodes D1 and D2 act as negative clamping diodes used to protect the inputs from any short-term negative input voltages that could damage the transistor. Q2 provides control and current boosting to the totem-pole output stage; when the output is high (1), Q4 is off (open) and Q3 is on (short). When the output is low (0), Q4 is on and Q3 is off. Because one or the other transistor is always off, the current flow from VCC to ground in that section of the circuit is minimized. The lower figures show both a high and low output state, along with the approximate voltages present at various locations. Notice that the actual output voltages are not exactly 0 or +5 V—a result of internal voltage drops across resistor, transistor, and diode. Instead, the outputs are around 3.4 V for high and 0.3 V for low. Note that to create, say, an eight-input NAND gate, the multi-emitter input transistor would have eight emitters instead of just two as shown.
FIGURE 12.54
A simple modification to the standard TTL series was made early on by reducing all the internal resistor values in order to reduce the RC time constants and thus increase the speed (reduce propagation delays). This improvement to the original TTL series marked the 74H series. Although the 74H series offered improved speed (about twice as fast) over the 74 series, it had more than double the power consumption. Later, the 74L series emerged. Unlike the 74H, the 74L took the 74 and increased all internal resistances. The net effect led to a reduction in power but increased propagation delay.
A significant improvement in speed within the TTL line emerged with the development of the 74Sxx series (Schottky TTL series). The key modifications involved placing Schottky diodes across the base-to-collector junctions of the transistors. These Schottky diodes eliminated capacitive effects caused by charge buildup in the transistor’s base region by passing the charge to the collector region. Schottky diodes were the best choice because of their inherent low charge buildup characteristics. The overall effect was an increase in speed by a factor of 5 and only a doubling in power.
Continually over time, by using different integration techniques and increasing the values of the internal resistors, more power-efficient series emerged, like the low-power Schottky 74LS series, with about one-third the power dissipation of the 74S. After the 74LS, the advanced-low-power Schottky 74ALS series emerged, which had even better performance. Another series developed around this time was the 74F series, or FAST logic, which used a new process of integration called oxide isolation (also used in the ALS series) that led to reduced propagation delays and decreased the overall size.
Today you will find many of the older series listed in electronics catalogs. Which series you choose ultimately depends on availability, cost, and what kind of performance you are seeking.
12.4.2 CMOS Family of ICs
While the TTL series was going through its various transformations, the CMOS series entered the picture. The original CMOS 4000 series (or the improved 4000B series) was developed to offer lower power consumption than the TTL series of devices—a feature made possible by the high input impedance characteristics of its MOSFET transistors. The 4000B series also offered a larger supply voltage range (3 to 18 V), with minimum logic high = 
VDD and maximum logic low = 
VDD. The 4000B series, though more energy efficient than the TTL series, was significantly slower and more susceptible to damage due to electrostatic discharge. Figure 12.55 shows the internal circuitry of CMOS NAND, AND, and NOR gates. To figure out how the gates work, apply high (logic 1) or low (logic 0) levels to the inputs and see which transistor gates turn on and which transistor gates turn off.
VDD and maximum logic low = VDD. The 4000B series, though more energy efficient than the TTL series, was significantly slower and more susceptible to damage due to electrostatic discharge. Figure 12.55 shows the internal circuitry of CMOS NAND, AND, and NOR gates. To figure out how the gates work, apply high (logic 1) or low (logic 0) levels to the inputs and see which transistor gates turn on and which transistor gates turn off.
FIGURE 12.55
A further improvement in speed over the original 4000B series came with the introduction of the 40H00 series. Although this series was faster than the 4000B series, it was not quite as fast as the 74LS TTL series. The 74C CMOS series also emerged on the scene, which was designed specifically to be pin-compatible with the TTL line.
Another significant improvement in the CMOS family came with the development of the 74HC and the 74HCT series. Both these series, like the 74C series, were pin-compatible with the TTL 74 series. The 74HC (high-speed CMOS) series had the same speed as the 74LS, as well as the traditional CMOS low-power consumption. The 74HCT (high-speed CMOS TTL compatible) series was developed to be interchangeable with TTL devices (same I/O voltage level characteristics). The 74HC series is very popular today.
Still further improvements in 74HC/74HCT series led to the advanced CMOS logic (74AC/74ACT) series. The 74AC (advanced CMOS) series approached speeds comparable with the 74F TTL series, while the 74ACT (advanced CMOS TTL compatible) series was designed to be TTL compatible.
12.4.3 I/O Voltages and Noise Margins
The exact input voltage levels required for a logic IC to perceive a high (logic 1) or low (logic 0) input level differ between the various logic families. At the same time, the high and low output levels provided by a logic IC vary among the logic families. For example, Fig. 12.56 shows valid input and output voltage levels for both the 74LS (TTL) and 74HC (CMOS) families.
FIGURE 12.56
In Fig. 12.56, the voltage ranges are represented as follows:
• VIH represents the valid voltage range that will be interpreted as a high logic input level.
• VIL represents the valid voltage range that will be interpreted as a low logic input level.
• VOL represents the valid voltage range that will be guaranteed as a low logic output level.
• VOH represents the valid voltage range that will be guaranteed as a high logic output level.
As you can see from Fig. 12.56, if you connect the output of a 74HC device to the input of a 74LS device, there is no problem—the output logic levels of the 74HC are within the valid input range of the 74LS. However, if you turn things around, driving a 74HC device’s inputs from a 74LS’s output, you have problems—a high output level from the 74LS is too small to be interpreted as a high input level for the 74HC. Section 12.4.9 shows some tricks used to interface the various logic families together.
12.4.4 Current Ratings, Fanout, and Propagation Delays
Logic IC inputs and outputs can sink or source only a given amount of current. IIL is defined as the maximum low-level input current, IIH as the maximum high-level input current, IOH as the maximum high-level output current, and IOL as the maximum low-level output current. As an example, a standard 74xx TTL gate may have an IL = −1.6 mA and IIH = 40 μA while having an IOL = 16 mA and IOH = −400 μA. The negative sign means that current is leaving the gate (the gate is acting as a source). A positive sign means that current is entering the gate (the gate is acting as sink).
The limit to how much current a device can sink or source determines the size of loads that can be attached. The term fanout is used to specify the total number of gates that can be driven by a single gate of the same family without exceeding the current rating of the gate. The fanout is determined by taking the smaller result of IOL/IIL or IOH/IIH. For the standard 74 series, the fanout is 10 (16 mA/1.6 mA). For the 74LS series, the fanout is around 20; for the 74F, it is around 33; and for the 7HC, it is around 50.
If you apply a square pulse to the input of a logic gate, the output signal will experience a sloping rise time and fall time, as shown in the graph in Fig. 12.57. The rise time (tr) is the length of time it takes for a pulse to rise from 10 to 90 percent of its high level (e.g., 5 V = high: 0.5 V = 10%, 4.5 V = 90%). The fall time (tf) is the length of time it takes for a high level to fall from the 90 to 10 percent.
FIGURE 12.57
The rise and fall times, however, are not as significant when compared with propagation delays between input transition and output response. Propagation delay results from the limited switching speeds of the internal transistors within the logic device. The low-to-high propagation delay TPHL is the time it takes for the output of a device to switch from low to high after the input transition. The high-to-low propagation delay TPLH is the time it takes for the output to switch from high to low after the input transition. When designing circuits, it is important to take into account these delays, especially when you start dealing with sequential logic, where timing is everything. Figs. 12.58 and 12.59 provide typical propagation delays for various TTL and CMOS devices. Manufacturers will provide more accurate propagation information in their data sheets.
FIGURE 12.58
12.4.5 A Detailed Look at the TTL and CMOS Subfamilies
The information shown in Figs. 12.58 and 12.59, especially the data pertaining to propagation delays and current ratings, represents typical values for a given logic series. For more accurate data about a specific device, you must consult the manufacturer’s literature. In other words, use the provided information only as a rough guide to get a feeling for the overall performance of a given logic series.
12.4.6 A Look at a Few Other Logic Series
The 74-BiCMOS Series
The 74-BiCMOS series of devices incorporates the best features of bipolar and CMOS technology together in one package. The overall effect is an extremely high-speed, low-power digital logic family. This product line is especially well suited for, and mostly limited to, microprocessor bus interface logic. Each manufacturer uses a different suffix to identify its BiCMOS line. For example, Texas Instruments uses 74BCTxx, while Signetics (Phillips) uses 74ABTxx.
The 74-Low-Voltage Series
The 74-low-voltage series is a relatively new series that uses a nominal supply voltage of 3.3 V. Members of this series include the 74LV (low-voltage HCMOS), 74LVC (low-voltage CMOS), 74LVT (low-voltage technology), and 74ALVC (advanced low-voltage CMOS). See Fig. 12.60.
A relatively new series of logic uses a nominal supply voltage of 3.3 V and is designed for extremely low-power and low-voltage applications (such as battery-powered devices). The switching speed of LV logic is extremely fast, ranging from about 9 ns for the LB series down to 2.1 ns for the ALVC. Another nice feature of LV logic is high output drive capability. The LVT, for example, can sink up to 64 mA and source up to 32 mA.
FIGURE 12.60
Emitter-Coupled Logic
Emitter-coupled logic (ECL), a member of the bipolar family, was used for extremely high-speed applications, reaching speeds up to 500 MHz with propagation delays as low as 0.8 ns. There is one problem with ECL: it consumes a considerable amount of power when compared with the TTL and CMOS series.
ECL is obsolete now, but was used in computer systems, where power consumption is not as big an issue as speed. The trick to getting the bipolar transistors in an ECL device to respond so quickly is to never let the transistors saturate. Instead, high and low levels are determined by which transistor in a differential amplifier is conducting more. Figure 12.61 shows the internal circuitry of an OR/NOR ECL gate. The high and low logic-level voltages (−0.8 and −17 V, respectively) and the supply voltage (−5.2 V/0 V) are somewhat unusual and cause problems when interfacing with TTL and CMOS.
The OR/NOR gate shown here is composed of a differential amplifier input stage and an output stage. In the differential amplifier stage, a reference voltage is set up at Q3’s base via the voltage divider network (diodes/resistors). This reference voltage determines the threshold between high and low logic levels. When the base of Q3 is at a more positive potential with respect to the emitter of Q1 and Q2, Q3 conducts. When Q5 conducts, the OR output goes low. If either input A or B is raised to −0.8 V (high), the base of Q1 or Q2 will be at a higher potential than the base of Q3, and Q3 will cease conducting, forcing the OR output high. The overall effect of the ECL design prevents transistors from saturating, thereby eliminating charge buildup on the base of the transistors that limits switching speeds.
FIGURE 12.61
12.4.7 Logic Gates with Open-Collector Outputs
Among the members of the TTL series is a special class of logic gates that have open-collector output stages instead of the traditional totem-pole configuration you saw earlier. (Within the CMOS family, there are similar devices that are said to have open-drain output stages). These devices are not to be confused with the typical logic gates you have seen so far. Logic gates with open-collector outputs have entirely different output characteristics.
Figure 12.62 shows a NAND gate with open-collector (OC) output. Notice that the Q3 transistor is missing in the OC NAND gate. By removing Q3, the output no longer goes high when A and B logic levels are set to 00, 01, or 10. Instead, the output floats. When A and B logic levels are both high (1), the output is grounded. This means that the OC gate can only sink current; it cannot source current! So how do you get a high output level?
FIGURE 12.62
You use an external voltage source and a pullup resistor, as shown in the center of Fig. 12.62. Now, when the output floats, the pullup resistor connected to the external voltage source will “pull” the output to the same level as the external voltage source, which in this case is at +15 V. That’s right—you don’t need to use +5 V. That is one of the primary benefits of using OC gates: you can drive load-requiring voltage levels different from those of the logic circuitry.
Another important feature of OC gates is their ability to sink large amounts of currents. For example, the 7406 OC inverter buffer/driver IC is capable of sinking 40 mA, which is 2.5 times the amount of current a standard 7404 inverter can sink. (The 7404 OC buffer/driver has the same sinking ability as the 7406 OC, but does not provide any logic function; it simply acts as a buffer stage.) The ability for an OC gate to sink a reasonably large current makes it useful for driving LED displays and other higher-current loads. Figure 12.63 shows a number of OC logic gate ICs.
FIGURE 12.63
OC gates are also useful in instances where the output from two or more gates or other devices must be tied together. When you use standard gates with totem-pole output stages, if one gate outputs a high (+5 V) while another gate outputs a low (0 V), a direct short circuit is also created, which can cause either or both gates to burn out. By using OC gates, this problem can be avoided.
When working with OC gates, you cannot apply the same Boolean rules you used earlier with the standard gates. Instead, you must use what is called wired-AND logic, which amounts to simply ANDing all gates together, as shown in Fig. 12.62. In other words, the outputs of all the gates must float in order to get a high output level.
12.4.8 Schmitt-Triggered Gates
Schmitt-triggered gates are special-purpose logic gates that come with Schmitt-triggered inputs. Unlike the conventional logic gates, Schmitt-triggered gates have two input threshold voltages: the positive threshold voltage (
) and the negative threshold voltage (
). Example Schmitt-triggered ICs include the quad 7414 inverter, the quad 2-input NAND gate, and the dual 4-input NAND gate shown in Fig. 12.64.
) and the negative threshold voltage (). Example Schmitt-triggered ICs include the quad 7414 inverter, the quad 2-input NAND gate, and the dual 4-input NAND gate shown in Fig. 12.64.
FIGURE 12.64
To get a sense of how these devices work, let’s compare the Schmitt-triggered 7414 inverter gate with a conventional inverter gate, the 7404. With the 7404, to make the output go from high to low or from low to high, the input voltage must fall above or below the single 2.0-V threshold voltage. However, with the 7414, to make the output go from low to high, the input voltage must dip below (which is +0.9 V for this particular IC). To make the output go from high to low, the input voltage must pop above (which is +1.7 V for this particular IC). The difference in voltage between and is called the hysteresis voltage (see Chapter 8 for details). The symbol used to designate a Schmitt trigger is based on the appearance of its transfer function, as shown in Fig. 12.65.
(which is +0.9 V for this particular IC). To make the output go from high to low, the input voltage must pop above (which is +1.7 V for this particular IC). The difference in voltage between and is called the hysteresis voltage (see Chapter 8 for details). The symbol used to designate a Schmitt trigger is based on the appearance of its transfer function, as shown in Fig. 12.65.
FIGURE 12.65
In terms of applications, Schmitt-triggered devices are quite handy for transforming noisy signals or signals that waver around critical threshold levels into sharply defined, jitter-free output signals. This is illustrated in the lower graphs shown in Fig. 12.65. The conventional 7404 experiences an unwanted output spike resulting from a short-term spike present during low-to-high and high-to-low input voltage transitions. The Schmitt-triggered inverter ignores these spikes because it incorporates hysteresis.
12.4.9 Interfacing Logic Families
Mixing of logic families, in general, should be avoided. Obvious reasons for not mixing include differences in I/O logic levels, supply voltages, and output drive capability that exist among the various families. Another important reason involves differences in speed between the various families; if you mix slow-logic ICs with faster-logic ICs, you can run into timing problems.
There are times, however, when mixing is unavoidable or even desirable. For example, perhaps a desired special-purpose device (such as memory or a counter) exists only in CMOS, but the rest of your system consists of TTL. Mixing of families is also common when driving loads. For example, a TTL gate (often with an open-collector output) is frequently used as an interface between a CMOS circuit and an external load, such as LED indicator lights. A CMOS output, by itself, usually does not provide sufficient drive current to power such loads. I will discuss driving loads in Section 12.10.
Figure 12.66 shows tricks for interfacing various logic families. These tricks take care of I/O incompatibility problems as well as supply voltage incompatibility problems. The tricks, however, do not take care of any timing incompatibility problems that may arise.
Figure a. TTL can be directly interfaced with itself or with HCT or ACT.
Figure b. CMOS 74C/4000(B) with VDD = +5 V can drive TTL, HC, HCT, AC, or ACT.
Figure c. HC, HCT, AC, and ACT can directly drive TTL, HC, HCT, AC, ACT, and 74C/4000B (5 V).
Figure d. When 74C/4000(B) uses a supply voltage that is higher than +5 V, a level-shifting buffer IC, like the 4050B, can be used. The 4050B is powered by a 5-V supply and can accept 0-V/15-V logic levels at its inputs, while providing corresponding 0V/5V logic level outputs. The buffer also provides increased output drive current (4000B has a weak output drive capability when compared to TTL).
Figure e. Recall that the actual high output of a TTL gate is around 3.4 V instead of 5 V. But CMOS (VDD = 5 V) inputs may require from 4.4 (HC) to 4.9 V (4000B) for high input levels. If the CMOS device is of the 74C/4000B series, the actual required high input voltage depends on the supply voltage and is equal to 2/3VDD. To provide enough voltage to match voltage levels, a pullup resistor is used. The pullup resistor pulls the input to the CMOS gate up to the supply voltage to which the pullup resistor is connected.
Figure f. Another trick for interfacing TTL with CMOS is to simply use a CMOS TTL-compatible gate, like the 74HCT or 74ACT.
Figures g and h. These two figures show different methods for interfacing a TTL gate with a CMOS gate set to a higher supply voltage. In Figure g, a 4504B level-shifting buffer is used. The 4504B requires two supply voltages: a TTL supply (for 0/5 V levels) and a CMOS supply (for 0 to 15 V levels). In Figure h, an open-collector buffer and 10-k pullup resistor are used to convert the lower-level TTL output voltages into higher-level CMOS input voltages.
FIGURE 12.66
12.5 Powering and Testing Logic ICs
Most TTL and CMOS logic devices will work with 5 V ± 0.25 V (5 percent) supplies like the ones shown in Fig. 12.67. The battery supplies should be avoided when using certain TTL families like the 74xx, 74S, 74AS, and 74F, which dissipate considerably more current than, say, the CMOS 74HC series. Of course, the low-power, low-voltage 74LV, 74LVC, 74LVT, 74ALVC, and 74BCT series, which require from 1.2 to 3.6 V with as low as 2.5 μW/gate power dissipation (for 74BCT), are ideal for small battery-powered applications.
FIGURE 12.67
12.5.1 Power Supply Decoupling
When a TTL device makes a low-to-high or a high-to-low level transition, there is an interval during which the conduction times in the upper and lower totem-pole output transistors overlap. During this interval, a drastic change in power supply current occurs, which results in a sharp, high-frequency current spike within the supply line. If a number of other devices are linked to the same supply, the unwanted spike can cause false triggering of these devices. The spike also can generate unwanted electromagnetic radiation.
To avoid unwanted spikes within TTL systems, decoupling capacitors can be used. A decoupling capacitor, typically multilayer ceramic, from 0.01 to 0.1 μF (>5 V), is placed directly across the VCC-to-ground pins of each IC in the system. The capacitors absorb the spikes and keep the VCC level at each IC constant, thus reducing the likelihood of false triggering and generally electromagnetic radiation. Decoupling capacitors should be placed as close to the ICs as possible to keep current spikes local, instead of allowing them to propagate back toward the power supply. You can usually get by with using one decoupling capacitor for every five to ten gates or one for every five counter or register ICs.
12.5.2 Unused Inputs
Unused inputs that affect the logical state of a chip should not be allowed to float. Instead, they should be tied high or low, as necessary (floating inputs are liable to pick up external electrical noise, which leads to erratic output behavior). For example, a four-input NAND TTL gate that uses only two inputs should have its two unused inputs held high to maintain proper logic operation. A three-input NOR gate that uses only two inputs should have its unused input held low to maintain proper logic operation. Likewise, the CLEAR and PRESET inputs of a flip-flop should be grounded or tied high, as appropriate.
If there are unused sections within an IC (for example, unused logic gates within a multigate package), the inputs that link to these sections can be left unconnected for TTL but not for CMOS. When unused inputs are left unconnected in CMOS devices, the inputs may pick up unwanted charge and may reach a voltage level that causes output MOS transistors to conduct simultaneously, resulting in a large internal current spike from the supply (VDD) to ground. The result can lead to excessive supply current drain and IC damage. To avoid this fate, inputs of unused sections of a CMOS IC should be grounded. Figure 12.68 illustrates what to do with unused inputs for TTL and CMOS NAND and NOR ICs.
FIGURE 12.68
As a last note of caution, never drive CMOS inputs when the IC’s supply voltage is removed. Doing so can damage the IC’s input protection diodes.
12.5.3 Logic Probes and Logic Pulsers
Two simple tools used to test logic ICs and circuits include the test probe and logic pulser, as shown in Fig. 12.69.
FIGURE 12.69
A typical logic probe comes in a pen-like package, with metal probe tip and power supply wires: one red and one black. Red is connected to the positive supply voltage of the digital circuit (VCC), and black is connected to the ground (VSS) of the circuit. To test a logic state within a circuit, the metal tip of the probe is applied. If a high voltage is detected, the probe’s high LED lights up; if a low voltage is detected, the probe’s low LED turns off.
Along with performing simple static tests, logic probes can perform a few simple dynamic tests, such as detecting a single momentary pulse that is too fast for the human eye to detect or detecting a pulse train, such as a clock signal. To detect a single pulse, the probe’s PULSE/MEMORY switch is thrown to the MEMORY position. When a single pulse is detected, the internal memory circuit remembers the single pulse and lights up both the HI LED and PULSE LED at the same time. To clear the memory to detect a new single pulse, the PULSE/MEMORY switch is toggled. To detect a pulse train, the PULSE/MEMORY switch is thrown to the PULSE position. When a pulse train is detected, the PULSE LED flashes on and off.
Logic probes usually will detect single pulses with widths as narrow as 10 ns and will detect pulse trains with frequencies around 100 MHz. Check the specifications that come with your probe to determine these minimum and maximum limits.
A logic pulser allows you to send a single logic pulse or a pulse train through an IC and circuits, where the results of the applied pulses can be monitored by a logic probe. Like a logic probe, the pulser comes with similar supply leads. To send a single pulse, the SINGLE-PULSE/PULSE-TRAIN switch is set to SINGLE-PULSE, and then the SINGLE-PULSE button is pressed. To send a pulse train, switch to PULSE-TRAIN mode. With the pulser model shown in Fig. 12.69, you get to select either 1 pulse per second (pps) or 500 pps.
12.6 Sequential Logic
The combinational circuits covered previously (encoders, decoders, multiplexers, parity generators/checkers, and so on) have the property of input-to-output immediacy. This means that when input data is applied to a combinational circuit, the output responds almost immediately. Now, combinational circuits lack a very important characteristic: they cannot store information. A digital device that cannot store information is not very interesting, practically speaking.
To provide “memory” to circuits, you must create devices that can latch onto data at a desired moment in time. The realm of digital electronics devoted to this subject is referred to as sequential logic. This branch of electronics is referred to as sequential because for data bits to be stored and retrieved, a series of steps must occur in a particular order. For example, a typical set of steps might involve first sending an enable pulse to a storage device, and then loading a group of data bits all at once (parallel load), or perhaps loading a group of data bits in a serial manner, which takes a number of individual steps. At a later time, the data bits may need to be retrieved by first applying a control pulse to the storage device. A series of other pulses might be required to force the bits out of the storage device.
To push bits through sequential circuits usually requires a clock generator. The clock generator is similar to the human heart. It generates a series of high and low voltages (analogous to a series of high and low pressures as the heart pumps blood) that can set bits into action. The clock also acts as a time base on which all sequential actions can be referenced. Clock generators will be discussed in detail in Section 12.6.7. Now, let’s take a look at the most elementary of sequential devices: the SR flip-flop.
12.6.1 SR Flip-Flops
The most elementary data-storage circuit is the set-reset (SR) flip-flop, also referred to as a transparent latch. There are two basic kinds of SR flip-flops: the cross-NOR SR flip-flop and the cross-NAND SR flip-flop.
Consider the cross-NOR SR flip-flop shown in Fig. 12.70. At first, it appears that figuring out what the cross-NOR SR flip-flop does given only two input voltages is impossible, since the NOR gates’ inputs depend on the outputs, and what are the outputs anyway? (For now, pretend that Q and 
are not complements but separate variables; you could call them X and Y if you like.) Well, first of all, you know that a NOR gate will output a high (logic 1) only if both inputs are low (logic 0). From this, you can deduce that if S = 1 and R = 0, Q must be 1 and must be 0, regardless of the outputs. This is called the set condition. Likewise, by similar argument, we can deduce that if S = 0 and R = 1, Q must be 0 and must be 1. This is called the reset condition.
are not complements but separate variables; you could call them X and Y if you like.) Well, first of all, you know that a NOR gate will output a high (logic 1) only if both inputs are low (logic 0). From this, you can deduce that if S = 1 and R = 0, Q must be 1 and must be 0, regardless of the outputs. This is called the set condition. Likewise, by similar argument, we can deduce that if S = 0 and R = 1, Q must be 0 and must be 1. This is called the reset condition.
FIGURE 12.70
But now, what about R = 0 and S = 0? Can you predict the outputs given only input levels? No! It is impossible to predict the outputs because the outputs are essential for predicting the outputs—it is a “catch-22.” However, if you know the states of the outputs beforehand, you can figure things out. For example, if you first set the flip-flop (S = 1, R = 0, Q = 1, = 0), and then apply S = 0, R = 0, the flip-flop would remain set (upper gate: S = 0, Q = 1 → =0; lower gate: R = 0, = 0 → Q = 1). Likewise, if you start out in reset mode (S = 0, R = 1, Q = 0, Q =0), and then apply S = 0, R = 0, the flip-flop remains in reset mode (upper gate: S = 0, Q = 0 → = 1; lower gate: R = 0, =1 → Q = 0). In other words, the flip-flop remembers, or latches onto, the previous output state even when both inputs go low (0). This is referred to as the hold condition.
= 0), and then apply S = 0, R = 0, the flip-flop would remain set (upper gate: S = 0, Q = 1 → =0; lower gate: R = 0, = 0 → Q = 1). Likewise, if you start out in reset mode (S = 0, R = 1, Q = 0, Q =0), and then apply S = 0, R = 0, the flip-flop remains in reset mode (upper gate: S = 0, Q = 0 → = 1; lower gate: R = 0, =1 → Q = 0). In other words, the flip-flop remembers, or latches onto, the previous output state even when both inputs go low (0). This is referred to as the hold condition.The last choice you have is S = 1, R = 1. Here, it is easy to predict what will happen because you know that as long as there is at least one high (1) applied to the input to the NOR gate, the output will always be 0. Therefore, Q = 0 and = 0. Now, there are two fundamental problems with the S = 1, R = 1 state. First, why would you want to set and reset at the same time? Second, when you return to the hold condition from S = 1, R = 1, you get an unpredictable result, unless you know which input returned low last. Why? When the inputs are brought back to the hold position (R = 0, S = 0, Q = 0, = 0), both NOR gates will want to be 1 (they want to be held). But let’s say one of the NOR gate’s outputs changes to 1 a fraction of a second before the other. In this case, the slower flip-flop will not output a 1 as planned, but will instead output 0. This is a classic example of a race condition, where the slower gate loses. But which flip-flop is the slower one? This unstable, unpredictable state cannot be avoided and is simply not used.
= 0. Now, there are two fundamental problems with the S = 1, R = 1 state. First, why would you want to set and reset at the same time? Second, when you return to the hold condition from S = 1, R = 1, you get an unpredictable result, unless you know which input returned low last. Why? When the inputs are brought back to the hold position (R = 0, S = 0, Q = 0, = 0), both NOR gates will want to be 1 (they want to be held). But let’s say one of the NOR gate’s outputs changes to 1 a fraction of a second before the other. In this case, the slower flip-flop will not output a 1 as planned, but will instead output 0. This is a classic example of a race condition, where the slower gate loses. But which flip-flop is the slower one? This unstable, unpredictable state cannot be avoided and is simply not used.The cross-NAND SR flip-flop provides the same basic function as the NOR SR flip-flop, but there is a fundamental difference: its hold and indeterminate states are reversed. This occurs because, unlike the NOR gate, which outputs a low only when both its inputs are the same, the NAND gate outputs a high only when both its inputs are the same. This means that the hold condition for the cross-NAND SR flip-flop is S = 1, R = 1, while the indeterminate condition is S = 0, R = 0.
Now let’s look at two simple applications for SR flip-flops.
Switch Debouncer
Say you want to use the far-left switch/pullup resistor circuit (see Fig. 12.71) to drive an AND gate’s input high or low (the other input is fixed high). When the switch is open, the AND gate should receive a high. When the switch is closed, the gate should receive a low. That’s what should happen, but that’s not what actually happens. Why? Because of switch bounce.
FIGURE 12.71
When a switch is closed, the metal contacts bounce a number of times before coming to rest due to inherent springlike characteristics of the contacts. Though the bouncing typically lasts no more than 50 ms, the results can lead to unwanted false triggering, as shown in the far left circuit in Fig. 12.71.
A simple way to get rid of switch bounce is to use the switch debouncer circuit, shown at center of Fig. 12.71. This circuit uses an SR flip-flop to store the initial switch contact voltage while ignoring all trailing bounces. In this circuit, when the switch is thrown from the B to A position, the flip-flop is set. As the switch bounces alternately high and low, the Q output remains high, because when the switch contact bounces away from A, the S input receives a low (R is low, too), but that’s just a hold condition; the output stays the same. The same debouncing feature occurs when the switch is thrown from position A to B.
Latched Temperature or Light Alarm
The simple circuit in Fig. 12.71 uses an SR flip-flop to sound a buzzer alarm when the temperature (when using a thermistor) or the light intensity (when using a photoresistor) reaches a critical level. When the temperature or light increases, the resistance of the thermistor or photoresistor decreases, and the R input voltage goes down. When the R input voltage goes below the high threshold level of the NAND gate, the flip-flop is set, and the alarm is sounded. The alarm will continue to sound until the RESET switch is pressed and the temperature or light level has gone below the critical triggering level. The pot is used to adjust this level.
Level-Triggered SR Flip-Flop (the Beginning of Clocked Flip-Flops)
Now it would be nice to make an SR flip-flop synchronous; that is, make the S and R inputs either enabled or disabled by a control pulse, such as a clock. Only when the clock pulse arrives are the inputs sampled. Flip-flops that respond in this manner are referred to as synchronous or clocked flip-flops (as opposed to the preceding asynchronous flip-flops).
To make the preceding SR flip-flop into a synchronous or clocked device, simply attach enable gates to the inputs of the flip-flop, as shown in Fig. 12.72. The figure shows the cross-NAND arrangement, but a cross-NOR arrangement also can be used. In this setup, only when the clock is high are the S and R inputs enabled. When the clock is low, the inputs are disabled, and the flip-flop is placed in hold mode. The truth table and timing diagram in Fig. 12.72 help illustrate how this device works.
FIGURE 12.72
The level-triggered SR flip-flop has an annoying feature: its S and R inputs must be held at the desired input condition (set, reset, or no change) for the entire time that the clock signal is enabling the flip-flop. With a slight alteration, however, you can make the level-triggered flip-flop more flexible (in terms of timing control) by turning it into an edge-triggered flip-flop.
An edge-triggered flip-flop samples the inputs only during either a positive or negative clock edge (↑ = positive edge, ↓ = negative edge). Any changes that occur before or after the clock edge are ignored—the flip-flop will be placed in hold mode.
To make an edge-triggered flip-flop, introduce either a positive or a negative level-triggered clock pulse generator network into the previous level-triggered flip-flop, as shown in Fig. 12.73.
FIGURE 12.73
In a positive edge-triggered generator circuit, a NOT gate with a propagation delay is added. Since the clock signal is delayed through the inverter, the output of the AND gate will not provide a low (as would be the case without a propagation delay), but will provide a pulse that begins at the positive edge of the clock signal and lasts for a duration equal to the propagation delay of the NOT gate. It is this pulse that is used to clock the flip-flop.
Within the negative edge-triggered generator network, the clock signal is first inverted and then applied through the same NOT/AND network. The pulse begins at the negative edge of the clock and lasts for a duration equal to the propagation delay of the NOT gate. The propagation delay is typically so small (in nanoseconds) that the pulse is essentially an “edge.”
Pulse-Triggered SR Flip-Flops
A pulse-triggered SR flip-flop is a level-clocked flip-flop; however, for any change in output to occur, both the high and low levels of the clock must rise and fall. Pulse-triggered flip-flops are also called master-slave flip-flops; the master accepts the initial inputs and then “whips” the slave with its output when the negative clock edge arrives. Another analogy often used is to say that during the positive edge, the master gets cocked (like a gun), and during the negative clock edge, the slave gets triggered. Figure 12.74 shows a simplified pulse-triggered cross-NAND SR flip-flop.
FIGURE 12.74
The master is simply a clocked SR flip-flop that is enabled during the high clock pulse and outputs Y and 
(set, reset, or no change). The slave is similar to the master, but it is enabled only during the negative clock pulse (due to the inverter). The moment the slave is enabled, it uses the Y and outputs of the master as inputs, and then outputs the final result.
(set, reset, or no change). The slave is similar to the master, but it is enabled only during the negative clock pulse (due to the inverter). The moment the slave is enabled, it uses the Y and outputs of the master as inputs, and then outputs the final result.Notice the preset (
) and clear (
) inputs. These are called asynchronous inputs. Unlike the synchronous inputs, S and R, the asynchronous inputs disregard the clock and either clear (also called asynchronous reset) or preset (also called asynchronous set) the flip-flop. When - is high and is low, you get asynchronous reset, Q = 1, = 0, regardless of the CLK, S, and R inputs. These active-low inputs are therefore normally pulled high to make them inactive. The ability to apply asynchronous set and resets is often used to clear entire registers that consist of an array of flip-flops.
) and clear () inputs. These are called asynchronous inputs. Unlike the synchronous inputs, S and R, the asynchronous inputs disregard the clock and either clear (also called asynchronous reset) or preset (also called asynchronous set) the flip-flop. When - is high and is low, you get asynchronous reset, Q = 1, = 0, regardless of the CLK, S, and R inputs. These active-low inputs are therefore normally pulled high to make them inactive. The ability to apply asynchronous set and resets is often used to clear entire registers that consist of an array of flip-flops.General Rules for Deciphering Flip-Flop Logic Symbols
Typically, you do not need to worry about constructing flip-flops from scratch. Instead, you buy flip-flop ICs, as discussed in the next section. Likewise, you do not need to worry about complex logic gate schematics. Instead, you use symbolic representations like the ones shown in Fig. 12.75. Although the symbols in the figure apply to SR flip-flops, the basic rules that are outlined can be applied to the D and JK flip-flops, which are discussed in the following sections.
FIGURE 12.75
12.6.2 SR Flip-Flop ICs
Figure 12.76 shows a few sample SR flip-flop (latch) ICs. The 74LS279A contains four independent SR latches (note that two of the latches have an EXTRA SET INPUT). This IC is commonly used in switch debouncers.
FIGURE 12.76
The 4043 contains four three-state cross-coupled NOR SR latches. Each latch has individual set and reset inputs, as well as separate Q outputs. The three-state feature is an extra bonus, which allows you to effectively disconnect all Q outputs, making it appear that the outputs are open circuits (high impedance, or high Z). This three-state feature is often used in applications where a number of devices must share a common data bus. When the output data from one latch is applied to the bus, the outputs of other latches (or other devices) are disconnected via the high-Z condition. The 4044 is similar to the 4043 but contains four three-state cross-coupled NAND RS latches.
12.6.3 D-Type Flip-Flops
A D-type flip-flop (data flip-flop) is a single input device. It is basically an SR flip-flop, where S is replaced with D and R is replaced with (inverted D). The inverted input is tapped from the D input through an inverter to the R input, as shown in Fig. 12.77. The inverter ensures that the indeterminate condition (race, or not used state, S = 1, R = 1) never occurs. At the same time, the inverter eliminates the hold condition so that you are left with only set (D = 1) and reset (D = 0) conditions. The circuit in Fig. 12.77 represents a level-triggered D-type flip-flop.
(inverted D). The inverted input is tapped from the D input through an inverter to the R input, as shown in Fig. 12.77. The inverter ensures that the indeterminate condition (race, or not used state, S = 1, R = 1) never occurs. At the same time, the inverter eliminates the hold condition so that you are left with only set (D = 1) and reset (D = 0) conditions. The circuit in Fig. 12.77 represents a level-triggered D-type flip-flop.
FIGURE 12.77
To create a clocked D-type level-triggered flip-flop, first start with the clocked level-triggered SR flip-flop and throw in the inverter, as shown in Fig. 12.78.
FIGURE 12.78
To create a clocked, edge-triggered, D-type flip-flop, take a clocked edge-triggered SR flip-flop and add an inverter, as shown in Fig. 12.79.
FIGURE 12.79
Figure 12.80 shows a popular edge-triggered D-type flip-flop IC, the 7474 (for example, the 74HC74). It contains two D-type positive edge-triggered flip-flops with asynchronous preset and clear inputs.
FIGURE 12.80
Note the lowercase letters l and h in the truth table in this figure. The h is similar to the H for a high voltage level, and the l is similar to the L for low voltage level; however, there is an additional condition that must be met for the flip-flop’s output to do what the truth table indicates. The additional condition is that the D input must be fixed high (or low) in duration for at least one setup time (ts) before the positive clock edge. This condition stems from the real-life propagation delays present in flip-flop ICs. If you try to make the flip-flop switch states too fast (do not give it time to move electrons around), you can end up with inaccurate output readings. For the 7474, the setup time is 20 ns. Therefore, when using this IC, you must not apply input pulses that are within the 20-ns limit. Other flip-flops will have different setup times, so you will need to check the manufacturer’s data sheets. I will discuss setup time and some other flip-flop timing parameters in greater detail in Section 12.6.6.
D-type flip-flops are sometimes found in the pulse-triggered (master-slave) variety. Recall that a pulse-triggered flip-flop requires a complete clock pulse before the outputs will reflect what is applied at the input(s) (in this case, the D input). Figure 12.81 shows the basic structure of a pulse-triggered D flip-flop. It is almost exactly like the pulse-triggered SR flip-flop, except for the inverter addition to the master’s input.
FIGURE 12.81
Now let’s look at a few simple D-type flip-flop applications.
In the stop-go indicator circuit, a simple level-triggered D-type flip-flop is used to turn on a red LED when its D input is low (reset) and turn on a green LED when the D input is high (set). Only one LED can be turned on at a time.
The divide-by-two counter uses a positive edge-triggered D-type flip-flop to divide an applied signal’s frequency by two. The explanation of how this works is simple: The positive edge-triggered feature does not care about negative edges. You can figure out the rest.
External Asynchronous Control Signal
A synchronizer is used when you want to use an external asynchronous control signal (perhaps generated by a switch or other input device) to control some action within a synchronous system. The synchronizer provides a means of keeping the phase of the action generated by the control signal in synch with the phase of the synchronous system.
For example, say you want an asynchronous control signal to control the number of clock pulses that get from point A to point B within a synchronous system. You might try using a simple enable gate, as shown below the synchronizer circuit in Fig. 12.82. However, because the external control signal is not synchronous (in phase) with the clock, when you apply the external control signal, you may shorten the first or last output pulse, as shown in the lower timing diagram.
FIGURE 12.82
Certain applications do not like shortened clock pulses and will not function properly. To avoid shortened pulses, throw in an edge-triggered D-type flip-flop to create a synchronizer. The flip-flop’s CLK input is tapped off the input clock line, its D input receives the external control signal, and its Q output is connected to the AND gate’s enable input. With this arrangement, there will never be shortened clock pulses because the Q output of the flip-flop will not supply enable pulses to the AND gate that are out of phase with the input clock signal. This is due to the fact that after the flip-flop’s CLK input receives a positive clock edge, the flip-flop ignores any input changes applied to the D input until the next positive clock edge.
12.6.4 Quad and Octal D Flip-Flops
Most frequently, you will find a number of D flip-flops or D latches grouped together within a single IC. For example, the 74HC75, shown in Fig. 12.83, contains four transparent D latches. Latches 0 and 1 share a common active-low enable E0 – E1, while latches 2 and 3 share a common active-low enable E2 – E3. From the function table, each Q output follows each D input as long as the corresponding enable line is high. When the enable line goes low, the Q output will become latched to the value that D was one setup time prior to the high-to-low enable transition. The 4042 is another quad D-type latch, which works as described in Fig. 12.83. D-type latches are commonly used as data registers in bus-oriented systems, as is also explained in the figure.
FIGURE 12.83
D flip-flops also come in octal form—eight flip-flops per IC. These devices are frequently used as 8-bit data registers within microprocessor systems, where devices share 8-bit or 2 × 8 = 16-bit data or address buses. An example of an octal D-type flip-flop is the 74HCT273 shown in Fig. 12.84. All D flip-flops within the 74HCT273 share a common positive edge-triggered clock input and a common active-low clear input. When the clock input receives a positive edge, data bits applied to D0 through D7 are stored in the eight flip-flops and appear at the outputs Q0 through Q7. To clear all flip-flops, the clear input is pulsed low. I will talk more about octal flip-flops and other bus-oriented devices in Section 12.9.
FIGURE 12.84
Finally, we come to the last of the flip-flops: the JK flip-flop. A JK flip-flop resembles an SR flip-flop, where J acts like S and K acts like R. Likewise, it has a set mode (J = 1, K = 0), a reset mode (J = 0, K = 1), and a hold mode (J = 0, K = 0). However, unlike the SR flip-flop, which has an indeterminate mode when S = 1, R = 1, the JK flip-flop has a toggle mode when J = 1, K = 1. Toggle means that the Q and outputs switch to their opposite states at each active clock edge.
outputs switch to their opposite states at each active clock edge.To make a JK flip-flop, modify the SR flip-flop’s internal logic circuit to include two cross-coupled feedback lines between the output and input. This modification, however, means that the JK flip-flop cannot be level-triggered; it can only be edge-triggered or pulse-triggered. Figure 12.85 shows how you can create edge-triggered flip-flops based on the cross-NAND SR edge-triggered flip-flop.
FIGURE 12.85
Edge-triggered JK flip-flops also come with preset (asynchronous set) and clear (asynchronous reset) inputs, as shown in Fig. 12.86.
FIGURE 12.86
There are pulse-triggered (master-slave) flip-flops, too. These devices are similar to the pulse-triggered SR flip-flops with the exception of the distinctive JK cross-coupled feedback connections from the slave’s Q and outputs back to the master’s input gates. Figure 12.87 shows a simple NAND pulse-triggered JK flip-flop.
outputs back to the master’s input gates. Figure 12.87 shows a simple NAND pulse-triggered JK flip-flop.
FIGURE 12.87
The pulse-triggered flip-flops are not as popular as the edge-triggered JK flip-flops because of an undesired effect that can occur. Pulse-triggered JK flip-flops occasionally experience what is called ones-catching. In ones-catching, unwanted pulses or glitches caused by electrostatic noise appear on J and K while the clock is high. The flip-flop remembers these glitches and interprets them as true data. Ones-catching normally is not a problem when clock pulses are of short duration; it is when the pulses get long that you must watch out. To avoid ones-catching altogether, stick with edge-triggered JK flip-flops.
Two major applications for JK flip-flops are found within counter and shift register circuits. Here, I will introduce a counter application. I will discuss shift registers in Section 12.8 and additional counter circuits in Section 12.7.
A simple counter, called a MOD-16 ripple counter (or asynchronous counter), can be constructed by joining four JK flop-flops together, as shown in Fig. 12.89. (MOD-16, or modulus 16, means that the counter has 16 binary states.) This means that it can count from 0 to 15—the 0 is one of the counts.
FIGURE 12.88
Each flip-flop in the ripple counter is fixed in toggle mode (J and K are both held high). The clock signal applied to the first flip-flop causes the flip-flop to divide the clock signal’s frequency by 2 at its Q0 output—a result of the toggle. The second flip-flop receives Q0’s output at its clock input and likewise divides by 2. The process continues down the line. What you get in the end is a binary counter with four digits. The LSB is Q0, while the MSB is Q3. When the count reaches 1111, the counter recycles back to 0000 and continues from there. To reset the counter at any given time, the active-low clear line is pulsed low. To make the counter count backward from 1111 to 0000, you would simply use the 
outputs.
outputs.FIGURE 12.89
The ripple counter in Fig. 12.89 also can be used as a divide-by-2, -4, -8, or -16 counter. Here, you simply replace the clock signal with any desired input signal that you wish to divide in frequency. To get a divide-by-2 counter, you only need the first flip-flop; to get a divide-by-8 counter, you need the first three flip-flops.
Ripple counters with higher MOD values can be constructed by slapping on more flip-flops to the MOD-16 counter. But how do you create a ripple counter with a MOD value other than 2, 4, 8, 16, and so on? For example, say you want to create a MOD-10 (0 to 9) ripple counter. And what do you do if you want to stop the counter after a particular count has been reached and then trigger some device, such as an LED or buzzer? Figure 12.90 shows just such a circuit.
To make a MOD-10 counter, you simply start with the MOD-16 counter and connect the Q0 and Q3 outputs to a NAND gate. When the counter reaches 9 (1001), Q0 and Q3 will both go high, causing the NAND gate’s output to go low. The NAND gate then sinks current, turning the LED on, while at the same time disabling the clock-enable gate and stopping the count. (When the NAND gate is high, there is no potential difference across the LED to light it up.) To start a new count, the active-low clear line is momentarily pulsed low. Now, to make a MOD-15 counter, you would apply the same basic approach used to the left, but you would connect Q1, Q2, and Q3 to a three-input NAND gate.
FIGURE 12.90
Synchronous Counter
There is a problem with the ripple counter just discussed. The output stages of the flip-flops further down the line (from the first clocked flip-flop) take time to respond to changes that occur due to the initial clock signal. This is a result of the internal propagation delay that occurs within a given flip-flop. A standard TTL flip-flop may have an internal propagation delay of 30 ns. If you join four flip-flops to create a MOD-16 counter, the accumulative propagation delay at the highest-order output will be 120 ns. When used in high-precision synchronous systems, such large delays can lead to timing problems.
To avoid large delays, you can create what is called a synchronous counter. Synchronous counters, unlike ripple (asynchronous) counters, contain flip-flops whose clock inputs are driven at the same time by a common clock line. This means that output transitions for each flip-flop will occur at the same time.
With this approach, unlike with the ripple counter, you must use some additional logic circuitry placed between various flip-flop inputs and outputs to give the desired count waveform. For example, to create a 4-bit MOD-16 synchronous counter requires adding two additional AND gates, as shown in Fig. 12.91. The AND gates act to keep a flip-flop in hold mode (if both inputs of the gate are low) or toggle mode (if both inputs of the gate are high), as follows:
FIGURE 12.91
• During the 0–1 count, the first flip-flop is in toggle mode (and always is); all the rest are in hold mode.
• When it is time for the 2–4 count, the first and second flip-flops are placed in toggle mode; the last two are held in hold mode.
• When it is time for the 4–8 count, the first AND gate is enabled, allowing the third flip-flop to toggle.
• When it is time for the 8–15 count, the second AND gate is enabled, allowing the last flip-flop to toggle.
You can work out the details for yourself by studying the circuit and timing waveforms.
The ripple (asynchronous) and synchronous counters discussed so far are simple but hardly ever used. In practice, if you need a counter—ripple or synchronous—you purchase a counter IC. These ICs are often MOD-16 or MOD-10 counters and usually come with many additional features. For example, many ICs allow you to preset the count to a desired number via parallel input lines. Others allow you to count up or to count down by means of control inputs. Counter ICs are discussed in Section 12.7.
12.6.6 Practical Timing Considerations with Flip-Flops
When working with flip-flops, it is important to avoid race conditions. For example, a typical race condition would occur if, say, you were to apply an active clock edge at the very moment you apply a high or low pulse to one of the inputs of a JK flip-flop. Since the JK flip-flop uses what is present on the inputs at the moment the clock edge arrives, having a high-to-low input change will cause problems because you cannot determine if the input is high or low at that moment—it is a straight line.
To avoid this type of race condition, you must hold the inputs of the flip-flop high or low for at least one setup time ts before the active clock transition. If the input changes during the ts to the clock edge region, the output levels will be unreliable.
To determine the setup time for a given flip-flop, you must look through the manufacturer’s data sheets. For example, the minimum setup time for the 74LS76 JK flip-flop is 20 ns. Other timing parameters, such as hold time and propagation delay, are also given by the manufacturers. A description of what these parameters mean is given in Fig. 12.92.
Setup time ts: The time that the input must be held before the active clock edge for proper operation. For a typical flip-flop, ts is around 20 ns.
Hold time th: The time that the input must be held after the active clock edge for proper operation. For most flip-flops, this is 0 ns—meaning inputs need not be held beyond the active clock signal.
TPLH: Propagation delay from clock trigger point to the low-to-high Q output swing. A typical TPLH for a flip-flop is around 20 ns.
TPHL: Propagation delay from clock trigger point to the high-to-low Q output swing. A typical TPLH for a flip-flop is around 20 ns.
fmax: Maximum frequency allowed at the clock input. Any frequency above this limit will result in unreliable performance. This can vary greatly.
tW(L): Clock pulse width (low), the minimum width (in nanoseconds) that is allowed at the clock input during the low level for reliable operation.
tW(H): Clock pulse width (high), the minimum width (in nanoseconds) that is allowed at the clock input during the high level for reliable operation.
Preset or clear pulse width: Also given by tW(L), the minimum width (in nanoseconds) of the low pulse at the preset or clear inputs.
FIGURE 12.92
12.6.7 Digital Clock Generators and Single-Pulse Generators
You have already seen the importance of clock and single-pulse control signals. Now let’s take a look at some circuits that can generate these signals.
Clocks (Astable Multivibrators)
A clock is simply a squarewave oscillator. Chapter 10 discusses ways to generate squarewaves, so you can refer there to learn the theory. Here, I will simply present some practical circuits. Digital clocks can be constructed from discrete components such as logic gates, capacitors, resistors, and crystals, or can be purchased in IC form. Figure 12.93 shows some sample clock generators.
Figure a. Here, two CMOS inverters are connected together to form an RC relaxation oscillator with squarewave output. The output frequency is determined by the RC time constant, as shown in the figure.
Figure b. The previous oscillator has one problem: it may not oscillate if the transition regions of its two gates differ, or it may oscillate at a slightly lower frequency than the equation predicts due to the finite gain of the leftmost gate. The oscillator shown here resolves these problems by adding hysteresis via the additional RC network.
Figure c. This oscillator uses a pair of CMOS NAND gates and RC timing network along with a pot to set the frequency. A squarewave output is generated with a maximum frequency of around 2 MHz. The enable lead could be connected to the other input of the first gate, but here it is brought out to be used as a clock enable input (the clock is enabled when this lead is high).
Figure d. Here, a TTL SR flip-flop with dual feedback resistors uses an RC relaxation-type configuration to generate a squarewave. The frequency of the clock is determined by the R and C values, as shown in the figure. Changing the C1-to-C2 ratio changes the duty cycle.
Figure e. When high stability is required, a crystal oscillator is the best choice for a clock generator. Here, a pair of CMOS inverters and a feedback crystal are used (see Chapter 9 for details). The frequency of operation is determined by the crystal (such as 2 MHz or 10 MHz). Adjustment of the pot may be needed to start oscillations.
Figure f. A 555 timer in astable mode can be used to generate squarewaves. Here, we slap on a JK flip-flop that is in toggle mode to provide a means of keeping the low and high times the same, as well as providing clock-enable control. The timing diagram and the equations provided within the figure paint the rest of the picture.
Figure g. The 74S124 dual voltage-controlled oscillator (VCO) outputs squarewaves at a frequency that is dependent on the value of an external capacitor and the voltage levels applied its frequency-range input (VRNG) and its frequency control input (Vfreq). The graph in this figure shows how the frequency changes with capacitance, while VRNG and Vfreq are fixed at 2 V. This device also comes with active-low enable input. Other VCOs that are designed for clock generation include the 74LS624, 4024, and 4046 PLL (Phase Locked Loop). You will find many more listed in the catalogs.
FIGURE 12.93
Monostables (One-Shots)
To generate single-pulse signals of a desired width, you can use a discrete device called a monostable multivibrator, or one-shot for short. A one-shot has only one stable state, high (or low), and can be triggered into its unstable state, low (or high), for a duration of time set by an RC network. One-shots can be constructed from simple gates, capacitors, and resistors. These circuits, however, tend to be “finicky” and simply are not worth talking about. If you want a one-shot, you can buy a one-shot IC, which typically costs around 50 cents.
Two popular one-shots, shown in Fig. 12.94, are the 74121 nonretriggerable monostable multivibrator and the 74123 retriggerable monostable multivibrator.
The 74121 has three trigger inputs (1, 2, B), true and complemented outputs (Q,), and timing inputs to which an RC network is attached (Rext/Cext, Cext). To trigger a pulse from the 74123, you can choose between five possible trigger combinations, as shown in the truth table in the figure. Bringing the input trigger in on B, however, is attractive when dealing with slowly rising or noisy signals, since the signal is directly applied to an internal Schmitt-triggered inverter (recall hystersis). To set the desired output pulse width (tw), a resistor/capacitor combination is connected to the Rext/Cext and Cext inputs, as shown. (An internal 2-k resistor is provided, which can be used alone by connecting pin 9 to VCC and placing the capacitor across pins 10 and 11, or which can be used in series with an external resistor attached to pin 9. Here, the internal resistor will not be used.) To determine which values to give to the external resistor and capacitor, use the formula given by the manufacturer, which is shown to the left. The maximum tw should not exceed 28 s (R = 40 k, C = 1000 μF) for reliable operation. Also, note that with a nonretriggerable one-shot like the 74121, any trigger pulses applied when the device is already in its astable state will be ignored.
1, 2, B), true and complemented outputs (Q,), and timing inputs to which an RC network is attached (Rext/Cext, Cext). To trigger a pulse from the 74123, you can choose between five possible trigger combinations, as shown in the truth table in the figure. Bringing the input trigger in on B, however, is attractive when dealing with slowly rising or noisy signals, since the signal is directly applied to an internal Schmitt-triggered inverter (recall hystersis). To set the desired output pulse width (tw), a resistor/capacitor combination is connected to the Rext/Cext and Cext inputs, as shown. (An internal 2-k resistor is provided, which can be used alone by connecting pin 9 to VCC and placing the capacitor across pins 10 and 11, or which can be used in series with an external resistor attached to pin 9. Here, the internal resistor will not be used.) To determine which values to give to the external resistor and capacitor, use the formula given by the manufacturer, which is shown to the left. The maximum tw should not exceed 28 s (R = 40 k, C = 1000 μF) for reliable operation. Also, note that with a nonretriggerable one-shot like the 74121, any trigger pulses applied when the device is already in its astable state will be ignored.
The 74123 is a dual, retriggerable one-shot. Unlike nonretriggerable one-shots, this device will not ignore trigger pulses that are applied during the astable state. Instead, when a new trigger pulse arrives during an astable state, the astable state will continue to be astable for a time of tw. In other words, the device is simply retriggered. The 74123 has two trigger inputs (,B) and a clear input (CLR). When CLR is low, the one-shot is forced back into its stable state (Q = low). To determine tw, use the formula given to the left, provided Cext > 1000 pF. If Cext < 1000 pF, use tw/Cext/Rext graphs provided by the manufacturer to find tw.
,B) and a clear input (CLR). When CLR is low, the one-shot is forced back into its stable state (Q = low). To determine tw, use the formula given to the left, provided Cext > 1000 pF. If Cext < 1000 pF, use tw/Cext/Rext graphs provided by the manufacturer to find tw.FIGURE 12.94
Note that a 555 timer IC can also be used as a monostable and is a lower-cost device.
Besides acting as simple pulse generators, one-shots can be combined to make time-delay generators and timing and sequencing circuits (see Fig. 12.95).
FIGURE 12.95
If you do not have a one-shot IC like the 74121, you can use a 555 timer (discussed in Chapter 9) wired in its monostable configuration, as shown in Fig. 12.96.
FIGURE 12.96
One-Shot/Continuous-Clock Generator
The circuit shown in Fig. 12.97 is a handy one-shot/continuous clock generator that is useful when you start experimenting with logic circuits.
In this circuit, switch S2 is used to select whether a single-step or a continuous-clock input is to be presented to the output. When S2 is in the single-step position, the cross-NAND SR flip-flop (switch debouncer) is set (Q = 1, = 0). This disables NAND gate B while enabling NAND gate A, which will allow a single pulse from the one-shot to pass through gate C to the output. To trigger the one-shot, press switch S1. When S2 is thrown to the continuous position, the switch debouncer is reset (Q = 0, = 1). This disables NAND gate A and enables NAND gate B, allowing the clock signal generated by the 555/flip-flop to pass through gate C and to the output. (Just as a note to avoid confusion, you need gate C to prevent the output from being low and high at the same time.)
= 0). This disables NAND gate B while enabling NAND gate A, which will allow a single pulse from the one-shot to pass through gate C to the output. To trigger the one-shot, press switch S1. When S2 is thrown to the continuous position, the switch debouncer is reset (Q = 0, = 1). This disables NAND gate A and enables NAND gate B, allowing the clock signal generated by the 555/flip-flop to pass through gate C and to the output. (Just as a note to avoid confusion, you need gate C to prevent the output from being low and high at the same time.)FIGURE 12.97
In sequential circuits, it is usually a good idea to clear (reset) devices when power is first applied. This ensures that devices, such as flip-flops and other sequential ICs, do not start out in a weird mode (for example, counter IC does not start counting at, say, 1101 instead of 0000). Figures 12.98 and 12.99 show some techniques used to provide automatic power-up clearing.
FIGURE 12.98
Let’s pretend that one of the devices in a circuit has a JK flip-flop that needs clearing during power-up. In order to clear the flip-flop and then quickly return it to synchronous operations, you would like to apply a low (0) voltage to its active-low clear input; afterward, you would like the voltage to go high (at least above 2.0 V for a 74LS76 JK flip-flop). A simple way to implement this function is to use an RC network like the one shown in the figure. When the power is off (switch open), the capacitor is uncharged (0 V). This means that the 
line is low (0 V). Once the power is turned on (switch closed), the capacitor begins charging up toward VCC (+5 V). However, until the capacitor’s voltage reaches 2.0 V, the line is considered low to the active-low clear input. After a duration of t = RC, the capacitor’s voltage will have reached 63 percent of VCC, or 3.15 V; after a duration of t = 5RC, its voltage will be nearly equal to +5 V. Since the 74LS76’s input requires at least 2.0 V to be placed back into synchronous operations, you know that t = RC is long enough. Thus, by rough estimate, if you want the line to remain low for 1 μs after power-up, you must set RC = 1 μs. Setting R = 1 k and C = 0.001 μF does the trick.
line is low (0 V). Once the power is turned on (switch closed), the capacitor begins charging up toward VCC (+5 V). However, until the capacitor’s voltage reaches 2.0 V, the line is considered low to the active-low clear input. After a duration of t = RC, the capacitor’s voltage will have reached 63 percent of VCC, or 3.15 V; after a duration of t = 5RC, its voltage will be nearly equal to +5 V. Since the 74LS76’s input requires at least 2.0 V to be placed back into synchronous operations, you know that t = RC is long enough. Thus, by rough estimate, if you want the line to remain low for 1 μs after power-up, you must set RC = 1 μs. Setting R = 1 k and C = 0.001 μF does the trick.This automatic resetting scheme can be used within circuits that contain a number of resettable ICs. If an IC requires an active-high reset (not common), simply throw in an inverter and create an active-high clear line, as shown in the figure. Depending on the device being reset, the length of time that the clear line is at a low will be about 1 μs. As more devices are placed on the clear line, the low time duration will decrease due to the additional charging paths. To prevent this from occurring, a larger capacitor can be used.
An improved automatic power-up clear circuit is shown in Fig. 12.99. Here a Schmitt-triggered inverter is used to make the clear signal switch off cleanly. With CMOS Schmitt-triggered inverters, a diode and input resistor (R2) are necessary to protect the CMOS IC when power is removed.
FIGURE 12.99
12.6.9 More on Switch Debouncers
The switch debouncer shown to the far left in Fig. 12.100 should look familiar. It is simply a cross-NAND SR-latch-type switch debouncer. This example uses a 74LS279A IC that contains four SR latches—an ideal choice when you need a number of switch debouncers.
FIGURE 12.100
A switch debouncer does not need to be constructed from an SR latch. In fact, most any old flip-flop with preset and clear (reset) inputs can be used. For example, the middle circuit in Fig. 12.100 uses a 74LS74 D-type flip-flop, along with pullup resistor, as a switch debouncer. The D input and CLK input are tied to ground so that the only two modes that can be enacted are the preset and clear modes. Also, the pullup resistors will always make either the preset input or clear input high, regardless of whether the switch is bouncing. From these two facts, you can figure out the rest for yourself, using the truth table for the 74HC74 in Fig. 12.80 as a guide.
Another approach that can be used to debounce an SPST switch is shown on the far right in Fig. 12.100. This debouncer uses a Schmitt-triggered inverter along with a unique RC timing network. When the switch is open, the capacitor is fully charged (+5 V), and the output is low. When the switch is closed, the capacitor discharges rapidly to ground through the 100-Ω resistor, causing the output to go high. Now, as the switch bounces, the capacitor will repeatedly attempt to charge slowly back to +5 V via the 10-k resistor, and then again will discharge rapidly to zero through the 100-W resistor, making the output high. By making the 10-k pullup resistor larger than the 100-Ω discharge resistor, the voltage across the capacitor or the voltage applied to the inverter’s input will not get a chance to exceed the positive threshold voltage () of the inverter during a bounce. Therefore, the output remains high, regardless of the bouncing switch. In this example, the charge-up time constant (R2C = 10 k × 0.1 μF) ensures sufficient leeway. When the switch is reopened, the capacitor charges up toward +5 V. When the capacitor’s voltage reaches , the output switches low.
) of the inverter during a bounce. Therefore, the output remains high, regardless of the bouncing switch. In this example, the charge-up time constant (R2C = 10 k × 0.1 μF) ensures sufficient leeway. When the switch is reopened, the capacitor charges up toward +5 V. When the capacitor’s voltage reaches , the output switches low.12.6.10 Pullup and Pulldown Resistors
As you learned when dealing with the switch debouncer circuits, a pullup resistor is used to keep an input high that would otherwise float if left unconnected. If you want to set the “pulled up” input low, you can ground the pin, say, via a switch.
It is important to get an idea of the size of pullup resistor to use. The key here is to make the resistor value small enough so that the voltage drop across it does not weigh down the input voltage below the minimum high threshold voltage (VIH,min) of the IC. At the same time, you do not want to make it too small; otherwise, when you ground the pin, excessive current will be dissipated.
In the left diagram in Fig. 12.100, a 10-k pullup resistor is used to keep a 74LS device’s input high. To make the input low, close the switch. To figure out if the resistor is large enough so as not to weigh down the input, use Vin = +5 V − RIIH, where IIH is the current drawn into the IC during the high input state, when the switch is open. For a typical 74LS device, IIH is around 20 μA. Thus, by applying the simple formula, you find that Vin= 4.80 V, which is well above the VIH,min level for a 74LS device. Now, if you close the switch to force the input low, the power dissipated through the resistor (PD = V2/R) will be (5 V)2/10 k = 25 mW. The graph shown in Fig. 12.101 provides Vin versus R and PD versus R curves. As you can see, if R becomes too large, Vin drops below the VIH,min level, and the output will not go high as planned. As R gets smaller, the power dissipation skyrockets. To determine what value of R to use for a specific logic IC, you look up the VIH,min and IIH,max values within the data sheets and apply the simple formulas. In most applications, a 10-k pullup resistor will work fine.
FIGURE 12.101
You will run into situations where a pulldown resistor is used to keep a floating terminal low. Unlike a pullup resistor, the pulldown resistor must be smaller because the input low current IIL (sourced by IC) is usually much larger than IIH. Typically, a pulldown resistor is around 100 to 1 kΩ. A lower resistance ensures that Vin is low enough to be interpreted as a low by the logic input. To determine if Vin is low enough, use Vin = 0 V + IILR. As an example, use a 74LS device with an IIL = 400 μA and a 500-Ω pulldown resistor. When the switch is open, the input will be 0.20 V—well below the VIL,max level for the 74LS (~0.8 V). When the switch is closed, the power dissipated by the resistor will be (5 V)2/500 Ω = 50 mW. The graph shown in Fig. 12.101 provides Vin versus R and PD versus R curves. As you can see by the curves, if R becomes too large, Vin surpasses VIL,max, and the output will not be low as planned. As R gets small, the power dissipation skyrockets. If you need to use a pulldown resistor/switch arrangement, be wary of the high power dissipation through the resistor when the switch is closed.
12.7 Counter ICs
In Section 12.6.5, you saw how flip-flops could be combined to make both asynchronous (ripple) and synchronous counters. In practice, using discrete flip-flops is to be avoided. Instead, use a prefabricated counter IC. These ICs cost a dollar or two and come with many additional features, like control enable inputs, parallel loading, and so on. A number of different kinds of counter ICs are available. They come in either synchronous (ripple) or asynchronous forms and are usually designed to count in binary or binary-coded decimal (BCD).
12.7.1 Asynchronous Counter (Ripple Counter) ICs
Asynchronous counters work fine for many noncritical applications, but for high-frequency applications that require precise timing, synchronous counters work better. Recall that unlike an asynchronous counter, a synchronous counter contains flip-flops that are clocked at the same time, and hence the synchronous counter does not accumulate nearly as many propagation delays as is the case with the asynchronous counter. Let’s look at a few asynchronous counter ICs you will find in the electronics catalogs.
7493 4-Bit Ripple Counter with Separate MOD-2 and MOD-8 Counter Sections
The 7493’s internal structure consists of four JK flip-flops connected to provide separate MOD-2 (0-to-1 counter) and MOD-8 (0-to-7 counter) sections. Both the MOD-2 and MOD-8 sections are clocked by separate clock inputs. The MOD-2 section uses Cp0 as its clock input, while the MOD-8 section uses Cp1 as its clock input. Likewise, the two sections have separate outputs: MOD-2’s output is Q0, while MOD-8’s outputs consist of Q1, Q2, and Q3. The MOD-2 section can be used as a divide-by-2 counter. The MOD-8 section can be used as a divide-by-2 counter (output tapped at Q1), a divide-by-4 counter (output tapped at Q2), or a divide-by-8 counter (output tapped at Q3). If you want to create a MOD-16 counter, simply join the MOD-2 and MOD-8 sections by wiring Q0 to Cp1, while using Cp0 as the single clock input.
The MOD-2, MOD-8, or the MOD-16 counter can be cleared by making both AND-gated master reset inputs (MR1 and MR2) high. To begin a count, one or both of the master reset inputs must be made low. When the negative edge of a clock pulse arrives, the count advances one step. After the maximum count is reached (1 for MOD-2, 111 for MOD-8, or 1111 for MOD-16), the outputs jump back to zero, and a new count begins.
7490 4-Bit Ripple Counter with MOD-2 and MOD-5 Counter Sections
The 7490, like the 7493, is another 4-bit ripple counter. However, its flip-flops are internally connected to provide MOD-2 (count-to-2) and MOD-5 (count-to-5) counter sections. Again, each section uses a separate clock: Cp0 for MOD-2 and Cp1 for MOD-5. By connecting Q0 to Cp1 and using Cp0 as the single clock input, a MOD-10 counter (decade or BCD counter) can be created.
When master reset inputs MR1 and MR2 are set high, the counter’s outputs are reset to 0—provided that master set inputs MS1 and MS2 are not both high (the MS inputs override the MR inputs). When MS1 and MS2 are high, the outputs are set to Q0 = 1, Q1 = 0, Q2 = 0, and Q3 = 1. In the MOD-10 configuration, this means that the counter is set to 9 (binary 1001). This master set feature comes in handy if you wish to start a count at 0000 after the first clock transition occurs (with master reset, the count starts out at 0001).
FIGURE 12.102
FIGURE 12.103
7492 Divide-by-12 Ripple Counter with MOD-2 and MOD-6 Counter Sections
The 7492 is another 4-bit ripple counter that is similar to the 7490. However, it has a MOD-2 and a MOD-6 section, with corresponding clock inputs Cp0 (MOD-2) and Cp1 (MOD-8). By joining Q0 to Cp1, you get a MOD-12 counter, where Cp0 acts as the single clock input. To clear the counter, high levels are applied to master reset inputs MR1 and MR2.
FIGURE 12.104
Like the asynchronous counter ICs, synchronous counter ICs come in various MOD arrangements. These devices usually come with extra goodies, such as controls for up or down counting and parallel load inputs used to preset the counter to a desired start count. Synchronous counter ICs are more popular than the asynchronous ICs, not only because of these additional features, but also because they do not have such long propagation delays as asynchronous counters. Let’s take a look at a few popular IC synchronous counters.
74193 Presettable 4-Bit (MOD-16) Synchronous Up/Down Counter
The 74193 is a versatile 4-bit synchronous counter that can count up or count down and can be preset to any count desired—at least a number between 0 and 15. There are two separate clock inputs: CpU is used to count up, and CpD is used to count down. One of these clock inputs must be held high in order for the other input to count. The binary output count is taken from Q0 (20), Q1 (21), Q2 (22), and Q3 (23).
To preset the counter to any desired count, a corresponding binary number is applied to the parallel inputs D0 to D3. When the parallel load input (
) is pulsed low, the binary number is loaded into the counter, and the count, either up or down, will start from that number. The terminal count up (
) and terminal count down (
) outputs are normally high. The output is used to indicate when the maximum count has been reached and the counter is about to recycle to the minimum count (0000)—the carry condition. Specifically, this means that goes low when the count reaches 15 (1111) and the input clock (CpU) goes from high to low. remains low until CpU returns high. This low pulse at can be used as an input to the next high-order stage of a multistage counter. The terminal count down () output is used to indicate that the minimum count has been reached (0000) and the counter is about to recycle to the maximum count 15 (1111)—the borrow condition. Specifically, this means that goes low when the down count reaches 0000 and the input clock (CpD) goes low. Figure 12.105 provides a truth table for the 74193, along with a sample load, up-count, and down-count sequence.
) is pulsed low, the binary number is loaded into the counter, and the count, either up or down, will start from that number. The terminal count up () and terminal count down () outputs are normally high. The output is used to indicate when the maximum count has been reached and the counter is about to recycle to the minimum count (0000)—the carry condition. Specifically, this means that goes low when the count reaches 15 (1111) and the input clock (CpU) goes from high to low. remains low until CpU returns high. This low pulse at can be used as an input to the next high-order stage of a multistage counter. The terminal count down () output is used to indicate that the minimum count has been reached (0000) and the counter is about to recycle to the maximum count 15 (1111)—the borrow condition. Specifically, this means that goes low when the down count reaches 0000 and the input clock (CpD) goes low. Figure 12.105 provides a truth table for the 74193, along with a sample load, up-count, and down-count sequence.
FIGURE 12.105
74192 Presettable Decade (BCD or MOD-10) Synchronous Up/Down Counter
The 74192, shown in Fig. 12.106, is essentially the same device as the 74193, except it counts up from 0 to 9 and repeats or counts down from 9 to 0 and repeats. When counting up, the terminal count up (
) output goes low to indicate when the maximum count is reached (9 or 1001) and the CpU clock input goes from high to low. remains low until CpU returns high. When counting down, the terminal count down output (
) goes low when the minimum count is reached (0 or 0000) and the input clock CpD goes low. The truth table and example load, count-up, and count-down sequence provided in Fig. 12.106 explain how the 74192 works in greater detail.
) output goes low to indicate when the maximum count is reached (9 or 1001) and the CpU clock input goes from high to low. remains low until CpU returns high. When counting down, the terminal count down output () goes low when the minimum count is reached (0 or 0000) and the input clock CpD goes low. The truth table and example load, count-up, and count-down sequence provided in Fig. 12.106 explain how the 74192 works in greater detail.
FIGURE 12.106
74190 Presettable Decade (BCD or MOD-10) and 74191 Presettable 4-Bit (MOD-16) Synchronous Up/Down Counters
The 74190 and the 74191 do basically the same things as the 74192 and 74193, but the input and output pins, as well as the operating modes, are a bit different. (The 74190 and the 74191 have the same pinouts and operating modes; the only difference is the maximum count.) Like the previous synchronous counters, these counters can be preset to any count by using the parallel load () operation. However, unlike the previous synchronous counters, to count up or down requires using a single input: 
/D. When /D is set low, the counter counts up; when /D is high, the counter counts down.
) operation. However, unlike the previous synchronous counters, to count up or down requires using a single input: /D. When /D is set low, the counter counts up; when /D is high, the counter counts down.A clock enable input (
) acts to enable or disable the counter. When is low, the counter is enabled. When is high, counting stops, and the current count is held fixed at the Q0 to Q3 outputs.
) acts to enable or disable the counter. When is low, the counter is enabled. When is high, counting stops, and the current count is held fixed at the Q0 to Q3 outputs.Unlike the previous synchronous counters, the 74190 and the 74191 use a single terminal count output (TC) to indicate when the maximum or minimum count has occurred and the counter is about to recycle. In count-down mode, TC is normally low but goes high when the counter reaches zero (for both the 74190 and 74191). In count-up mode, TC is normally low but goes high when the counter reaches 9 (for the 74190) or reaches 15 (for the 74191).
The ripple-clock output (
) follows the input clock (CP) whenever TC is high. This means, for example, that in count-down mode, when the count reaches zero, will go low when CP goes low. The output can be used as a clock input to the next higher stage of a multistage counter. This, however, leads to a multistage counter that is not truly synchronous because of the small propagation delay from CP to of each counter. To make a multistage counter that is truly synchronous, you must tie each IC’s clock to a common clock input line. You use the TC output to inhibit each successive stage from counting until the previous stage is at its terminal count. Figure 12.107 shows various asynchronous (ripple-like) and synchronous multistage counters built from 74191 ICs.
) follows the input clock (CP) whenever TC is high. This means, for example, that in count-down mode, when the count reaches zero, will go low when CP goes low. The output can be used as a clock input to the next higher stage of a multistage counter. This, however, leads to a multistage counter that is not truly synchronous because of the small propagation delay from CP to of each counter. To make a multistage counter that is truly synchronous, you must tie each IC’s clock to a common clock input line. You use the TC output to inhibit each successive stage from counting until the previous stage is at its terminal count. Figure 12.107 shows various asynchronous (ripple-like) and synchronous multistage counters built from 74191 ICs.
FIGURE 12.107
Presettable 4-Bit (MOD-16) Synchronous Up/Down Counter
The 74160 and 74163 resemble the 74190 and 74191 but require no external gates when used in multistage counter configurations. Instead, you simply cascade counter ICs together, as shown in Fig. 12.109.
FIGURE 12.109
For both devices, a count can be preset by applying the desired count to the D0 to D3 inputs and then applying a low to the parallel enable input (
) ; the input number is loaded into the counter on the next low-to-high clock transition. The master reset (
) is used to force all Q output low, regardless of the other input signals. The two clock enable inputs (CEP and CET) must be high for counting to begin. The terminal count output (TC) is forced high when the maximum count is reached, but will be forced low if CET goes low. This is an important feature that makes the multistage configuration synchronous, while avoiding the need for external gating. The truth tables along with the example load, count-up, and count-down timing sequences in Figs. 12.108 and 12.109 should help you better understand how these two devices work.
) ; the input number is loaded into the counter on the next low-to-high clock transition. The master reset () is used to force all Q output low, regardless of the other input signals. The two clock enable inputs (CEP and CET) must be high for counting to begin. The terminal count output (TC) is forced high when the maximum count is reached, but will be forced low if CET goes low. This is an important feature that makes the multistage configuration synchronous, while avoiding the need for external gating. The truth tables along with the example load, count-up, and count-down timing sequences in Figs. 12.108 and 12.109 should help you better understand how these two devices work.
FIGURE 12.108
12.7.3 A Note on Counters with Displays
If you want to build a fairly sophisticated counter that can display many digits, the previous techniques are not worth pursuing, because there are simply too many discrete components to work with (for example, a separate seven-segment decoder/driver for each digit). A common alternative approach is to use a microcontroller that functions both as a counter and a display driver.
What microcontrollers can do that discrete circuits have a hard time achieving is multiplex a display. In a multiplexed system, corresponding segments of each digit of a multidigit display are linked together, while the common lines for each digit are brought out separately. You can see that the number of lines is significantly reduced; a nonmultiplexed 7-segment 4-digit display has 28 segment lines and 4 common lines, while the 4-digit multiplexed display has only 7 + 4, or 11, lines.
The trick to multiplexing involves flashing each digit, one after the other (and recycling), in a fast enough manner to make it appear that the display is continuously lit. In order to multiplex, the microcontroller’s program must supply the correct data to the segment lines at the same time that it enables a given digit via a control signal sent to the common lead of that digit. I will talk about multiplexing in greater detail in Chapter 13.
Another approach used to create multidigit counters is to use a multidigit counter/display driver IC. One such IC is the ICM7217, a four-digit LED display programmable up/down counter made by Intersil. This device is typically used in hardwired applications where thumbwheel switches are used to load data and SPDT switches are used to control the chip. The ICM7217A provides multiplexed seven-segment LED display outputs that are used to drive common cathode displays.
This simple clock-pulse generator provides a unique way to generate 60-, 10-, and 1-Hz clock signals that can be used in applications that require real-time counting. The basic idea is to take the characteristic 60-Hz ac line voltage (from the wall socket) and convert it into a lower-voltage squarewave of the same frequency. (Note that countries other than the United States typically use 50 Hz instead of 60 Hz. For 50 Hz operation, use an appropriate transformer and replace the divide-by-6 counter with the divide-by-5 counter shown in the upper left of Fig. 12.109.) First, the ac line voltage is stepped down to 12.6 V by the transformer. The negative-going portion of the 12.6-V ac voltage is removed by the zener diode (which acts as a half-wave rectifier). At the same time, the zener diode clips the positive-going signal to a level equal to its reverse breakdown voltage (3.9 V). This prevents the Schmitt-triggered inverter from receiving an input level that exceeds its maximum input rating. The Schmitt-triggered inverter takes the rectified/chipped sine wave and converts it into a true squarewave. The Schmitt trigger’s output goes low (~0.2 V) when the input voltage exceeds its positive threshold voltage (~1.7 V) and goes high (~3.4 V) when its input falls below its negative threshold voltage (~0.9 V). From the inverter’s output, you get a 60-Hz squarewave (or a clock signal beating out 60 pulses per second). To get a 10-Hz clock signal, you slap on a divide-by-6 counter. To get a 1-Hz signal, you slap a divide-by-10 counter onto the output of the divide-by-6 counter.
(~1.7 V) and goes high (~3.4 V) when its input falls below its negative threshold voltage (~0.9 V). From the inverter’s output, you get a 60-Hz squarewave (or a clock signal beating out 60 pulses per second). To get a 10-Hz clock signal, you slap on a divide-by-6 counter. To get a 1-Hz signal, you slap a divide-by-10 counter onto the output of the divide-by-6 counter.FIGURE 12.110
In the circuit shown here, three 74LS90 MOD-10 counter ICs are used to create a three-digit (decimal) counter. Features to note include an auto-reset RC network that acts to reset counters during power-up via the master reset inputs. Before the count begins, the D flip-flop’s output is held high, disabling the clock from reaching the first counter’s clock input. When the push button switch is closed, the flip-flop’s output goes low, enabling the first counter to count. The BCD outputs of each counter are fed through separate BCD-to-seven-segment decoder/driver ICs, which in turn drive the LED displays. The far-left counter’s output represents the count’s LSB, while the far-right counter’s output represents the count’s MSB. As shown, the last counter’s output is wired so that when a count of 600 is reached, an AND gate is enabled, causing the three-input OR gate to disable the clock (stop count) while also triggering a relay. To reset the counter, the manual reset switch is momentarily closed.
output is held high, disabling the clock from reaching the first counter’s clock input. When the push button switch is closed, the flip-flop’s output goes low, enabling the first counter to count. The BCD outputs of each counter are fed through separate BCD-to-seven-segment decoder/driver ICs, which in turn drive the LED displays. The far-left counter’s output represents the count’s LSB, while the far-right counter’s output represents the count’s MSB. As shown, the last counter’s output is wired so that when a count of 600 is reached, an AND gate is enabled, causing the three-input OR gate to disable the clock (stop count) while also triggering a relay. To reset the counter, the manual reset switch is momentarily closed.FIGURE 12.111
Synchronous counter applications
FIGURE 12.112
FIGURE 12.113
A simple application of the ICM7217A is a four-digit unit counter shown in Fig. 12.114. If you are interested in knowing all the specifics of how this counter works, along with learning about other applications for this device, check out Maxim’s data sheets at http://www.maxim-ic.com/datasheet/index.mvp/id/1501. It is better to learn from the maker in this case. Also, take a look at the other counter/display driver ICs Maxim has to offer. Other manufacturers produce similar devices, so visit their websites as well.
FIGURE 12.114
12.8 Shift Registers
Data words traveling through a digital system frequently must be temporarily held, copied, and bit-shifted to the left or to the right. A device that can be used for such applications is the shift register. A shift register is constructed from a row of flip-flops connected so that digital data can be shifted down the row either in a left or right direction. Most shift registers can handle parallel movement of data bits as well as serial movement, and also can be used to convert from parallel to serial or from serial to parallel. Figure 12.115 shows several types of shift register arrangements: serial-in/serial-out, parallel-in/serial-out, and serial-in/parallel out.
FIGURE 12.115
12.8.1 Serial-In/Serial-Out Shift Registers
Figure 12.116 shows a simple 4-bit serial-in/serial-out shift register made from D flip-flops. Serial data is applied to the D input of flip-flop 0. When the clock line receives a positive clock edge, the serial data is shifted to the right from flip-flop 0 to flip-flop 1. Whatever bits of data were present at flip-flop 2’s, 3’s, and 4’s outputs are shifted to the right during the same clock pulse. To store a 4-bit word into this register requires four clock pulses. The rightmost circuit shows how you can rewire the flip-flops to make a shift-left register. To make larger bit-shift registers, more flip-flops are added (for example, an 8-bit shift register would require eight flip-flops cascaded together).
FIGURE 12.116
12.8.2 Serial-In/Parallel-Out Shift Registers
Figure 12.117 shows a 4-bit serial-in/parallel-out shift register constructed from D flip-flops. This circuit is essentially the same as the previous serial-in/serial-out shift register, except now you attach parallel output lines to the outputs of each flip-flop as shown. Note that this shift register circuit also comes with an active-low clear input () and a strobe input that acts as a clock enable control. The timing diagram in the figure shows a sample serial-to-parallel shifting sequence.
) and a strobe input that acts as a clock enable control. The timing diagram in the figure shows a sample serial-to-parallel shifting sequence.
FIGURE 12.117
12.8.3 Parallel-In/Serial-Out Shift Registers
Constructing a 4-bit parallel-to-serial shift register from D flip-flops requires some additional control logic, as shown in the circuit in Fig. 12.118. Parallel data must first be loaded into the D inputs of all four flip-flops. To load data, the SHIFT/
is made low. This enables the AND gates with X marks, allowing the 4-bit parallel input word to enter the D0–D3 inputs of the flip-flops. When strobe and CLK are both high, the 4-bit parallel word is latched simultaneously into the four flip-flops and appears at the Q0–Q3 outputs. To shift the latched data out through the serial output, the SHIFT/ line is made high. This enables all unmarked AND gates, allowing the latched data bit at the Q output of a flip-flop to pass (shift) to the D input of the flip-flop to the right. In this shift mode, four clock pulses are required to shift the parallel word out of the serial output.
is made low. This enables the AND gates with X marks, allowing the 4-bit parallel input word to enter the D0–D3 inputs of the flip-flops. When strobe and CLK are both high, the 4-bit parallel word is latched simultaneously into the four flip-flops and appears at the Q0–Q3 outputs. To shift the latched data out through the serial output, the SHIFT/ line is made high. This enables all unmarked AND gates, allowing the latched data bit at the Q output of a flip-flop to pass (shift) to the D input of the flip-flop to the right. In this shift mode, four clock pulses are required to shift the parallel word out of the serial output.
FIGURE 12.118
12.8.4 Ring Counter (Shift Register Sequencer)
The ring counter (shift register sequencer) is a unique type of shift register that incorporates feedback from the output of the last flip-flop to the input of the first flip-flop. Figure 12.119 shows a 4-bit ring counter made from D-type flip-flops. In this circuit, when the 
input is set low, Q0 is forced high by the active-low preset, while Q1, Q2, and Q3 are forced low (cleared) by the active-low clear. This causes the binary word 1000 to be stored within the register. When the line is brought low, the data bits stored in the flip-flops are shifted right with each positive clock edge. The data bit from the last flip-flop is sent to the D input of the first flip-flop. The shifting cycle will continue to recirculate while the clock is applied. To start a fresh cycle, the line is momentarily brought low.
input is set low, Q0 is forced high by the active-low preset, while Q1, Q2, and Q3 are forced low (cleared) by the active-low clear. This causes the binary word 1000 to be stored within the register. When the line is brought low, the data bits stored in the flip-flops are shifted right with each positive clock edge. The data bit from the last flip-flop is sent to the D input of the first flip-flop. The shifting cycle will continue to recirculate while the clock is applied. To start a fresh cycle, the line is momentarily brought low.
FIGURE 12.119
The Johnson shift counter is similar to the ring counter except that its last flip-flop feeds data back to the first flip-flop from its inverted output (). For this reason, this type is sometimes called a Moebius counter, as the bit sequence will be shifted out first “normally,” then inverted, then normally, and so on. In the simple 4-bit Johnson shift counter shown in Fig. 12.120, you start out by applying a low to the line, which sets presets Q0 high; Q1, Q2, and Q3 low; and 3 high. In other words, you load the register with the binary word 1000, as you did with the ring counter.
). For this reason, this type is sometimes called a Moebius counter, as the bit sequence will be shifted out first “normally,” then inverted, then normally, and so on. In the simple 4-bit Johnson shift counter shown in Fig. 12.120, you start out by applying a low to the line, which sets presets Q0 high; Q1, Q2, and Q3 low; and 3 high. In other words, you load the register with the binary word 1000, as you did with the ring counter.
FIGURE 12.120
Now, when you bring the line low, data will shift through the register. However, unlike the ring counter, the first bit sent back to the D0 input of the first flip-flop will be high because feedback is from 3 not Q3. At the next clock edge, another high is fed back to D0; at the next clock edge, another high is fed back; at the next edge, another high is fed back. Only after the fourth clock edge does a low get fed back (the 1 has shifted down to the last flip-flop and 3 goes high). At this point, the shift register is full of 1s.
line low, data will shift through the register. However, unlike the ring counter, the first bit sent back to the D0 input of the first flip-flop will be high because feedback is from 3 not Q3. At the next clock edge, another high is fed back to D0; at the next clock edge, another high is fed back; at the next edge, another high is fed back. Only after the fourth clock edge does a low get fed back (the 1 has shifted down to the last flip-flop and 3 goes high). At this point, the shift register is full of 1s.As more clock pulses arrive, the feedback loop supplies lows to D0 for the next four clock pulses. After that, the Q outputs of all the flip-flops are low, while 3 goes high. This high from 3 is fed back to 
0 during the next positive clock edge, and the cycle repeats.
3 goes high. This high from 3 is fed back to 0 during the next positive clock edge, and the cycle repeats.As you can see, the 4-bit Johnson shift counter has eight output stages (which require eight clock pulses to recycle), not four, as is the case with the ring counter.
12.8.6 Shift Register ICs
Now that we have covered the basic theory of shift registers, let’s take a look at practical shift register ICs that contain all the necessary logic circuitry inside.
The 7491A is an 8-bit serial-in/serial-out shift register that consists of eight internally linked SR flip-flops. This device has positive edge-triggered inputs and a pair of data inputs (A and B) that are internally ANDed together, as shown in the logic diagram in Fig. 12.121. This type of data input means that for a binary 1 to be shifted into the register, both data inputs must be high. For a binary 0 to be shifted into the register, either input can be low. Data is shifted to the right at each positive clock edge.
FIGURE 12.121
74164 8-Bit Serial-In/Parallel-Out Shift Register IC
The 74164 is an 8-bit serial-in/parallel-out shift register. It contains eight internally linked flip-flops and has two serial inputs, Dsa and Dsb, which are ANDed together. Like the 7491A, the unused serial input acts as an enable/disable control for the other serial input. For example, if you use Dsa as the serial input, you must keep Dsb high to allow data to enter the register, or you can keep it low to prevent data from entering the register.
Data bits are shifted one position to the right at each positive clock edge. The first data bit entered will end up at the Q7 parallel output after the eighth clock pulse. The master reset () resets all internal flip-flops and forces the Q outputs low when it is pulsed low.
) resets all internal flip-flops and forces the Q outputs low when it is pulsed low.In the sample circuit shown in Fig. 12.122, a serial binary number 10011010 (15410) is converted into its parallel counterpart. Note the AND gate and strobe input used in this circuit. The strobe input acts as a clock enable input; when it is set high, the clock is enabled. The timing diagram paints the rest of the picture.
FIGURE 12.122
The 75165 is a unique 8-bit device that can act as either a serial-to-serial shift register or as a parallel-to-serial shift register. When used as a parallel-to-serial shift register, parallel data is applied to the D0–D7 inputs and then loaded into the register when the parallel load input (
) is pulsed low. To begin shifting the loaded data out of the serial output Q7 (or 7 if you want inverted bits), the clock enable input () must be set low to allow the clock signal to reach the clock inputs of the internal D-type flip-flops. When used as a serial-to-serial shift register, serial data is applied to the serial data input DS. A sample shift, load, and inhibit timing sequence is shown in Fig. 12.123.
) is pulsed low. To begin shifting the loaded data out of the serial output Q7 (or 7 if you want inverted bits), the clock enable input () must be set low to allow the clock signal to reach the clock inputs of the internal D-type flip-flops. When used as a serial-to-serial shift register, serial data is applied to the serial data input DS. A sample shift, load, and inhibit timing sequence is shown in Fig. 12.123.
FIGURE 12.123
74194 Universal Shift Register IC
Figure 12.124 shows the 74194 4-bit bidirectional universal shift register. This device can accept either serial or parallel inputs, provide serial or parallel outputs, and shift left or right based on input signals applied to select controls S0 and S1. Serial data can be entered into either the serial shift-right input (DSR) or the serial shift-left input (DSL). Select controls S0 and S1 are used to initiate a hold (S0 = low, S1 = low), shift left (S0 = low, S1 = high), shift-right (S0 = high, S1 = low), or to parallel load (S0 = high, S1 = high) mode. A clock pulse must then be applied to shift or parallel load the data.
FIGURE 12.124
In parallel load mode (S0 and S1 are high), parallel input data is entered via the D0 through D3 inputs and transferred to the Q0 to Q3 outputs following the next low-to-high clock transition. The 74194 also has an asynchronous master reset () input that forces all Q outputs low when pulsed low. To make a shift-right recirculating register, the Q3 output is wired back to the DSR input, while making S0 = high and S1 = low. To make a shift-left recirculating register, the Q0 output is connected back to the DSL input, while making S0 = low and S1 = high. The timing diagram in Fig. 12.124 shows a typical parallel load and shifting sequence.
) input that forces all Q outputs low when pulsed low. To make a shift-right recirculating register, the Q3 output is wired back to the DSR input, while making S0 = high and S1 = low. To make a shift-left recirculating register, the Q0 output is connected back to the DSL input, while making S0 = low and S1 = high. The timing diagram in Fig. 12.124 shows a typical parallel load and shifting sequence.74299 8-Bit Universal Shift/Storage Register with Three-State Interface
A number of shift registers have three-state outputs—outputs that can assume a high, low, or high impedance state (open-circuit or float state). These devices are commonly used as storage registers in three-state bus interface applications.
An example 8-bit universal shift/storage register with three-state outputs is the 74299, shown in Fig. 12.125. This device has four synchronous operating modes that are selected via two select inputs, S0 and S1. Like the 74194 universal shift register, the 74299’s select modes include shifting right, shifting left, holding, and parallel loading (see the function table in Fig. 12.125). The mode-select inputs, serial data inputs (DS0 and DS7), and parallel-data inputs (I/O0 through I/O7) are positive edge triggered. The master reset (
) input is an asynchronous active-low input that clears the register when pulsed low.
) input is an asynchronous active-low input that clears the register when pulsed low.
FIGURE 12.125
The three-state bidirectional I/O port has three modes of operation:
• The read-register mode allows data within the register to be available at the I/O outputs. This mode is selected by making both output-enable inputs (
1 and 2) low and making one or both select inputs low.
1 and 2) low and making one or both select inputs low.• The load-register mode sets up the register for a parallel load during the next low-to-high clock transition. This mode is selected by setting both select inputs high.
• The disable-I/O mode acts to disable the outputs (set to a high impedance state) when a high is applied to one or both of the output-enable inputs. This effectively isolates the register from the bus to which it is attached.
16-Bit Serial-to-Parallel Converter
A simple way to create a 16-bit serial-to-parallel converter is to join two 74164 8-bit serial-in/parallel-out shift registers, as shown in Fig. 12.126. To join the two ICs, simply wire the Q7 output from the first register to one of the serial inputs of the second register. (Recall that the serial input that is not used for serial input data acts as an active-high enable control for the other serial input.)
FIGURE 12.126
In terms of operation, when data is shifted out of Q7 of the first register (or data output D7), it enters the serial input of the second (the example uses DSa as the serial input) and will be presented to the Q0 output of the second register (or data output D8). For an input data bit to reach the Q7 output of the second register (or data output D15), 16 clock pulses must be applied.
8-Bit Serial-to-Parallel Converter with Simultaneous Data Transfer
Figure 12.127 shows a circuit that acts as a serial-to-parallel converter that outputs the converted 8-bit word only when all 8 bits have been entered into the register. Here, a 74164 8-bit serial-in/parallel-out shift register is used, along with a 74HCT273 octal D-type flip-flop and a divide-by-8 counter. At each positive clock edge, the serial data is loaded into the 74164. After eight clock pulses, the first serial bit entered is shifted down to the 74164’s Q7 output, while the last serial bit entered resides at the 74164’s Q0 output. At the negative edge of the eighth clock pulse, the negative-edge triggered divide-by-8 circuit’s output goes high. During this high transition, the data present on the inputs of the 74HCT273 (which hold the same data present at the 74164’s Q outputs) is passed to the 74HCT273’s outputs at the same time. (Think of the 74HCT273 as a temporary storage register that dumps its contents after every eighth clock pulse.)
FIGURE 12.127
8-Bit Parallel-to-Serial Interface
Figure 12.128 shows a 74165 8-bit parallel-to-serial shift register used to accept a parallel ASCII word and convert it into a serial ASCII word that can be sent to a serial device. Recall that ASCII codes are only 7 bits long (for example, the binary code for & is 010 0110). How do you account for the missing bit? As it turns out, most 8-bit devices communicating via serial ASCII will use an additional eighth bit for a special purpose, perhaps to act as a parity bit or as a special function bit to enact a special set of characters. Often, the extra bit is simply set low and ignored by the serial device receiving it.
FIGURE 12.128
To keep things simple, let’s set the extra bit low and assume that is how the serial device likes things done. This means that you will set the D0 input of the 74165 low. The MSB of the ASCII code will be applied to the D1 input, while the LSB of the ASCII code will be applied to the D7 input. Now, with the parallel ASCII word applied to the inputs of the register, when you pulse the parallel load line () low, the ASCII word, along with the “ignored bit,” is loaded into the register. Next, you must enable the clock to allow the loaded data to be shifted out serially, by setting the clock enable input () low for the duration it takes for the clock pulses to shift out the parallel word. After the eighth clock pulse (0 to 7), the serial device will have received all 8 serial data bits. Practically speaking, a microprocessor or microcontroller is necessary to provide the and lines with the necessary control signals to ensure that the register and serial device communicate properly.
) low, the ASCII word, along with the “ignored bit,” is loaded into the register. Next, you must enable the clock to allow the loaded data to be shifted out serially, by setting the clock enable input () low for the duration it takes for the clock pulses to shift out the parallel word. After the eighth clock pulse (0 to 7), the serial device will have received all 8 serial data bits. Practically speaking, a microprocessor or microcontroller is necessary to provide the and lines with the necessary control signals to ensure that the register and serial device communicate properly.Recirculating Memory Registers
A recirculating memory register is a shift register that is preloaded with a binary word that is serially recirculated through the register via a feedback connection from the output to the input. Recirculating registers can be used for a number of applications, from supplying a specific repetitive waveform used to drive IC inputs to driving output drivers used to control stepper motors.
In the leftmost circuit in Fig. 12.129, a parallel 4-bit binary word is applied to the D0 to D3 inputs of a 74194 universal shift register. When the S1 select input is brought high (switch opened), the 4-bit word is loaded into the register. When the S1 input is then brought low (switch closed), the 4-bit word is shifted in a serial fashion through the register, out Q3, and back to Q0 via the DSR input (serial shift-right input) as positive clock edges arrive. Here, the shift register is loaded with 0111. As you begin shifting the bits through the register, a single low output will propagate down through high outputs, which in turn causes the LED attached to the corresponding low output to turn on. In other words, you have made a simple Christmas tree flasher.
FIGURE 12.129
The rightmost circuit in Fig. 12.129 is basically the same thing as the leftmost circuit. However, now the circuit is used to drive a stepper motor. Typically, a stepper motor has four stator coils that must be energized in sequence to make the motor turn at a given angle. For example, to make a simple stepper motor turn clockwise, you must energize its stator coils 1, 2, 3, and 4 in the following sequence: 1000, 0100, 0010, 0001, 1000, and so on. To make the motor go counterclockwise, apply the following sequence: 1000, 0001, 0010, 0100, 1000, and so on. You can generate these simple firing sequences with the 74194 by parallel loading the D0 to D3 inputs with the binary word 1000. To output the clockwise firing sequence, simply shift bits to the right by setting S0 = high and S1 = low. As clock pulses arrive, the 1000 present at the outputs will then become 0100, then 0010, 0001, 1000, and so on.
The speed of rotation of the motor is determined by the clock frequency. To output the counterclockwise firing sequence, simply shift bits to the left by setting S0 = low and S1 = high. To drive steppers, it is typically necessary to use a buffer/driver interface like the 7407 shown in Fig. 12.129, as well a number of output transistors, not shown. Also, different types of stepper motors may require different firing sequences than the one shown here. Stepper motors and the various circuits used to drive them are discussed in detail in Chapter 14.
12.9 Three-State Buffers, Latches, and Transceivers
Digital systems that use microprocessors require that a number of different devices (such as RAM, ROM, and I/O devices) share a common bus of some sort. For simple microprocessor systems, the data bus is often 8 bits wide (eight separate conductors). In order for devices to share the bus, only one device can be transmitting data at a time. The microprocessor decides which devices get access to the bus and which devices do not. In order for the microprocessor to control the flow of data, it may need help from an external register-type device. This device accepts a control signal issued by the microprocessor and responds by either allowing or disallowing parallel data to pass. Three popular devices used for such applications are the octal three-state buffer, octal latch/flip-flop, and transceiver.
12.9.1 Three-State Octal Buffers
When enabled, a three-state octal buffer passes data present on its eight inputs to its outputs unchanged. When disabled, input data is prevented from reaching the outputs—the outputs are placed in a high-impedance state. This high-impedance state makes data bus sharing between various devices possible. The octal buffer also can provide the additional sink or source current required to drive output devices.
Three popular three-state octal buffers are shown in Fig. 12.130: the 74xx240 is a three-state inverting octal buffer, the 74xx241 is a three-state Schmitt-triggered inverting octal buffer, and the 74244 is a conventional three-state octal buffer. The enable/disable control for all three devices is the same. To enable all eight outputs (allow data to pass from I inputs to Y outputs), both output enable inputs, a and a, must be set low. If you wish to enable only four outputs, make one output enable high while setting the other low (refer to the ICs in Fig. 12.130 to see which output enable controls which group of inverters). To disable all eight outputs, both output enables are set high. To disable only four outputs, set only one output enable input high.
a and a, must be set low. If you wish to enable only four outputs, make one output enable high while setting the other low (refer to the ICs in Fig. 12.130 to see which output enable controls which group of inverters). To disable all eight outputs, both output enables are set high. To disable only four outputs, set only one output enable input high.
FIGURE 12.130
Figure 12.131 shows an example of how three-state inverting octal buffers can be used in an 8-bit microprocessor system. The upper buffer links one bus to a common data bus. The two lower buffers are used to link input devices to the common data bus. With programming and the help of an additional control bus, the microprocessor can select which buffer is enabled and which buffers are disabled.
Data from an input device or another bus passes to the data bus only when the corresponding octal buffer is enabled (input enables made low). Only one input device or bus is allowed to pass data to the data bus at a time. Here, input device 1 is the only device allowed to pass data to the data bus because its enable inputs are set low. Note that data is inverted when passed through the inverting octal buffer.
FIGURE 12.131
A three-state octal latch or octal flip-flop, unlike a three-state octal buffer, has the ability to hold onto data present at its data inputs before transmitting the data to its outputs. In microprocessor applications, where a number of devices share a common data bus, this memory feature is handy because it allows the processor to store data, go onto other operations that require the data bus, and come back to the stored data if necessary. This feature also allows output devices to sample held bus data at leisure while the current state of the data bus is changing. To understand how three-state octal latches and flip-flops work, let’s first consider the 74xx373 three-state octal latch and the 74xx374 three-state octal flip-flop shown in Fig. 12.132.
FIGURE 12.132
The 74xx373 octal latch contains eight D-type “transparent” latches. When its enable input (E) is high, the outputs (Q0–Q7) follow the inputs (D0–D7). When E is low, data present at the inputs is loaded into the latch. To place the output in a high-impedance state, the output enable () input is set high.
) input is set high.Figure 12.133 shows a simple bus-oriented system that uses two 74HC373s to communicate with an input device and output device. Again, as with the octal buffers, control signals are typically supplied by a microprocessor.
FIGURE 12.133
The 74xx374 octal flip-flop comes with eight edge-triggered flip-flops. Unlike the octal latch, the 74xx374’s outputs are not transparent—they do not follow the inputs. Instead, a positive clock edge at clock input CP must be applied to load the device before data is presented at the Q outputs. To place the output in a high-impedance state, is set high. Figure 12.134 shows a simple bus-oriented system that uses two 74HC374s to communicate with two output devices.
is set high. Figure 12.134 shows a simple bus-oriented system that uses two 74HC374s to communicate with two output devices.
FIGURE 12.134
12.9.3 Transceivers
Another method for connecting devices that share a common bus is to use a transceiver. Unlike the three-state octal buffer, octal latch, and octal flip-flop, the transceiver is a bidirectional device. This means that when used in a bus-oriented system, external devices can read or write from the data bus. Figure 12.135 shows the 74xx245 octal transceiver, along with a sample application. In the application circuit, a 74LS245 is used as a bidirectional interface between two data buses. To send data from bus A to bus B, the 74LS245’s transmit/receive input (T/
) is set high, while the output enable input () is set low. To send data from bus B to bus A, T/ is set low. To disable the transceiver’s outputs (place output in a high-impedance state), a high is applied to .
) is set high, while the output enable input () is set low. To send data from bus B to bus A, T/ is set low. To disable the transceiver’s outputs (place output in a high-impedance state), a high is applied to .
FIGURE 12.135
12.10 Analog/Digital Interfacing
A number of tricks are used to interface analog circuits with digital circuits. In this section, we’ll take a look at two basic levels of interfacing. One level deals with simple on/off triggering. The other level deals with true analog-to-digital and digital-to-analog conversion—converting analog signals into digital numbers and converting digital numbers into analog signals.
12.10.1 Triggering Simple Logic Responses from Analog Signals
There are times when you need to drive logic from simple on/off signals generated by analog devices. For example, you may want to latch an alarm (via a flip-flop) when an analog voltage—say, one generated from a temperature sensor—reaches a desired threshold level. Or perhaps you simply want to count the number of times a certain analog threshold is reached. For simple on/off applications such as these, it is common to use a comparator or op amp as the interface between the analog output of the transducer and the input of the logic circuit. Often it is possible to simply use a voltage divider network composed of a transducer of variable resistance and a pullup resistor. Figure 12.136 shows some sample networks to illustrate the point.
FIGURE 12.136
In Fig. 12.136a, a phototransistor is used to trigger a logic response. Normally, the phototransistor is illuminated, which keeps the input of the first Schmitt inverter low. The output of the second inverter is high. When the light is briefly interrupted, the phototransistor momentarily stops conducting, causing the input to the first inverter to pulse low, while the output of the second inverter pulses high. This high pulse could be used to latch a D flip-flop, which could be used to trigger an LED or a buzzer alarm.
In Fig. 12.136b, a single-supply comparator with open-collector output is used as an analog-to-digital interface. When an analog voltage applied to Vin exceeds the reference voltage (Vref) set at the noninverting input (+) via the pot, the output goes low (the comparator sinks current through itself to ground). When Vin goes below Vref, the output goes high (the comparator’s output floats, but the pullup resistor pulls the comparator’s output high).
In Fig. 12.136c, a simple application of the previous comparator interface is shown. The input voltage is generated by an LM34 or LM35 temperature sensor. The LM34 generates 10 mV/°F, while the LM35 generates 10 mV/°C. The resistance of the pot and V+ determine the reference voltage. If we want to drive the comparator low when 75°C is reached, we set the reference voltage to 750 mV, assuming we’re using the LM35.
In Fig. 12.136d, an op amp set in comparator mode can also be used as an analog-to-digital interface for simple switching applications. CMOS logic can be driven directly through a current limiting resistor, as shown. If the supply voltage of the op amp exceeds the supply voltage of the logic, protection diodes should be used (as shown in the figure).
Protection diodes were not necessary with the LM339 because that has open-collector outputs.
In Fig. 12.136e, an op amp that is used to drive TTL typically uses a transistor output stage like the one shown here. The diode acts to prevent base-to-emitter reverse breakdown. When Vin exceeds Vref, the op amp’s output goes low, the transistor turns off, and the logic input receives a high.
In Fig. 12.136f, an n-channel MOSFET transistor is used as an output stage to an op amp.
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