4.3.1 The Ideal Switch

It is always desired to have the power switches perform as close as possible to the ideal case. Device characteristically speaking, for a semiconductor device to operate as an ideal switch, it must possess the following features:

The switching waveforms for an ideal switch is shown in Fig. 4.2, where i_sw and v_sw are the current through and the voltage across the switch, respectively.

FIGURE 4.2 Ideal switching current, voltage, and power waveforms.

Both during the switching and conduction periods, the power loss is zero, resulting in a 100% efficiency, and with no switching delays, an infinite operating frequency can be achieved. In short, an ideal switch has infinite speed, unlimited power handling capabilities, and 100% efficiency. It must be noted that it is not surprising to find semiconductor-switching devices that can almost, for all practical purposes, perform as ideal switches for number of applications.

4.3.2 The Practical Switch

The practical switch has the following switching and conduction characteristics:

The average switching power and conduction power losses can be evaluated from these waveforms. We should point out the exact practical switching waveforms vary from one device to another device, but Fig. 4.3a is a reasonably good representation. Moreover, other issues such as temperature dependence, power gain, surge capacity, and over voltage capacity must be considered when addressing specific devices for specific applications. A useful plot that illustrates how switching takes place from on to off and vice versa is what is called switching trajectory, which is simply a plot of i_sw vs v_sw. Figure 4.3b shows several switching trajectories for the ideal and practical cases under resistive loads.

EXAMPLE 4.2 Consider a linear approximation of Fig. 4.3a as shown in Fig. 4.4a: (a) Give a possible circuit implementation using a power switch whose switching waveforms are shown in Fig. 4.4a, (b) Derive the expressions for the instantaneous switching and conduction power losses and sketch them, (c) Determine the total average power dissipated in the circuit during one switching frequency, and (d) The maximum power.

SOLUTION. (a) First let us assume that the turn-on time, t_on, and turn-off time, t_off, the conduction voltage V_ON, and the leakage current, I_OFF, are part of the switching characteristics of the switching device and have nothing to do with circuit topology.

When the switch is off, the blocking voltage across the switch is V_OFF that can be represented as a dc voltage source of value V_OFF reflected somehow across the switch during the off-state. When the switch is on, the current through the switch equals I_ON, hence, a dc current is needed in series with the switch when it is in the on-state. This suggests that when the switch turns off again, the current in series with the switch must be diverted somewhere else (this process is known as commutation). As a result, a second switch is needed to carry the main current from the switch being investigated when it's switched off. However, since i_sw and v_sw are linearly related as shown in Fig. 4.4b, a resistor will do the trick and a second switch is not needed. Figure 4.4 shows a one-switch implementation with S, the switch and R represents the switched-load.

(b) The instantaneous current and voltage waveforms during the transition and conduction times are given as follows

FIGURE 4.3 (a) Practical switching current, voltage, and power waveforms and (b) switching trajectory.

FIGURE 4.4 Linear approximation of typical current and voltage switching waveforms.

It can be shown that if we assume I_ON I_OFF and V_OFF V_ON, then the instantaneous power, p(t) = i_swv_sw can be given as follows,

Figure 4.4c shows a plot of the instantaneous power where the maximum power during turn-on and off is V_OFFI_ON/4.

(c) The total average dissipated power is given by

The evaluation of the above integral gives

The first expression represents the total switching loss, whereas the second expression represents the total conduction loss over one switching cycle. We notice that as the frequency increases, the average power increases linearly. Also the power dissipation increases with the increase in the forward conduction current and the reverse blocking voltage.

(d) The maximum power occurs at the time when the first derivative of p(t) during switching is set to zero, i.e.

solve the above equation for t_max, we obtain values at turn on and off, respectively,

Solving for the maximum power, we obtain

4.4.1 MOSFET Structure

Unlike the lateral channel MOSFET devices used in many IC technology in which the gate, source, and drain terminals are located in the same surface of the silicon wafer, power MOSFET use vertical channel structure in order to increase the device power rating [1]. In the vertical channel structure, the source and drain are in opposite side of the silicon waver. Figure 4.7a shows vertical cross-sectional view for a power MOSFET. Figure 4.7b shows a more simplified representation. There are several discrete types of the vertical structure power MOSFET available commercially today such as V-MOSFET, U-MOSFET, D-MOSFET, and S-MOSFET [1, 2]. The P–N junction between p-base (also referred to as body or bulk region) and the n-drift region provide the forward voltage blocking capabilities. The source metal contact is connected directly to the p-base region through a break in the n⁺ source region in order to allow for a fixed potential to p-base region during the normal device operation. When the gate and source terminal are set the same potential (V_GS = 0), no channel is established in the p-base region, i.e. the channel region remain unmodulated. The lower doping in the n-drift region is needed in order to achieve higher drain voltage blocking capabilities. For the drain–source current, I_D, to flow, a conductive path must be established between the n⁺ and n⁻ regions through the p-base diffusion region.

FIGURE 4.7 (a) Vertical cross-sectional view for a power MOSFET and (b) simplified representation.

4.4.2 MOSFET Regions of Operation

Most of the MOSFET devices used in power electronics applications are of the n-channel, enhancement-type like that which is shown in Fig. 4.6a. For the MOSFET to carry drain current, a channel between the drain and the source must be created. This occurs when the gate-to-source voltage exceeds the device threshold voltage, V_Th. For v_GS > V_Th, the device can be either in the triode region, which is also called “constant resistance” region, or in the saturation region, depending on the value of v_DS. For given v_GS , with small v_DS ( v_DS < v_GS − V_Th), the device operates in the triode region(saturation region in the BJT), and for larger v_DS(v_DS > v_GS –V_Th), the device enters the saturation region (active region in the BJT). For v_GS < V_Th, the device turns off, with drain current almost equals zero. Under both regions of operation, the gate current is almost zero. This is why the MOSFET is known as a voltage-driven device, and therefore, requires simple gate control circuit.

The characteristic curves in Fig. 4.6b show that there are three distinct regions of operation labeled as triode region, saturation region, and cut-off-region. When used as a switching device, only triode and cut-off regions are used, whereas, when it is used as an amplifier, the MOSFET must operate in the saturation region, which corresponds to the active region in the BJT.

The device operates in the cut-off region (off-state) when v_GS < V_Th, resulting in no induced channel. In order to operate the MOSFET in either the triode or saturation region, a channel must first be induced. This can be accomplished by applying gate-to-source voltage that exceeds V_Th, i.e.

Once the channel is induced, the MOSFET can either operate in the triode region (when the channel is continuous with no pinch-off, resulting in the drain current proportioned to the channel resistance) or in the saturation region (the channel pinches off, resulting in constant I_D). The gate-to-drain bias voltage (v_GD) determines whether the induced channel enter pinch-off or not. This is subject to the following restriction.

For triode mode of operation, we have

And for the saturation region of operation, Pinch-off occurs when v_GD = V_Th.

In terms of v_DS, the above inequalities may be expressed as follows:

It can be shown that drain current, i_D, can be mathematically approximated as follows:

(4.6)

(4.7)

where,

μn = electron mobility

C_OX = oxide capacitance per unit area

L = length of the channel

W = width of the channel.

Typical values for the above parameters are given in the PSPICE model discussed later. At the boundary between the saturation (active) and triode regions, we have,

(4.8)

Resulting in the following equation for i_D,

(4.9)

The input transfer characteristics curve for i_D and v_S. v_GS is when the device is operating in the saturation region shown in Fig. 4.10.

FIGURE 4.10 Input transfer characteristics for a MOSFET device when operating in the saturation region.

The large signal equivalent circuit model for a n-channel enhancement-type MOSFET operating in the saturation mode is shown in Fig. 4.11. The drain current is represented by a current source as the function of V_Th and v_GS.

FIGURE 4.11 Large signal equivalent circuit model.

If we assume that once the channel is pinched-off, the drain–source current will no longer be constant but rather depends on the value of v_DS as shown in Fig. 4.12. The increased value of v_DS results in reduced channel length, resulting in a phenomenon known as channel-length modulation [3, 4]. If the v_DS –i_D lines are extended as shown in Fig. 4.12, they all intercept the v_DS-axis at a single point labeled − 1/λ, where λ is a positive constant MOSFET parameter. The term (1 + λ v_DS) is added to the i_D equation in order to account for the increase in i_D due to the channel-length modulation, i.e. i_D is given by,

(4.10)

FIGURE 4.12 MOSFET characteristics curve including output resistance.

From the definition of the r_o given in Eq. (4.1), it is easy to show the MOSFET output resistance which can be expressed as follows:

(4.11)

If we assume the MOSFET is operating under small signal condition, i.e. the variation in v_GS on i_D vs v_GS is in the neighborhood of the dc operating point Q at i_D and v_GS as shown in Fig. 4.13. As a result, the i_D current source can be represented by the product of the slope g_m and v_GS as shown in Fig. 4.14.

FIGURE 4.13 Linearized i_D vs v_GS curve with operating dc point (Q).

FIGURE 4.14 Small-signal equivalent circuit including MOSFET output resistance.

4.4.3 MOSFET Switching Characteristics

Since the MOSFET is a majority carrier transport device, it is inherently capable of a high frequency operation [5–8]. But still the MOSFET has two limitations:

As stated earlier the input capacitance consists of two components: the gate-to-source and gate-to-drain capacitances. The input capacitances can be expressed in terms of the device junction capacitances by applying Miller theorem to Fig. 4.15a. Using Miller theorem, the total input capacitance, C_in, seen between the gate-to-source is given by,

(4.12)

FIGURE 4.15 (a) Small-signal model including parasitic capacitances and (b) equivalent circuit using Miller theorem.

The frequency response of the MOSFET circuit is limited by the charging and discharging times of C_in. Miller effect is inherent in any feedback transistor circuit with resistive load that exhibits a feedback capacitance from the input and output. The objective is to reduce the feedback gate-to-drain resistance. The output capacitance between the drain-to-source, C_ds, does not affect the turn-on and turn-off MOSFET switching characteristics. Figure 4.16 shows how C_gd and C_gs vary under increased drain–source, v_Ds, voltage.

FIGURE 4.16 Variation of C_gd and C_gs as a function of v_DS.

In power electronics applications, the power MOSFETs are operated at high frequencies in order to reduce the size of the magnetic components. In order to reduce the switching losses, the power MOSFETs are maintained in either the on-state (conduction state) or the off-state (forward blocking) state.

It is important we understand the internal device behavior; therefore, the parameters that govern the device transition from the on-state and off-states. To investigate the on and off switching characteristics, we consider the simple power electronic circuit shown in Fig. 4.17a under inductive load. The fly back diode D is used to pick up the load current when the switch is off. To simplify the analysis we will assume the load inductance is L₀ large enough so that the current through it is constant as shown in Fig. 4.17b.

FIGURE 4.17 (a) Simplified equivalent circuit used to study turn-on and turn-off characteristics of the MOSFET and (b) simplified equivalent circuit.

4.4.4 MOSFET PSPICE Model

The PSPICE simulation package has been used widely by electrical engineers as an essential software tool for circuit design. With the increasing number of devices available in the market place, PSPICE allows for the accurate extraction and understanding of various device parameters and their variation effect on the overall design prior to their fabrication. Today's PSPICE library is rich with numerous commercial MOSFET models. This section will give a brief overview of how the MOSFET model is implemented in PSPICE. A brief overview of the PSPICE modeling of the MOSFET device will be given here.

4.4.5 MOSFET Large-signal Model

The equivalent circuit of Fig. 4.28 includes five device parasitic capacitances. The capacitors C_GB, C_GS, C_GD, represent the charge-storage effect between the gate terminal and the bulk, source, and drain terminals, respectively. These are non-linear two-terminal capacitors expressed as function of W, L, C_ox, V_GS, V_T0, V_DS, and C_GBO, C_GSO, C_GDO, where the capacitors C_GBO, C_GSO, C_GDO are outside the channel region, known as overlap capacitances, that exist between the gate electrode and the other three terminals, respectively. Table 4.1 shows the list of PSPICE MOSFET capacitance parameters and their default values. Notice that the PSPICE overlap capacitors keywords (C_GBO, C_GSO, C_GDO) are proportional either to the MOSFET width or length of the channel as follows:

(4.46)

FIGURE 4.28 Large-signal model for the n-channel MOSFET.

In the triode region, v_GS > v_DS –V_Th, the terminal capacitors are given by,

(4.47)

In the saturation (linear) region, we have

(4.48)

where C_OX is the per-unit-area oxide capacitance given by,

K_OX = Oxide's relative dielectric constant.

E₀ = Free space dielectric constant equals 8.854 × 10^{− 12} F/m.

T_OX = Oxide's thickness layer given as Tox in Table 4.1.

Finally, the diffusion and junction region capacitances between the bulk-to-channel (drain and source) are modeled by C_BD and C_BS across the two diodes. Because for almost all power MOSFETs, the bulk and source terminals are connected together and at zero potential, diodes D_BD and D_BS don't have forward bias, resulting in very small conductance values, i.e. small diffusion capacitances. The small-signal model for MOSFET devices is given in Fig. 4.29.

FIGURE 4.29 Small-signal equivalent circuit model for MOSFET.

EXAMPLE 4.4 Figure 4.30a shows an example of a soft switching power factor connection circuit that has two MOSFETs. Its PSPICE simulation waveforms are shown in Fig. 4.30b.

Table 4.2 shows the PSPICE code for Fig. 4.30a.

FIGURE 4.30 (a) Example of power electronic circuit and (b) PSPICE simulation waveforms.

TABLE 4.2 PSPICE MOSFET capacitance parameters and their default values for Fig. 4.30a

4.4.6 Current MOSFET Performance

The current focus of MOSFET technology development is much more broad than power handling capacity and switching speed; the size, packaging, and cooling of modern MOSFET technology is a major focus. Of course, the development of higher power and efficiency is still paramount, but as modern electronics have become increasingly smaller, the packaging and cooling of power circuits has become more important. It has been indicated by manufacturers that many of their modern MOSFETs are not limited by their semiconductor, but by the packaging. If the MOSFET cannot properly disperse heat, the device will become overheated, which will lead to failure.

An example of modern MOSFET technology is the DirectFET surface mounted MOSFET manufactured by International Rectifier. Part number IRF6662, for example, can handle 47A at 100V, while consuming a board space of 5 × 6 mm, and being only 0.6 mm thick. This switch is efficient at frequencies greater than 1 MHz, and the packaging can dissipate over 50% more heat than traditional surface mounted MOSFETs of similar power ratings. The power density of this switch is many times the power density of similarly rated devices made by International Rectifier in the past. One major factor in the performance gain of this product line is dual-sided cooling. By designing the package to mount to the board through a large contact patch, and by using materials with high heat conductivity, the switch has a very high surface area vs volume ratio, which allows for the heat to be dissipated through the top heat sink as well as through the circuit board.

Another example of manufacturers that are focusing on packaging and cooling to increase the performance of their products is Vishay's PolarPAK and PowerPAK. These devices have a 65% smaller board surface area than traditional SO-8 packages. Also, the thermal conductivity of the package is 88% greater than traditional devices. The PolarPAK device increases the performance by cooling the part from the top and the bottom of the package. These advances in packaging and cooling have allowed the devices to have power densities greater than 250W/mm³ as well, while maintaining high efficiencies into the megahertz.

Another important characteristic of any solid-state device is the expected service life. For MOSFETs, manufacturers have indicated that the mean time before failure (MTBF) approximately decreases by 50% for every 10°C that the operational temperature increases. For this reason, the current advancement in cooling and packaging has a direct effect on the longevity of the components. While there are definite increases in device longevity every year, the easiest way to have a large impact on the life of the device is to keep the temperature down.

Examples of modern MOSFETs

As development continues, MOSFETs will become smaller, more efficient, higher power density, and higher frequency of operation. As such, MOSFETs will continue to expand into applications that typically use other forms of power switches.