A. The Carrier-based Pulse Width Modulation (PWM) Technique

As mentioned earlier, it is desired that the ac output voltage, v₀ = v_aN, follow a given waveform (e.g. sinusoidal) on a continuous basis by properly switching the power valves. The carrier-based PWM technique fulfills such a requirement as it defines the on- and off-states of the switches of one leg of a VSI by comparing a modulating signal v_c (desired ac output voltage) and a triangular waveform vΔ (carrier signal). In practice, when v_Δ > vΔ the switch S₊ is on and the switch S+ is off; similarly, when v_c < v_Δ the switch S+ is off and the switch S− is on.

A special case is when the modulating signal v_c is a sinusoidal at frequency f_c and amplitude and the triangular signal V_Δ is at frequency f_Δ and amplitude This is the sinusoidal PWM (SPWM) scheme. In this case, the modulation index m_a (also known as the amplitude-modulation ratio) is defined as

(15.1)

and the normalized carrier frequency m_f (also known as the frequency-modulation ratio) is

(15.2)

Figure 15.3e clearly shows that the ac output voltage v₀ = V_aN is basically a sinusoidal waveform plus harmonics, which features: (a) the amplitude of the fundamental component of the ac output voltage satisfying the following expression:

(15.3)

for m_a ≤ 1, which is called the linear region of the modulating technique (higher values of m_a leads to overmodulation that will be discussed later); (b) for odd values of the normalized carrier frequency m_f the harmonics in the ac output voltage appear at normalized frequencies fh, centered around mf and its multiples, specifically,

(15.4)

where k = 2,4,6,… for l = 1,3,5,…; and k = 1,3,5,… for l = 2, 4, 6,…; (c) the amplitude of the ac output voltage harmonics is a function of the modulation index m_a and is independent of the normalized carrier frequency m_f for m_f > 9; (d) the harmonics in the dc link current (due to the modulation) appear at normalized frequencies f_p centered around the normalized carrier frequency mf and its multiples, specifically,

(15.5)

where k = 2,4,6,… for l = 1,3, 5,…; and k = 1,3, 5,… for l = 2,4,6,. …Additional important issues are: (a) for small values of m_f (m_f < 21), the carrier signal v_Δ and the signal v_c should be synchronized to each other (mf integer), which is required to hold the previous features; if this is not the case, subharmonics will be present in the ac output voltage; (b) for large values of m_f (m_f > 21), the subharmonics are negligible if an asynchronous PWM technique is used, however, due to potential very low-order subharmonics, its use should be avoided; finally (c) in the overmodulation region (m_a > 1) some intersections between the carrier and the modulating signal are missed, which leads to the generation of low-order harmonics but a higher fundamental ac output voltage is obtained; unfortunately, the linearity between m_a and achieved in the linear region does not hold in the overmodulation region, moreover, a saturation effect can be observed (Fig. 15.4).

FIGURE 15.4 Normalized fundamental ac component of the output voltage in a half-bridge VSI SPWM modulated.

The PWM technique allows an ac output voltage to be generated that tracks a given modulating signal. A special case is the SPWM technique (the modulating signal is a sinusoidal) that provides, in the linear region, an ac output voltage that varies linearly as a function of the modulation index, and the harmonics are at well-defined frequencies and amplitudes. These features simplify the design of filtering components. Unfortunately, the maximum amplitude of the fundamental ac voltage is v_i/2 in this operating mode. Higher voltages are obtained by using the overmodulation region (m_a > 1); however, low-order harmonics appear in the ac output voltage. Very large values of the modulation index (m_a > 3.24) lead to a totally square ac output voltage that is considered as the square-wave modulating technique.

B. Square-wave Modulating Technique

Both switches S+ and S_ are on for one half-cycle of the ac output period. This is equivalent to the SPWM technique with an infinite modulation index m_a. Figure 15.5 shows the following: (a) the normalized ac output voltage harmonics are at frequencies h = 3, 5,7,9,…, and for a given dc link voltage; (b) the fundamental ac output voltage features an amplitude given by

(15.6)

and the harmonics feature an amplitude given by

(15.7)

FIGURE 15.5 The half-bridge VSI. Ideal waveforms for the square-wave modulating technique: (a) ac output voltage and (b) ac output voltage spectrum.

It can be seen that the ac output voltage cannot be changed by the inverter. However, it could be changed by controlling the dc link voltage v. Other modulating techniques that are applicable to half-bridge configurations (e.g., selective harmonic elimination) are reviewed here as they can easily be extended to modulate other topologies.

C. Selective Harmonic Elimination

The main objective is to obtain a sinusoidal ac output voltage waveform where the fundamental component can be adjusted arbitrarily within a range and the intrinsic harmonics selectively eliminated. This is achieved by mathematically generating the exact instant of the turn-on and turn-off of the power valves. The ac output voltage features odd half-and quarter-wave symmetry; therefore, even harmonics are not present . Moreover, the phase voltage waveform (v_o = v_aN in Fig. 15.2), should be chopped N times per half-cycle in order to adjust the fundamental and eliminate N − 1 harmonics in the ac output voltage waveform. For instance, to eliminate the third and fifth harmonics and to perform fundamental magnitude control (N = 3), the equations to be solved are the following:

(15.8)

where the angles α₁, α₂ and α₃ are defined as shown in Fig. 15.6a. The angles are found by means of iterative algorithms as no analytical solutions can be derived. The angles a α₁, α₂, and α₃ are plotted for different values of in Fig. 15.7a. The general expressions to eliminate an even N − 1 (N − 1 = 2,4,6,…) number of harmonics are

(15.9)

where α₁, α₂. …, α_N should satisfy α₁ < α₂ < … < α_N < π/2. Similarly, to eliminate an odd number of harmonics, for instance the third, fifth, and seventh, and to perform the fundamental magnitude control (N − 1 = 3), the equations to be solved are:

(15.10)

where the angles α₁, α₂, α_3, and α₄ are defined as shown in Fig. 15.6b. The angles α₁, α_2., and α₃ are plotted for different values of in Fig. 15.7b. The general expressions to eliminate an odd N − 1 (N − 1 = 3,5,7,…) number of harmonics are given by

(15.11)

where α₁, α_2, … α_N should satisfy α₁ < α₂ < … < α_N < π/2.

FIGURE 15.6 The half-bridge VSI. Ideal waveforms for the SHE technique: (a) ac output voltage for third and fifth harmonic elimination; (b) spectrum of (a); (c) ac output voltage for third, fifth, and seventh harmonic elimination; and (d) spectrum of (c).

FIGURE 15.7 Chopping angles for SHE and fundamental voltage control in half-bridge VSIs: (a) third and fifth harmonic elimination and (b) third, fifth, and seventh harmonic elimination.

To implement the SHE modulating technique, the modulator should generate the gating pattern according to the angles as shown in Fig. 15.7. This task is usually performed by digital systems that normally store the angles in look-up tables.

D. DC Link Current

The split capacitors are considered a part of the inverter and therefore an instantaneous power balance cannot be considered due to the storage energy components (C+ and C_). However, if a lossless inverter is assumed, the average power absorbed in one period by the load must be equal to the average power supplied by the dc source. Thus, we can write

(15.12)

where T is the period of the ac output voltage. For an inductive load and a relatively high switching frequency, the load current i₀ is nearly sinusoidal and therefore, only the fundamental component of the ac output voltage provides power to the load. On the other hand, if the dc link voltage remains constant V_i(t) = V_i, Eq. (15.12) can be simplified to

(15.13)

where V₀₁ is the fundamental rms ac output voltage, I₀ is the rms load current, ϕ is an arbitrary inductive load power factor, and I_i is the dc link current that can be further simplified to

(15.14)

A. Bipolar PWM Technique

States 1 and 2 (Table 15.2) are used to generate the ac output voltage in this approach. Thus, the ac output voltage waveform features only two values, which are v_i and — v_i. To generate the states, a carrier-based technique can be used as in half-bridge configurations (Fig. 15.3), where only one sinusoidal modulating signal has been used. It should be noted that the on-state in switch S+ in the half-bridge corresponds to both switches S₁+ and S₂− being in the on-state in the full-bridge configuration. Similarly, S_ in the on-state in the half-bridge corresponds to both switches S₁₊ and S₂₋ being in the on-state in the full-bridge configuration. This is called bipolar carrier-based SPWM. The ac output voltage waveform in a full-bridge VSI is basically a sinusoidal waveform that features a fundamental component of amplitude that satisfies the expression

(15.15)

in the linear region of the modulating technique (m_a ≤ 1), which is twice that obtained in the half-bridge VSI. Identical conclusions can be drawn for the frequencies and the amplitudes of the harmonics in the ac output voltage and dc link current, and for operations at smaller and larger values of odd m_f (including the overmodulation region (m_a > 1)), than in half-bridge VSIs, but considering that the maximum ac output voltage is the dc link voltage v_i. Thus, in the over-modulation region the fundamental component of amplitude satisfies the expression

(15.16)

B. Unipolar PWM Technique

In contrast to the bipolar approach, the unipolar PWM technique uses the states 1, 2, 3, and 4 (Table 15.2) to generate the ac output voltage. Thus, the ac output voltage waveform can instantaneously take one of the three values, namely v_i, −v_i, and 0. To generate the states, a carrier-based technique can be used as shown in Fig. 15.9, where two sinusoidal modulating signals (v_c and — v_c) are used. The signal v_c is used to generate v_aN, and — v_c is used to generate v_bn; thus v_bn1 = v_aN1- On the other hand, v₀₁ = v_aN1 –v_bN1,= 2. v_aN1; thus This is called unipolar carrier-based SPWM.

FIGURE 15.9 The fall-bridge VSI. Ideal waveforms for the unipolar SPWM (m_a = 0.8, m_f = 8): (a) carrier and modulating signals; (b) switch Si+ state; (c) switch S2+ state; (d) ac output voltage; (e) ac output voltage spectrum; (f) ac output current; (g) de current; (h) de current spectrum; (i) switch S14. current; and (j) diode D₁₊ current.

Identical conclusions can be drawn for the amplitude of the fundamental component and harmonics in the ac output voltage and dc link current, and for operations at smaller and larger values of m_f (including the overmodulation region (m_a > 1)) than in full-bridge VSIs modulated by the bipolar SPWM. However, because the phase voltages (v_nN and v_bN) are identical but 180° out of phase, the output voltage (v_o = v_ab = v_aN − v_bn) will not contain even harmonics. Thus, if mf is taken even, the harmonics in the ac output voltage appear at normalized odd frequencies f_h centered around twice the normalized carrier frequency m_f and its multiples. Specifically,

(15.17)

where k = 1,3, 5,… and the harmonics in the dc link current appear at normalized frequencies f_p centered around twice the normalized carrier frequency mf and its multiples. Specifically,

(15.18)

where k = 1,3, 5,… This feature is considered to be an advantage because it allows the use of smaller filtering components to obtain high-quality voltage and current waveforms while using the same switching frequency as in VSIs modulated by the bipolar approach.

C. Selective Harmonic Elimination

In contrast to half-bridge VSIs, this approach is applied in a per-line fashion for full-bridge VSIs. The ac output voltage features odd half- and quarter-wave symmetry; therefore, even harmonics are not present . Moreover, the ac output voltage waveform (v₀ = v_fl in Fig. 15.8), should feature N pulses per half-cycle in order to adjust the fundamental component and eliminate N − 1 harmonics. For instance, to eliminate the third, fifth, and the seventh harmonics and to perform fundamental component magnitude control (N = 4), the equations to be solved are:

(15.19)

where the angles α₁, α₂, α₃, and α₄, are defined as shown in Fig. 15.10a. The angles α₁, α₂, α₃, and α₄, are plotted for different values of in Fig. 15.11a. The general expressions to eliminate an arbitrary N — I (N − 1 = 3, 5,7,…) number of harmonics are given by

(15.20)

where α_1, α_{2 …,} α_N should satisfy α₁ < α₂ < … < α_N < ϕ/2.

FIGURE 15.10 The half-bridge VSI. Ideal waveforms for the SHE technique: (a) ac output voltage for third, fifth, and seventh harmonic elimination; (b) spectrum of (a); (c) ac output voltage for fundamental control; and (d) spectrum of (c).

FIGURE 15.11 Chopping angles for SHE and fundamental voltage control in half-bridge VSIs: (a) fundamental control and third, fifth, and seventh harmonic elimination and (b) fundamental control.

Figure 15.10c shows a special case where only the fundamental ac output voltage is controlled. This is known as output control by voltage cancellation, which derives from the fact that its implementation is easily attainable by using two phase-shifted square-wave switching signals as shown in Fig. 15.12. The phase-shift angle becomes 2 α₁ (Fig. 15.11b). Thus, the amplitude of the fundamental component and harmonics in the ac output voltage are given by

(15.21)

FIGURE 15.12 The fall-bridge VSI. Ideal waveforms for the output control by voltage cancellation: (a) switch S₁₊. state; (b) switch S2+ state; (c) ac output voltage; and (d) ac output voltage spectrum.

It can also be observed in Fig. 15.12c that for α₁ = 0 square-wave operation is achieved. In this case, the fundamental

ac output voltage is given by

(15.22)

where the fundamental load voltage can be controlled by the manipulation of the dc link voltage.

D. DC Link Current

Due to the fact that the inverter is assumed lossless and constructed without storage energy components, the instantaneous power balance indicates that,

(15.23)

For inductive load and relatively high switching frequencies, the load current i₀ is nearly sinusoidal. As a first approximation, the ac output voltage can also be considered sinusoidal. On the other hand, if the dc link voltage remains constant V_i(t) = V_i, Eq. (15.23) can be simplified to

(15.24)

where V₀₁ is the fundamental rms ac output voltage, I₀ is the rms load current, and ϕ is an arbitrary inductive load power factor. Thus, the dc link current can be further simplified to

(15.25)

The preceding expression reveals an important issue, that is, the presence of a large second-order harmonic in the dc link current (its amplitude is similar to the dc link current). This second harmonic is injected back into the dc voltage source, thus its design should consider it in order to guarantee a nearly constant dc link voltage. In practical terms, the dc voltage source is required to feature large amounts of capacitance, which is costly and demands space, both undesired features, especially in medium- to high-power supplies.

A. Space-vector Transformation

Any three-phase set of variables that add up to zero in the stationary abc frame can be represented in a complex plane by a complex vector that contains a real (a) and an imaginary (β) component. For instance, the vector of three-phase line-modulating signals v_c^abc = [v_cav_cbV_cc]^T can be represented by the complex vector by means of the following transformation:

(15.36)

(15.37)

If the line-modulating signals v_c^abc are three balanced sinusoidal waveforms that feature an amplitude and an angular frequency ω, the resulting modulating signals in the αβ stationary frame become a vector of fixed module which rotates at frequency ω (Fig. 15.20). Similarly, the SV transformation is applied to the line voltages of the eight states of the VSI normalized with respect to v_i, (Table 15.3), which generates the eight space vectors ( i = 1,2,…, 8) in Fig. 15.20. As expected, to are non-null line-voltage vectors and and are null line-voltage vectors.

FIGURE 15.20 The space-vector representation.

The objective of the SV technique is to approximate the line-modulating signal space vector with the eight space vectors ( i = 1,2,…, 8) available in VSIs. However, if the modulating signal is laying between the arbitrary vectors , and , only the nearest two non-zero vectors ( and ) and one zero SV should be used. Thus, the maximum load line voltage is maximized and the switching frequency is minimized. To ensure that the generated voltage in one sampling period T_s (made up of the voltages provided by the vectors and used during times T_i, T_{i+ 1}, and T_z) is on average equal to the vector the following expression should hold:

(15.38)

The solution of the real and imaginary parts of Eq. (15.37) for a line-load voltage that features an amplitude restricted to 0 ≤ 1 ≤ gives

(15.39)

(15.40)

(15.41)

The preceding expressions indicate that the maximum fundamental line-voltage amplitude is unity as 0 ≤ 0 ≤ ϕ/3. This is an advantage over the SPWM technique which achieves a √ 3/2 maximum fundamental line-voltage amplitude in the linear operating region. Although, the space vector modulation (SVM) technique selects the vectors to be used and their respective on-times, the sequence in which they are used, the selection of the zero space vector, and the normalized sampled frequency remain undetermined.

For instance, if the modulating line-voltage vector is in sector 1 (Fig. 15.20), the vectors , , and should be used within a sampling period by intervals given by T₁, T₂, and T_z, respectively. The question that remains is whether the sequence (i) - - , (ii) - - - (iii) - - - - . (iv) - - - - , - - or any other sequence should actually be used. Finally, the technique does not indicate whether should be , , or a combination of both.

B. Space-vector Sequences and Zero Space-vector Selection

The sequence to be used should ensure load line-voltages that feature quarter-wave symmetry in order to reduce unwanted harmonics in their spectra (even harmonics). Additionally, the zero SV selection should be done in order to reduce the switching frequency. Although there is not a systematic approach to generate a SV sequence, a graphical representation shows that the sequence (where is alternately chosen among and ) provides high performance in terms of minimizing unwanted harmonics and reducing the switching frequency.

C. The Normalized Sampling Frequency

The normalized carrier frequency mf in three-phase carrier-based PWM techniques is chosen to be an odd integer number multiple of 3 (mf = 3 n, n = 1,3, 5,…). Thus, it is possible to minimize parasitic or non-intrinsic harmonics in the PWM waveforms. A similar approach can be used in the SVM technique to minimize uncharacteristic harmonics. Hence, it is found that the normalized sampling frequency f_sn should be an integer multiple of 6. This is due to the fact that in order to produce symmetrical line voltages, all the sectors (a total of 6) should be used equally in one period. As an example, Fig. 15.21 shows the relevant waveforms of a VSI SVM for f_sn = 18 and v_c = 0.8. Figure 15.21 confirms that the first set of relevant harmonics in the load line voltage are at f_sn which is also the switching frequency.

FIGURE 15.21 The three-phase VSI. Ideal waveforms for space-vector modulation : (a) modulating signals; (b) switch Si state; (c) switch S3 state; (d) ac output voltage; (e) ac output voltage spectrum; (f) ac output current; (g) de current; (h) de current spectrum; (i) switch Si current; and (j) diode D₁ current.

A. Space-vector Transformation in CSIs

Similarly to VSIs, the vector of three-phase line-modulating signals i_c^abc = [i_{ca icb} i_cc]^T can be represented by the complex vector by means of Eqs. (15.36) and (15.37). For three-phase balanced sinusoidal modulating waveforms, which feature an amplitude and an angular frequency ω, the resulting modulating signals complex vector becomes a vector of fixed module , which rotates at frequency ω (Fig. 15.33). Similarly, the SV transformation is applied to the line currents of the nine states of the CSI normalized with respect to i_i, which generates nine space vectors (, i = 1,2,…, 9 in Fig. 15.33). As expected, to are non-null line current vectors and , , and are null line current vectors.

FIGURE 15.33 The space-vector representation in CSIs.

The SV technique approximates the line-modulating signal space vector by using the nine space vectors (, i = 1,2,…, 9) available in CSIs. If the modulating signal vector i_c is between the arbitrary vectors , and , then , and combined with one zero SV ( = or or should be used to generate . To ensure that the generated current in one sampling period T_s (made up of the currents provided by the vectors , , and used during times T, T_i,+ 1, and T_z) is on average equal to the vector , the following expressions should hold:

(15.57)

(15.58)

(15.59)

where 0 ≤ ≤ 1. Although, the SVM technique selects the vectors to be used and their respective on-times, the sequence in which they are used, the selection of the zero space vector, and the normalized sampled frequency remain undetermined.

B. Space-vector Sequences and Zero Space-vector Selection

Although there is no systematic approach to generate a SV sequence, a graphical representation shows that the sequence , (where the chosen depends upon the sector) provides high performance in terms of minimizing unwanted harmonics and reducing the switching frequency. To obtain the zero SV that minimizes the switching frequency, it is assumed that I_c is in Sector $$. Then Fig. 15.34 shows all the possible transitions that could be found in Sector $$. It can be seen that the zero vector should be chosen to minimize the switching frequency. Table 15.6 gives a summary of the zero space vector to be used in each sector in order to minimize the switching frequency. However, should be noted that Table 15.6 is valid only for the sequence , , . Another sequence will require reformulating the zero space-vector selection algorithm.

FIGURE 15.34 Possible state transitions in Sector $$ involving a zero SV: (a) transition: or (b) transition: ; and (c) transition: .

TABLE 15.6 Zero SV for minimum switching frequency in CSI and sequence , ,

C. The Normalized Sampling Frequency

As in VSIs modulated by a SV approach, the normalized sampling frequency f_sn should be an integer multiple of 6 to minimize uncharacteristic harmonics. As an example, Fig. 15.35 shows the relevant waveforms of a CSI SVM for f_sn = 18 and = 0.8. Figure 15.35 also shows that the first set of relevant harmonics load line current are at f_sn.

FIGURE 15.35 The three-phase CSI. Ideal waveforms for space-vector modulation : (a) modulating signals; (b) switch Si state; (c) switch S3 state; (d) ac output current; (e) ac output current spectrum; (f) ac output voltage; (g) de voltage; (h) de voltage spectrum; (i) switch S₁ current; and (j) switch S₁ voltage.

A. Hysteresis Current Control

The main purpose here is to force the ac line current to follow a given reference. The status of the power valves S₁ and S₄ are changed whenever the actual i_oa current goes beyond a given reference i_oa,_ref ± Δi/2. Figure 15.41 shows the hysteresis current controller for phase a. Identical controllers are used in phase b and c. The implementation of this controller is simple as it requires an operational amplifier (op-amp) operating in the hysteresis mode, thus the controller and modulator are combined in one unit.

FIGURE 15.41 The three-phase VSI. Hysteresis current control (phase a).

Unfortunately, there are several drawbacks associated with the technique itself. First, the switching frequency cannot be predicted as in carrier-based modulators and therefore the harmonic content of the ac line voltages and currents becomes random (Fig. 15.42d). This could be a disadvantage when designing the filtering components. Second, as three-phase loads do not have the neutral connected as in ASDs, the load currents add up to zero. This means that only two ac line currents can be controlled independently at any given instant. Therefore, one of the hysteresis controllers is redundant at a given time. This explains why the load current goes beyond the limits and introduces limit cycles (Fig. 15.42a). Finally, although the ac load currents add up to zero, the controllers cannot ensure that all load line currents feature a zero dc component in one load cycle.

FIGURE 15.42 The three-phase VSI. Ideal waveforms for hysteresis current control: (a) actual ac load current and reference; (b) switch S₁ state; (c) ac output voltage; and (d) ac output voltage spectrum.

B. Linear Control of VSIs

Proportional and proportional-integrative controllers can also be used in VSIs. The main purpose is to generate the modulating signals v_ca, v_cb, and v_cc in a closed-loop fashion as depicted in Fig. 15.43. The modulating signals can be used by a carrier-based technique such as the SPWM (as depicted in Fig. 15.43) or by space vector modulation. Because the load line currents add up to zero, the load line current references must add up to zero. Thus, the abc/αβγ transformation can be used to reduce to two controllers the overall implementation scheme as the γ component is always zero. This avoids limit cycles in the ac load currents.

FIGURE 15.43 The three-phase VSI. Feedback control based on linear controllers.

The transformation of a set of variables in the stationary abc frame X^abc into a set of variables in the stationary αβ frame X^αβ is given by

(15.73)

The selection of the controller (P, PI,…) is done according to the control procedures such as steady-state error, settling time, overshoot, and so forth. Figure 15.44 shows the relevant waveforms of a VSI SPWM controlled by means of a PI controller as shown in Fig. 15.43.

FIGURE 15.44 The three-phase VSI. Ideal waveforms for a PI controller in a feedback loop (m_a, = 0.8, mf = 15): (a) actual ac load current and reference; (b) carrier and modulating signals; (c) ac output voltage; and (d) ac output voltage spectrum.

Although it is difficult to prove that no limit cycles are generated, the ac line current appears very much sinusoidal. Moreover, the ac line voltage generated by the VSI preserves the characteristics of such waveforms generated by SPWM modulators. This is confirmed by the harmonic spectrum shown in Fig. 15.44d, where the first set of characteristic harmonics are around the normalized carrier frequency mf = 15.

However, an error between the actual i_oa and the ac line current reference i_{oa, ref} can be observed (Fig. 15.44a). This error is inherent to linear controllers and cannot be totally eliminated, but it can be minimized by increasing the gain of the controller. However, the noise in the circuit is also increased, which could deteriorate the overall performance of the control scheme. The inherent presence of the error in this type of controllers is due to the fact that the controller needs a sinusoidal error to generate sinusoidal modulating signals v_ca, v_cb, and v_cc, as required by the modulator. Therefore, an error must exist between the actual and the ac line current references.

Nevertheless, as current-controlled VSIs are actually the inner loops in many control strategies, their inherent errors are compensated by the outer loop. This is the case of ASDs, where the outer speed loop compensates the inner current loops. In general, if the outer loop is implemented with dc quantities (such as speed), it can compensate the ac inner loops (such as ac line currents). If it is mandatory that a zero steady-state error be achieved with the ac quantities, then a stationary (abc frame) to rotating (dq frame) transformation is a valid alternative to use.

C. Linear Control of VSIs in a Rotating Frame

The rotating dq transformation allows ac three-phase circuits to be operated as if they were dc circuits. This is based upon a mathematical operation, that is the transformation of a set of variables in the stationary abc frame x^abc into a set of variables in the rotating dq0 frame x^dq0. The transformation is given by

(15.74)

where ω is the angular frequency of the ac quantities. For instance, the current vector given by

(15.75)

becomes the vector

(15.76)

where I and ϕ are the amplitude and phase of the line currents, respectively. It can be observed that: (a) the zero component o is always zero as the three-phase quantities add up to zero; and (b) the d and q components id, i_q are dc quantities. Thus, linear controllers should help to achieve zero steady-state error. The control strategy shown in Fig. 15.45 is an alternative where the zero-component controller has been eliminated due to fact that the line currents at the load side add up to zero.

FIGURE 15.45 The three-phase VSI. Feedback control based on dqo transformation.

The controllers in Fig. 15.45 include an integrator that generates the appropriate dc outputs m_d and m_q even if the actual and the line current references are identical. This ensures that the zero steady-state error is achieved. The decoupling block in Fig. 15.45 is used to eliminate the cross-coupling effect generated by the dq0 transformation and to allow an easier design of the parameters of the controllers.

The dq0 transformation requires the intensive use of multiplications and trigonometric functions. These operations can readily be done by means of digital microprocessors. Also, analog implementations would indeed be involved.

A. Occasional Regenerative Operating Mode

This mode is required during transient conditions such as in occasional braking of electrical machines (ASDs). Specifically, the speed needs to be reduced and the kinetic energy is taken into the dc bus. Because the motor line voltage is imposed by the VSI, the speed reduction should be done in such a way that the motor line currents do not exceed the maximum values. This boundary condition will limit the ramp-down speed to a minimum, but shorter braking times will require a mechanical braking system.

Figure 15.49 shows a transition from the motoring to regenerative operating mode for an ASD as shown in Fig. 15.47. Here, a stiff dc bus voltage has been used. Zone I in Fig. 15.49 is the motoring mode, Zone II is a transition condition, and Zone III is the regeneration mode. The line voltage is adjusted dynamically to obtain nominal motor line currents during regeneration (Fig. 15.49d). Zone III clearly shows that the shaft power gets reversed.

FIGURE 15.49 The ASD based on a VSI. Motoring to regenerative operating mode transition: (a) dc bus current; (b) ac line motor voltage; (c) ac phase motor voltage; (d) motor line current and back-emf; and (e) shaft power.

Occasional regeneration means that the drive rarely goes into this operating mode. Therefore, such energy can be: (a) left uncontrolled or (b) burned in resistors that are paralleled to the dc bus. The first option is used in low- to medium-power applications that use diode-based front-end rectifiers. Therefore, the dc bus current flows into the dc bus capacitor and the dc bus voltage rises accordingly to

(15.87)

where Δv_i, is the dc bus voltage variation, C is the dc bus voltage capacitor, I_i is the average dc bus current during regeneration, and Δt is the duration of the regeneration operating mode. Usually, the drives have the capacitor C designed to allow a 10% overvoltage in the dc bus.

The second option uses burning resistors R_R that are paralleled in the dc bus as shown in Fig. 15.50 by means of the switch S_R. A closed-loop strategy based on the actual dc bus voltage modifies the duty cycle of the turn-on/turn-off of the switch S_R in order to keep such voltage under a given reference. This alternative is used when the energy recovered by the VSI would result in an acceptable dc bus voltage variation if an uncontrolled alternative is used.

FIGURE 15.50 The ASD based on a VSI. Burning resistor strategy.

There are some special cases where the regeneration operating mode is frequently used. For instance, electrical shovels in mining companies have repetitive working cycles and ≈ 15% of the energy is sent back into the dc bus. In this case, a valid alternative is to send back the energy into the ac distribution system.

The schematic shown in Fig. 15.51 is capable of taking the kinetic energy and sending it into the ac grid. As reviewed earlier, the regeneration operating mode reverses the polarity of the dc current i, and because the diode-based front-end converter cannot take negative currents, a thyristor-based front-end converter is added. Similarly to the burning-resistor approach, a closed-loop strategy based on the actual dc bus voltage v_i modifies the commutation angle α of the thyristor rectifier in order to keep such voltage under a given reference.

FIGURE 15.51 The ASD based on a VSI. Diode-thyristor-based front-end rectifier with regeneration capabilities.

B. Regenerative Operating Mode as Normal operating Mode

Fewer industrial applications are capable of returning energy into the ac distribution system on a continuous basis. For instance, mining companies usually transport their product downhill for a few kilometers before processing it. In such cases, the drive maintains the transportation belt conveyor at constant speed and takes the kinetic energy. Due to the large amount of energy and the continuous operating mode, the drive should be capable of taking the kinetic energy, transforming it into electrical energy, and sending it into the ac distribution system. This would make the drive a generator that would compensate for the active power required by other loads connected to the electrical grid.

The schematic shown in Fig. 15.52 is a modern alternative for adding regeneration capabilities to the VSI-based drive on a continuous basis. In contrast to the previous alternatives, this scheme uses a VSI topology as an active front-end converter, which is generally called voltage-source rectifier (VSR). The VSR operates in two quadrants, that is, positive dc voltages and positive/negative dc currents as reviewed earlier. This feature makes it a perfect match for ASDs based on a VSI. Some of the advantages of using a VSR topology are: (i) the ac supply current can be as sinusoidal as required (by increasing the switching frequency of the VSR or the ac line inductance); (ii) the operation can be done at a unity displacement power factor in both motoring and regenerative operating modes; and (iii) the control of the VSR is done in both motoring and regenerative operating modes by a single dc bus voltage loop.

FIGURE 15.52 The ASD based on a VSI. Active front-end rectifier with regeneration capabilities.

A. Valid Switch States in a Three-level VSI

The easiest way of obtaining the valid switch states is to analyze each phase separately. Phase a contains the switches S_1a, S_1b, S_4a, and S_4b,, which cannot be on simultaneously because a short circuit across the dc bus would be produced, and cannot be off simultaneously because an undefined phase voltage v_aN would be produced. A summary of the valid switch combinations is given in Table 15.7. It is important to note that all valid switch combinations satisfy the condition that switch S_1a state is always the opposite to switch S_4a, state, and that switch S_1b, state is always the opposite to switch S_4b, state. Any other switch-state combination would result in an undefined inverter phase a voltage because it will depend upon the load-phase current i_oa polarity. The switch states for phases b and c are identical to that of phase a; moreover, because they are paralleled, they can operate in an independent manner.

TABLE 15.7 Valid switch states for a three-level VSI, phase a

B. The SPWM Technique in Three-level VSIs

The main objective is to generate the appropriate 12 gating signals so as to obtain fundamental inverter phase voltages equal to a given set of modulating signals. Specifically, the SPWM in three-level inverters uses a sinusoidal set of modulating signals (v_ca, v_cb, and v_cc for phases a, b, and c, respectively) and N − 1 = 2 triangular type of carrier signals (v_{Δ 1} and V_{Δ 2}) as illustrated in Fig. 15.60a. The best results are obtained if the carrier signals are in-phase and feature an odd normalized frequency (e.g. mf = 15). According to Fig. 15.60a, switch Si” is either turned on if v_ca > v_{Δ 1} or off if v_ca < v_{Δ 1}, and switch S_1b is either turned on if v_ca > v_{Δ 2} or off if v_ca < v_{Δ 2.} Additionally, the switch S_4a status is obtained as the opposite to switch S_1a, and the switch S_4b status is obtained as the opposite to switch S_1b( In order to use the same set of carrier signals to generate the gating signals for phases b and c, the normalized frequency of the carrier signal mf should be a multiple of 3.

Thus, the possible values are mf = 3,9,15,21,….

Figure 15.60 shows the relevant waveforms for a three-level inverter modulated by means of a SPWM technique (m_f = 15, m_a = 0.8). Specifically, Fig. 15.60d shows the inverter phase voltage, which is clearly a three-level type of voltage, and Fig. 15.60f shows the load line voltage, which shows that the step voltages are at most v_i/2. More importantly, the inverter phase voltage (Fig. 15.60e) contains harmonics at l (mf ± k with l = 1,3,… and k = 0,2,4,… and at l (mf ± k with l = 2,4,… and k = 1,3,… For instance, the first set of harmonics (l = 1, mf = 15) are at 15, 15 ± 2, 15 ± 4,… The inverter line voltage (Fig. 15.60g) contains harmonics at l (m_f ± k with l = 1,3,… and k = 2,4,… and at l. m_f ± k with l = 2,4,… and k = 1,3,… For instance, the first set of harmonics in the line voltages (l = 1, mf = 15) are at 15 ± 2, 15 ± 4,….

All the other features of carrier-based PWM techniques also apply in multilevel inverters. For instance, (I) the fundamental component of the inverter phase voltages satisfies

(15.89)

and thus the line voltages satisfy

(15.90)

where 0 < m_a ≤ 1 the linear operating region. To further increase the amplitude of the load voltages, the overmodulation operating region can be used by further increasing the modulating signal amplitudes (m_a > 1), where the line voltages range in

(15.91)

Also, (II) the modulating signals could be improved by adding a third harmonic (zero sequence), which will increase the linear region up to m_a = 1.15. This results in a maximum fundamental line-voltage component equal to v_i; (III) a non-sinusoidal set of modulating signals could also be used by the modulating technique. This is the case where nonsinusoidal line voltages are required as in active filter applications; and (IV) because of the two quadrants operation of VSIs, the multilevel inverter could equally be used in applications where the active power flow goes from the dc to the ac side or from the ac to the dc side.

In general, for an N-level inverter modulated by means of a carrier-based technique, the following conclusions can be drawn:

FIGURE 15.61 Five-level VSI topology. Relevant waveforms using a SPWM (mf = 15, m_a = 0.8): (a) inverter phase a voltage; (b) inverter phase a voltage spectrum; (c) load line voltage; and (d) load line voltage spectrum.

One of the drawbacks of the multilevel inverter is that the dc link capacitors should be equal. Unfortunately, this is not a natural operating condition mainly due to the fact that the currents required by the inverter in the dc bus are not symmetrical and therefore the capacitors will not equally share the total dc supply voltage v_i. To overcome this problem, two alternatives are developed later on.

C. The Space-vector Modulation in Three-level VSIs

Digital techniques are naturally extended to multilevel inverters. In fact, the SV modulating technique can be applied using the same principles used in two-level inverters. However, the higher number of voltage levels increases the complexity of the practical implementation of the technique. For instance, in N = 3-level inverters, each leg allows N = 3 different switch combinations as indicated in Table 15.7. Therefore, there are N³ = 27 total valid switch combinations, which generate N³ = 27 load line voltages that are represented by N³ = 27 space vectors (, ,…,) in Fig. 15.62. For instance, = 0.5+jO.866 is due to the line voltages v_ab = 0.5, v_bc = 0.5, v_ca = − 1.0 in pu. Thus, although the principle of operation is the same, the SV digital algorithm will have to deal with a higher number of states N³. Moreover, because some space vectors (e.g. and in Fig. 15.62) produce the same load-voltage terminals, the algorithm will have to decide between the two based on additional criteria and that of the basic SV-approach. Clearly, as the number of level increases, the algorithm becomes more and more elaborate. However, the benefits are not evident as the number of level increases. The maximum number of levels used in practical applications is five. This is based on a compromise between the complexity of the implementation and the benefits of the resulting waveforms.

FIGURE 15.62 The space-vector representation in a three-level VSI.

D. DC Link Voltage Balancing Issues

Figure 15.59 shows a three-level inverter and the ideal waveforms are shown in Fig. 15.60, which assume an even distribution of the voltage across the dc link capacitors. This even distribution is not naturally achieved and could be overcome by supplying both capacitors from independent supplies or properly gating the power valves of the inverter in order to minimize the unbalance.

Figure 15.63 shows an ASD based on a three-level VSI, where the dc link capacitors are feed from two different sources. This approach is being commercially used as it ensures a robust balanced dc link voltage distribution and operates with a high-performance type of ac mains current. Indeed, for a N level inverter, N − 1 independent dc voltage supplies are required that could be provided by N − 1 six-pulse rectifiers feed from anN-1 -pulse transformer. Therefore, the ac main currents is a N − 1 level type of waveform.

FIGURE 15.63 ASD based on a three-phase three-level VSI topology.

This approach cannot be used when the inverter does not feature dc link voltage supplies. This is the case of static power reactive power compensators and static power active filters. In this case, the proper gating of the power valves becomes the only choice to keep and balance the dc link voltages. Figure 15.64a shows this case where the current added by the inverter i_o^abc provides the reactive power and current harmonics such that the ac mains current i_s^abc features a given power factor.

FIGURE 15.64 Reactive power and current harmonics compensator based on a three-phase three-level VSI topology: (a) power topology; (b) carrier and modulating signals; and (c) δ closed loop scheme.

The SPWM modulating technique could be used as in Fig. 15.60; however, the zero level of the carriers δ is left as a manipulable variable Fig. 15.64b. In fact, it is used to control the difference of the upper and lower capacitor voltages Δv_i = v_i1 — v_i2. A closed loop alternative is depicted in Fig. 15.64c to manipulate δ. The modulating signals v_c^abc are left to control the reactive power and current harmonics injected into the ac mains by regulating the currents i_o^abc and keep the total dc link voltage v_i = v_i1 + v_i2 equal to a reference. Both loops are not included in Fig. 15.64c.

A. The SPWM Technique in Three-level CSIs

As in three-level VSIs, the main objective is to generate the appropriate 12 gating signals so as to obtain fundamental inverter line currents equal to a given set of modulating signals. Specifically, the SPWM in three-level inverters uses a sinusoidal set of modulating signals (i_ca, i_cb, and i_cc for phases a, b, and c, respectively) and N − 1 = 2 triangular type of carrier signals (i_{Δ 1} and i_{Δ 2}) as illustrated in Fig. 15.66a and 15.66e. The best results are obtained if the carrier signals are 180° out of phase and feature an odd normalized frequency (e.g. mf = 15). In order to use the same set of carrier signals to generate the gating signals for phases b and c, the normalized frequency of the carrier signal m_f should be a multiple of 3. Thus, the possible values are m_f = 3,9,15,21,. …

FIGURE 15.66 Three-level CSI topology. Relevant waveforms using a SPWM (mf = 15, m_a = 0.8): (a) modulating signals and carrier signal 1; (b) switch Si i status; (c) inverter 1 linea current; (d) inverter 1 linea current spectrum; (e) modulating signals and carrier signal 2; (f) switch S₁₂ status; (g) inverter 2 linea current; and (h) inverter 2 linea current spectrum.

Figure 15.66 shows the relevant waveforms for a three-level inverter modulated by means of a SPWM technique (m_f = 15, m_a = 0.8). Specifically, Fig. 15.66b and 15.66f show the gating signals obtained as described earlier in this chapter. The inverter line currents shown in 15.66c and 15.66g feature spectra shown in 15.66d and 15.66h, respectively. As expected, the inverter line currents contain harmonics at l · mf ± k with l = 1,3,… and k = 2,4,… and at l (mf ± k with l = 2,4,. and k = 1,3,. … For instance, the first set of harmonics in the line currents (l = 1, m_f = 15) are at 15 ± 2, 15 ± 4,. …

The total inverter line current is shown in Fig. 15.67a, and features the first set of unwanted harmonics around 2 mf Fig. 15.67b. This becomes the first advantage of using a multilevel topology as the filtering component requirements become more relaxed. All the other features of carrier-based PWM techniques also apply in current source multilevel inverters. For instance: (I) the fundamental component of the line currents satisfy

(15.94)

where 0 < m_a ≤ 1 is the linear operating region. Also: (II) to further increase the amplitude of the load currents, a zero sequence signal could be injected to the modulating signals, in this case

(15.95)

the overmodulation operating region can be used by further increasing the modulating signal amplitudes , where the line currents range in

(15.96)

FIGURE 15.67 Three-level CSI topology. Relevant waveforms using a SPWM (mf = 15, m_a = 0.8): (a) total inverter line current and (b) total inverter line current spectrum.

Also: (III) a nonsinusoidal set of modulating signals could also be used by the modulating technique. This is the case where nonsinusoidal line currents are required as in active filter applications; and (IV) because of the two quadrants operation of CSIs, the multilevel inverter could equally be used in applications where the active power flow goes from the dc to the ac side or from the ac to the dc side. In general, for an N-level inverter modulated by means of a carrier-based technique, three modulating signals 120° out-of-phase and N − 1 carrier signals are required and the line currents in the inverters have a peak value of i_i/(N − 1).

One of the drawbacks of the multilevel inverter is that the dc link capacitors cannot be supplied by a single dc voltage source. This is due to the fact that the currents required by the inverter in the dc bus are not symmetrical and therefore the capacitors will not equally share the dc supply voltage v_i. To overcome this problem, two alternatives are developed later on.

B. DC Link Voltage Balancing Issues

Figure 15.65 shows a three-level inverter and the ideal waveforms are shown in Fig. 15.66 and Fig. 15.67, which assume equal dc link currents, i_i1 = i_i2 This even distribution is not naturally achieved and could be overcome by supplying the dc link inductors from independent supplies or properly gating the power valves of the inverter in order to minimize the unbalance.

Figure 15.68 shows an ASD based on a three-level current source inverter, where the dc link inductors are feed from two different sources. Unlike the VS topology, the scheme needs a closed loop control strategy to keep constant the dc link currents and equal to a given reference. This is achieved in commercial units by using either phase-controlled rectifiers or PWM rectifiers. Nevertheless, the multipulse transformer required to provide isolated dc link currents improves the ac mains current as in the VS multilevel topology.

FIGURE 15.68 ASD based on a three-phase three-level CSI topology.

This approach cannot be used when the inverter is not feed from an external power supply. This is the case of static series voltage compensators. In this case, the proper gating of the power valves becomes the only choice to keep and balance the dc link currents. Figure 15.64a shows this case where the voltage added by the inverter n v_o^abc compensates the sags and/or swells present in the ac mains in order to provide a constant voltage to the load.

The SPWM modulating technique could be used as in Fig. 15.66 and Fig. 15.67; however, the peak amplitude of one triangular is amplified in the factor 1 + δ and the peak amplitude of other triangular is amplified in the factor 1 − δ, where δ is left as a manipulable variable Fig. 15.69b. In fact, δ is used to control the difference of the dc link currents Δi_i = i_i1 –i_i2.

FIGURE 15.69 Reactive power and current harmonics compensator based on a three-phase three-level VSI topology: (a) power topology; (b) carrier and modulating signals; and (c) δ closed loop scheme.

A closed loop alternative is depicted in Fig. 15.69c to manipulate δ. The modulating signals i_c^abc are left to control the series injected voltage into the ac mains by regulating the voltages v_o^abc and keep the total dc link current i_i = i_i1 + i_i2 equal to a reference. Both loops are not included in Fig. 15.69c.