36
Advanced Control of Switching Power Converters
TU Lisbon, Instituto Superior Técnico, DEEC, A. C. Energia, Center for Innovation on Electrical and Energy Engineering, AV. Rovisco Pais 1, 1049-001 Lisboa, Portugal
36.1 Introduction
36.2 Switching Power Converter Control Using State-Space Averaged Models
36.2.1 Introduction
36.2.2 State-Space Modeling
36.2.3 Converter Transfer Functions
36.2.4 Pulse-Width Modulator Transfer Functions
36.2.5 Linear Feedback Design Ensuring Stability
36.2.6 Examples: Buck–Boost DC/DC Converter, Forward DC/DC Converter, 12 Pulse Rectifiers, Buck–Boost DC/DC Converter in the Discontinuous Mode (Voltage and Current Mode), Three-Phase PWM Inverters
36.3 Sliding-Mode Control of Switching Power Converters
36.3.1 Introduction
36.3.2 Principles of Sliding-Mode Control
36.3.3 Constant-Frequency Operation
36.3.4 Steady-State Error Elimination in Converters with Continuous Control Inputs
36.3.5 Examples: Buck–Boost DC/DC Converter, Half-bridge Inverter, 12-Pulse Parallel Rectifiers, Audio Power Amplifiers, Near-Unity Power Factor Rectifiers, Multilevel Inverters, Matrix Converters
36.4 Predictive Optimum Control of Switching Power Converters
36.4.1 Introduction
36.4.2 Principles of Nonlinear Predictive Optimum Control
36.4.3 Principles of Nonlinear Fast Predictive Optimum Control
36.4.4 Examples: Predictive Control of Multilevel Inverters and Matrix Converters
36.5 Fuzzy Logic Control of Switching Power Converters
36.5.1 Introduction
36.5.2 Fuzzy Logic Controller Synthesis
36.5.3 Example: Near Unity Power Factor Buck–Boost PWM Rectifier
36.6 Conclusions
36.1 Introduction
Switching power converters must be suitably designed and controlled in order to supply the voltages, currents, or frequency ranges needed for the load and to guarantee the requested dynamics [1–4]. Furthermore, they can be designed to serve as “clean” interfaces between most loads and the electrical utility system. Thereafter, the set switching power converter plus load behaves as an almost pure electrical utility resistive load.
This chapter provides basic and advanced skills to control electronic power converters, considering that the control of switching power converters is a vast and interdisciplinary subject. Control designers for switching power converters should know the static and dynamic behavior of the electronic power converter and how to design its elements for the intended operating modes. Designers must be experts on control techniques, especially the nonlinear ones, because switching converters are nonlinear, time-variant, discrete systems, and designers must be capable of analog or digital implementation of the derived modulators, regulators, or compensators. Powerful modeling methodologies and sophisticated control processes must be used to obtain stable-controlled switching power converters, not only with satisfactory static and dynamic performance but also with low sensitivity against load or line disturbances or, preferably, robustness.
In Section 36.2, the techniques to obtain suitable nonlinear and linear state-space models, for most switching converters, are presented and illustrated through examples. The derived linear models are used to create equivalent circuits and to design linear feedback controllers for converters operating in the continuous or discontinuous mode. The classical, linear time-invariant systems control theory, based on Laplace transform, transfer function concepts, Bode plots, or root locus, is best used with state-space averaged models, or derived circuits, and well-known triangular wave modulators for generating the switching variables or the trigger signals for the power semiconductors.
Nonlinear state-space models and sliding-mode controllers, presented in Section 36.3, provide a more consistent way of handling the problem in controlling switching converters because sliding mode is aimed at variable structure systems, as are switching power converters. Chattering, a characteristic of sliding mode, is inherent to switching power converters, even if they are controlled with linear methods. Chattering is very hard to remove and is acceptable in certain converter variables. The described sliding-mode methodology defines exactly the variables that need to be measured while providing the necessary equations (control and switching laws) whose implementation gives the robust modulator and compensator low-level hardware (or software). Therefore, the sliding-mode control integrates the design of the switching converter modulator and controller electronics, reducing the needed designer expertise. This approach requires measurement of the state variables but eliminates conventional modulators and linear feedback compensators, enabling better performance and robustness. It also reduces the converter cost, control complexity, volume, and weight (increasing power density). The so-called main drawback of sliding mode, variable switching frequency, is also addressed, providing fixed-frequency auxiliary functions and suitable augmented control laws to null steady-state errors due to the use of constant switching frequency.
Predictive control uses a detailed, nonlinear dynamic model (including system bounds, saturations, hysteresis) of the switching power converter to forecast the converter future behavior on application of every possible switching state or vector. For all possible switching states (vectors), the control errors are evaluated and weighted, and the vector that leads to the minimum value of a suitable cost function is selected and applied to the converter. Predictive controllers also integrate the design of the switching converter modulator and the controller electronics using fast microprocessors or fast algorithms. The steps in designing a predictive optimum controller for switching power converters with finite small number of switching states are explained in Section 36.4. On choosing a suitable cost function, obtained converter performances are usually better than that obtained using linear or even sliding-mode controllers. This arises since sliding mode tries to go as fast as possible towards the sliding regime, but chatters along the sliding surface, while predictive control aims to zero the error at the next sampling step.
In contrast, fuzzy control of switching converters (Section 36.5) is a control technique that needs no converter models, parameters, or operating conditions but only an expert qualitative knowledge of the converter dynamics. Fuzzy controllers can be used in a diverse array of switching converters with only small adaptations because the controllers, based on fuzzy sets, are obtained from the knowledge of the system dynamics, using a model reference adaptive control philosophy. Obtained fuzzy control rules can be built into a decision-lookup table, in which the control processor simply picks up the control input corresponding to the sampled measurements. Fuzzy controllers are almost resistant to system parameter fluctuations because they do not consider their values. The steps to obtain a fuzzy controller are described, and the example provided compares the fuzzy controller performance to the current-mode control.
36.2 Switching Power Converter Control Using State-Space Averaged Models
36.2.1 Introduction
State-space models provide a general and strong basis for dynamic modeling of various systems including switching converters. State-space models are useful to design the needed linear control loops and can also be used to computer simulate the steady state and the dynamic behavior of the switching converter fitted with the designed feedback control loops and subjected to external perturbations. Furthermore, state-space models are the basis for applying powerful nonlinear control methods such as sliding mode. State-space averaging and linearization provides an elegant solution for the application of widely known linear control techniques to most switching power converters.
36.2.2 State-Space Modeling
Consider a switching power converter with sets of power semiconductor structures, each one with two different circuit configurations, according to the state of the respective semiconductors, and operating in the continuous mode of conduction. Supposing the power semiconductors as controlled ideal switches (zero on-state voltage drops, zero off-state currents, and instantaneous commutation between the on and off states), the time (t) behavior of the circuit, over period T, can be represented by the general form of the state-space model (36.1):
(36.1)
where x is the state vector, 
= dx/dt, u is the input or control vector, y is the output vector, and A, B, C, and D are, respectively, the dynamics (or state), the input, the output, and the direct transmission (or feedforward) matrices.
Since the power semiconductors will be either conducting or blocking, a time-dependent switching variable δ(t) can be used to describe the allowed switch states of each structure (i.e. δ(t) = 1 for the on-state circuit and δ(t) = 0 for the off-state circuit). Then, two subintervals must be considered: subinterval 1 for 0 ≤ t ≤ δ1 T, when δ(t) = 1, where δ1 is the duty ratio between the on state and the off state, and subinterval 2 for δ1 T ≤ t ≤ T, when δ(t) = 0. The state equations of the circuit, in each of the circuit configurations, can be written as
(36.2)
(36.3)
36.2.2.1 Switched State-Space Model
Given the two binary values of the switching variable δ(t), Eqs. (36.2) and (36.3) can be combined to obtain the nonlinear and time-variaint switched state-space model of the switching converter circuit, Eq. (36.4) or (36.5):
(36.4)
(36.5)
where As = [A1 δ(t) + A2(1 –δ(t))], Bs = [B1 δ(t) + B2(1 –δ(t))], Cs = [C1 δ(t) + C2(1 –δ(t))], and Ds = [D1 δ(t) + D2 (1 –δ(t))].
36.2.2.2 State-Space Averaged Model
Since the state variables of the x vector are continuous, using Eq. (36.4), with the initial conditions x1(0) = x2(T), x2(δ1 T) = X1(δ1 T), and considering the duty cycle δ1 as the average value of δ(t), the time evolution of the converter state variables can be obtained, integrating Eq. (36.4) over the intervals 0 ≤ t ≤ δ1 T and δ1 T ≤ t ≤ T, although it often requires excessive calculation effort. However, a convenient approximation can be devised, considering λmax, the maximum of the absolute values of all eigenvalues of A (usually λmax is related to the cutoff frequency fc of an equivalent low-pass filter with fc 
1/T). For λmax T 1, the exponential matrix (or state transition matrix) eAt = I + A t + A2 t2/2 + … + An tn/n!, where I is the identity or unity matrix, can be approximated by eAt ≈ I + A t. Therefore, 
Hence, the solution over the period T, for the system represented by Eq. (36.4), is found to be
(36.6)
This approximate response of Eq. (36.4) is identical to the exact response obtained from the nonlinear continuous time-invariant state-space model (36.7), supposing that the average values of x, denoted 
, are the new state variables and considering δ2 = 1 –δ1. Moreover, if A1 A2 = A2 A1, the approximation is exact.
For λmax T 1, the model (36.7), often referred to as the state-space averaged model, is also said to be obtained by “averaging” Eq. (36.4) over one period under small ripple and slow variations, as the average of products is approximated byproducts of the averages. Comparing Eq. (36.7) with Eq. (36.1), the following relations (36.8), defining the state-space averaged model, are obtained.
EXAMPLE 36.1 State-space models for the buck-boost dc/dc converter
Consider the simplified circuitry of the buck-boost converter of Fig. 36.1 switching at fs = 20 kHz (T = 50 µs) with VDCmax = 28V, VDCmin = 22V, Vo = 24 V, Li = 400 μH, Co = 2700 µF, Ro = 2Ω.
The differential equations governing the dynamics of the state vector x = [iL, vo]T (T denotes the transpose of vectors or matrices) are
(36.9)
(36.10)
Comparing Eqs. (36.9) and (36.10) with Eqs. (36.2) and (36.3) and considering y =[v0, iL]T, the following matrices can be identified:
FIGURE 36.1 (a) Basic circuit of the buck-boost dc/dc converter and (b) ideal waveforms.
From Eqs. (36.4) and (36.5), the switched state-space model of this switching converter is
(36.11)
Now, applying Eq. (36.7) Eqs. (36.12) and (36.13) can be obtained:
(36.12)
(36.13)
From Eqs. (36.12) and (36.13), the state-space averaged model, written as a function of δ1, is
(36.14)
(36.15)
The eigenvalues sbb1,2, or characteristic roots of A, are the roots of |sI –A|. Therefore,
(36.16)
Since λmax is the maximum of the absolute values of all the eigenvalues of A, the model (36.14, 36.15) is valid for switching frequencies fs(fs= 1/T) that verify λmax T 1. Therefore, as T 1/λmax, the values of T that approximately verify this restriction are T 1/max(|sbb1,2|). Given this buck-boost converter data, T 2 ms is obtained. Therefore, the converter switching frequency must obey fs 
max(
), implying switching frequencies above, say, 5 kHz. Consequently, the buck-boost switching frequency, the inductor value, and the capacitor value were chosen accordingly.
This restriction can be further used to discuss the maximum frequency Ωmax for which the state-space averaged model is still valid, given a certain switching frequency. As λmax can be regarded as a frequency, the preceding constraint brings Ωmax 2 π fs, say Ωmax < 2 π fs/10, which means that the state-space averaged model is a good approximation at frequencies under one-tenth of the power converter switching frequency.
The state-space averaged model (36.14, 36.15) is also the state-space model of the circuit represented in Fig. 36.2. Hence, this circuit is often named “the averaged equivalent circuit” of the buck-boost converter and allows the determination, under small ripple and slow variations, of the average equivalent circuit of the converter switching cell (power transistor plus diode).
FIGURE 36.2 Equivalent circuit of the averaged state-space model of the buck-boost converter.
The average equivalent circuit of the switching cell (Fig. 36.3a) is represented in Fig. 36.3b and emerges directly from the state-space averaged model (36.14, 36.15). This equivalent circuit can be viewed as the model of an “ideal transformer” (Fig. 36.3c), whose primary to secondary ratio (v1/v2) can be calculated applying Kirchhoff's voltage law to obtain –v1 + vs − v2 = 0. As v2 = δ1 vs, it follows that v1 = vs (1 − δ1), giving (v1/v2) = (1 –δ1)/δ1. The same ratio could be obtained beginning with iL = i1 + i2 and i1 = δ1 iL (Fig. 36.3b), which gives i2 = iL(1 –δ1) and (i2/i1) = δ2 /δ1.
FIGURE 36.3 Average equivalent circuit of the switching cell: (a) switching cell; (b) average equivalent circuit; and (c) average equivalent circuit using an ideal transformer.
The average equivalent circuit concept, obtained from Eq. (36.7) or Eqs. (36.14) and (36.15), can be applied to other switching converters, with or without a similar switching cell, to obtain transfer functions or to simulate the converter average behavior. The average equivalent circuit of the switching cell can be applied to converters with the same switching cell operating in the continuous conduction mode. However, note that the state variables of Eq. (36.7) or Eqs. (36.14) and (36.15) are the mean values of the converter instantaneous variables and therefore do not represent their ripple components. The inputs of the state-space averaged model are the mean values of the converter inputs over one switching period.
36.2.2.3 Linearized State-Space Averaged Model
Since the converter outputs 
must be regulated actuating on the duty cycle δ(t), the converter inputs 
usually present perturbations due to the load and power supply variations. State variables are decomposed in small ac perturbations (denoted by “~”) and dc steady-state quantities (represented by uppercase letters). Therefore,
(36.17)
Using Eq. (36.17) in Eq. (36.7) and rearranging terms, we obtain
(36.18)
(36.19)
The terms [A1Δ1 + A2Δ2]X + [B1Δ1 + B2 Δ2] U and [C1 Δ1 + C2 Δ2]X + [D1Δ1 + D2 Δ2]U, respectively, from Eqs. (36.18) and (36.19) represent the steady-state behavior of the system. As in steady state, 
, the following relationships hold:
(36.21)
Neglecting higher order terms 
of Eqs. (36.18) and (36.19), the linearized small-signal state-space averaged model is
(36.22)
or
(36.23)
(36.24)
36.2.3 Converter Transfer Functions
Using Eq. (36.20) in Eq. (36.21), the input U to output Y steady-state relations (36.25), needed for open-loop and feedforward control, can be obtained.
Applying Laplace transforms to Eq. (36.23) with zero initial conditions, and using the superposition theorem, the small-signal duty-cycle 
to output 
transfer functions (36.26), can be obtained considering zero-line perturbations (
= 0).
The line to output transfer function (or audio susceptibility transfer function), Eq. (36.27), is derived using the same method, considering now zero small-signal duty-cycle perturbations 
.
EXAMPLE 36.2 Buck-boost dc/dc converter transfer functions
From Eqs. (36.14) and (36.15) of Example 36.1 and Eq. (36.23), making X = [IL, V0]T, Y = [V0, IL]T, and U = [VDC], the linearized small-signal state-space model of the buck-boost converter is
(36.28)
From Eqs. (36.24) and (36.28), the following matrices are identified:
(36.29)
The averaged linear equivalent circuit, resulting from Eq. (36.28) or from the linearization of the averaged equivalent circuit (Fig. 36.2) derived from Eqs. (36.14) and (36.15), now includes the small-signal current source 
in parallel with the current source 
and the small-signal voltage source 
in series with the voltage source 
The supply voltage source 
is replaced by the voltage source 
Using Eq. (36.29) in Eq. (36.25), the input U to output Y steady-state relations are
(36.30)
(36.31)
These relations are the well-known steady-state transfer relationships of the buck-boost converter [2, 5, 6]. For open-loop control of the Vo output, knowing the nominal value of the power supply VDC and the required Vo, the value of Δ1 can be off-line calculated from Eq. (36.31), (Δ1 = Vo/(Vo + VDC)). A modulator such as that described in Section 36.2.4, with the modulation signal proportional to Δ1, would generate the signal Δ(t). The open-loop control for fixed output voltages is possible if the power supply VDC is almost constant, and the converter load does not change significantly. If the VDC value presents disturbances, then the feedforward control can be used, calculating Δ1 online so that its value will always be in accordance with Eq. (36.31). The correct Vo value will be attained at steady state, despite input-voltage variations. However, because of converter parasitic reactances, not modeled here (see Example 36.3), in practice a steady-state error would appear. Moreover, the transient dynamics imposed by the converter would present overshoots, being often not suited for demanding applications.
From Eq. (36.27), the line to output transfer functions are
(36.32)
(36.33)
From Eq. (36.26), the small-signal duty-cycle
to output 
transfer functions are
(36.34)
(36.35)
These transfer functions enable the choice and feedback-loop design of the compensation network. Note the positive zero in 
pointing out a nonminimum-phase system. These equations could also be obtained using the small-signal equivalent circuit derived from Eq. (36.28) or from the linearized model of the switching cell (Fig. 36.3b), substituting the current source 
by the current sources 
and 
in parallel and the voltage source 
by the voltage sources 
and 
in series.
EXAMPLE 36.3 Transfer functions of the forward dc/dc converter
Consider the forward (buck-derived) converter of Fig. 36.4 switching at fS= 100 kHz (T=10 µs) with VDC = 300 V, n = 30, Vo = 5 V, Li = 20 μH, rL = 0.01 Ω, Co = 2200 µ F, rC = 0.005 Ω, Ro = 0.1 Ω.
Assuming x= [iL, vC]T, δ(t) = 1 when both Q1 and D1 are “on” and D2 is “off” (0 ≤ t ≤ δ1 T) and δ(t) = 0 when both Q1 and D1 are “off” and D2 is “on” (δ1 T ≤ t ≤ T), the switched state-space model of the forward converter, considering as output vector y = [iL, vo]T, is
(36.36)
FIGURE 36.4 (a) Basic circuit of the forward dc/dc converter and (b) circuit main waveforms.
Making rcm = rC/(1 + rC/Ro), Roc = Ro + rC, koc = Ro/Roc, rP = rL + rcm and comparing Eq. (36.36) with Eqs. (36.2) and (36.3), the following matrices can be identified:
Now, applying Eq. (36.7) the exact (since A1 = A2) state-space averaged model, Eqs. (36.37) and (36.38), is obtained:
(36.37)
(36.38)
Since A1 = A2, this model is valid for ωmax > 2πfs. The converter eigenvalues sf1,2, are
(36.39)
The equivalent circuit arising from Eqs. (36.37) and (36.38) is represented in Fig. 36.5. It could also be obtained with the concept of the switching cell equivalent circuit (Fig. 36.3) of Example (36.1).
FIGURE 36.5 Equivalent circuit of the averaged state-space model of the forward converter.
Making X = [IL, VC]T, Y = [IL, Vo, and U = [VDC], from Eq. (36.23) the small-signal state-space averaged model is
(36.40)
(36.41)
From Eq. (36.25), the input U to output Y steady-state relations are
(36.42)
(36.43)
Making rC = 0, rL = 0 and n = 1, the former relations give the well-known dc transfer relationships of the buck dc/dc converter. Relations shown in Eqs. (36.42) and (36.43) allow the open-loop and feedforward control of the converter, as discussed in Example 36.2, provided that all the modeled parameters are time invariant and accurate enough.
From Eq. (36.27), the line to output transfer functions are derived:
(36.44)
(36.45)
Using Eq. (36.26), the small-signal duty-cycle 
to output 
transfer functions are
(36.46)
(36.47)
The real zero of Eq. (36.47) is due to rC, the equivalent series resistance (ESR) of the output capacitor. A similar zero would occur in the buck–boost converter (Example 36.2) if the ESR of the output capacitor had been included in the modeling.
36.2.4 Pulse-Width Modulator Transfer Functions
In the pulse-width modulation (PWM) voltage-mode control, the output voltage uc(t) of the error (between desired and actual outputs) amplifier plus regulator, processed if needed, is compared to a repetitive or carrier waveform r(t) to obtain the switching variable δ(t) (Fig. 36.6a). This function controls the power switch, turning it “on” at the beginning of the period and turning it “off” when the ramp exceeds the uc (t) voltage. In Fig. 36.6b, the opposite occurs (turnoff at the end of the period, turnon when the uc(t) voltage exceeds the ramp).
FIGURE 36.6 Waveforms of pulse width modulators showing the variable time delays of the modulator response: (a) r(t) = ucmax t/T and (b) r(t) = ucmax –2ucmax Ωt/π.
Considering r(t) as represented in Fig. 36.6a (r(t) = ucmax t/T), δk is obtained equating r(t) = uc. giving δk = uc(t)/ucmax or δk/uc(t) = GM (GM= 1/ucmax). In Fig. 36.6b, the switching-on angle αk is obtained from r(t) = ucmax –2ucmax ωt/π, uc(t) = ucmax –2ucmax αk/π, giving αk = (π/2)(1 –uc/ucmax) and GM = ∂αk/∂uc = –π/(2 ucmax).
Since, after turn-off or turn-on, any control action variation of uc(t) will only affect the converter duty cycle in the next period (or sample for digital hardware), a time delay is introduced in the control loop. For simplicity, with small-signal perturbations around the operating point, this delay is assumed almost constant and equal to its mean value (T/2). Then, the transfer function of the PWM modulator is
(36.48)
The final approximation of Eq. (36.48), valid for ωT/2 < ω 2/2, [7] suggests that the PWM modulator can be considered an amplifier with gain GM and a dominant pole. Notice that this pole occurs at a frequency doubling the switching frequency, and most state-space averaged models are valid only for frequencies below one-tenth of the switching frequency. Therefore, in most situations, this modulator pole can be neglected, being simply δ(s) = GMuc(s), as the dominant pole of Eq. (36.48) stays at least one decade to the left of the dominant poles of the converter.
36.2.5 Linear Feedback Design Ensuring Stability
In the application of classical linear feedback control to switching power converters, Bode plots and root locus are, usually, suitable methods to assess system performance and stability. General rules for the design of the compensated open-loop transfer function are as follows:
1. The low-frequency gain should be high enough to minimize output steady-state errors;
2. The frequency of 0 dB gain (unity gain), ω0dB, should be placed close to the maximum allowed by the modeling approximations (λmax T 1) to allow fast response to transients. In practice, this frequency should be almost an order of magnitude lower than the switching frequency;
3. To ensure stability, the phase margin, defined as the additional phase shift needed to render the system unstable without gain changes (or the difference between the open-loop system phase at ω0dB and –180°), must be positive and in general greater than 30° (45° –70° is desirable). In the root locus, no poles should enter the right-half of the complex plane;
4. To increase stability, the gain should be less than − 30 dB at the frequency where the phase reaches − 180° (gain margin greater than 30 dB).
Transient behavior and stability margins are related: the obtained damping factor is generally 0.01 times the phase margin (in degrees), and overshoot (in percent) is given approximately by 75° minus the phase margin. The product of the rise time (in seconds) and the closed-loop bandwidth (in rad/s) is close to 2.8.
To guarantee gain and phase margins, the following series compensation transfer functions (usually implemented with operational amplifiers) are often used [8]:
36.2.5.1 Types of Compensation
36.2.5.1.1 Lag or Lead compensation
Lag compensation should be used in converters with good stability margin but poor steady-state accuracy. If the frequencies 1/Tp and 1/TZ of Eq. (36.49) with 1/Tp < 1/TZ are chosen sufficiently below the unity gain frequency, lag-lead compensation lowers the loop gain at high frequency but maintains the phase unchanged for frequencies f 1/TZ. Then, the dc gain can be increased to reduce the steady-state error without significantly decreasing the phase margin.
Lead compensation can be used in converters with good steady-state accuracy but poor stability margin. If the frequencies 1/Tp and 1/TZ of Eq. (36.49) with 1/Tp> 1/TZ are chosen below the unity gain frequency, lead-lag compensation increases the phase margin without significantly affecting the steady-state error. The Tp and Tz values are chosen to increase the phase margin, fastening the transient response and increasing the bandwidth.
36.2.5.1.2 Proportional-Integral Compensation
Proportional-integral (PI) compensators (36.50) are used to guarantee null steady-state error with acceptable rise times. The PI compensators are a particular case of lag-lead compensators, therefore suitable for converters with good stability margin but poor steady-state accuracy.
36.2.5.1.3 Proportional-Integral plus High-Frequency Pole Compensation
This integral plus zero-pole compensation (36.51) combines the advantages of a PI with lead or lag compensation. It can be used in converters with good stability margin but poor steady-state accuracy. If the frequencies 1/Tm and 1/TZ (1/Tz < 1/Tm) are carefully chosen, compensation lowers the loop gain at high frequency while only slightly lowering the phase to achieve the desired phase margin.
36.2.5.1.4 Proportional-Integral Derivative (PID), Plus High-Frequency Poles
The PID notch filter type (36.52) scheme is used in converters with two lightly damped complex poles, to increase the response speed, while ensuring zero steady-state error. In most switching power converters, the two complex zeros are selected to have a damping factor greater than the converter complex poles and slightly smaller oscillating frequency. The high-frequency pole is placed to achieve the needed phase margin [9]. The design is correct if the complex pole loci, heading to the complex zeros in the system root locus, never enter the right half-plane.
For systems with a high-frequency zero placed at least one decade above the two lightly damped complex poles, the compensator (36.53), with Ωz1 ≈ Ωτ2 < Ωρ, can be used. Usually, the two real zeros present frequencies slightly lower than the frequency of the converter complex poles. The two high-frequency poles are placed to obtain the desired phase margin [9]. The obtained overall performance will often be inferior to that of the PID type notch filter.
36.2.5.2 Compensator Selection and Design
The procedure to select the compensator and to design its parameters can be outlined as follows:
1. Compensator selection: In general, since VDC perturbations exist, null steady-state error guarantee is needed. High-frequency poles are usually necessary if the transfer function shows a − 6 dB/octave roll-off due to high frequency left plane zeros. Therefore, in general, two types of compensation schemes with integral action, Eq. (36.51) or (36.50) and Eq. (36.52) or (36.53), can be tried. Compensator (36.52) is usually convenient for systems with lightly damped complex poles;
2. Unity gain frequency, ω0dB, choice:
• If the selected compensator has no complex zeros, it is better to be conservative, choosing ω0dB sufficiently below the frequency of the lightly damped poles of the converter (or the frequency of the right half-plane zeros if lower). However, because of the resonant peak of most converter transfer functions, the phase margin can be obtained at a frequency near the resonance. If the phase margin is not enough, the compensator gain must be lowered;
• If the selected compensator has complex zeros, ω0dB can be chosen slightly above the frequency of the lightly damped poles;
3. Desired phase margin (ϕμ) specification, ϕm ≥ 30° (preferably between 45° and 70°);
4. Compensator zero-pole placement to achieve the desired phase margin:
• With the integral plus zero-pole compensation type (36.51), the compensator phase ϕcp, at the maximum frequency of unity gain (often ω0dB), equals the phase margin (ϕM) minus 180° and minus the converter phase ϕcv, (ϕcp = ϕμ –180° –ϕcv). The zero-pole position can be obtained calculating the factor fct = tg(π/2 + ϕcp/2) being ωz = ω0dB/fct and ωm = ω0dBfct.
• With the PID notch filter type (36.52) controller, the two complex zeros are placed to have a damping factor, τp, roughly equal to two times the damping τz of the converter complex poles, and oscillating frequency ω0cp 30% smaller than the complex poles frequency ωp. The high-frequency pole ωp1 is placed to achieve the needed phase margin 
with fct = tg(π/2 + ϕcp/2) and ϕcp = ϕμ –180° –ϕcv [5]). Alternatively, since for stability 
and 
it is obtained 1 > τz > τp and using the geometric mean, 
5. Compensator gain calculation (the product of the converter and compensator gains at the ω0dB frequency must be one);
6. Stability margin verification using Bode plots and root locus;
7. Result evaluation; restarting the compensator selection and design if the attained results are still not good enough.
Note that several modern computer programs, such as MAT-LAB, provide very easy and efficient tools (such as SISOTOOL) to design these controllers, even considering that switching power converters are discrete systems. Optimum controllers such as Linear Quadratic Gaussian (LQG, LQR) controllers, whose performances might be much better than linear controllers, can also be designed using the same tools. However, in evaluating optimum controller results, care must be taken in order to guarantee that the controlled converter frequency bandwidth and gain are not beyond the validity limits of the used models.
36.2.6 Examples: Buck-Boost DC/DC Converter, Forward DC/DC Converter, 12 Pulse Rectifiers, Buck-Boost DC/DC Converter in the Discontinuous Mode (Voltage and Current Mode), Three-Phase PWM Inverters
EXAMPLE 36.4 Feedback design for the buck-boost dc/dc converter
Consider the converter output voltage v0 (Fig. 36.1) to be the controlled output. From Example 36.2 and Eqs. (36.33) and (36.35), the block diagram shown in Fig. 36.7 is obtained. The modulator transfer function is considered a pure gain (Gm = 0.1). The magnitude and phase of the open-loop transfer function v0/uc (Fig. 36.8a trace 1) show a resonant peak due to the two lightly damped complex poles and the associated − 12 dB/octave roll-off. The right half-plane zero changes the roll-off to − 6 dB/octave and adds − 90° to the converter phase (nonminimum-phase converter).
Compensator selection. As VDC perturbations exist null, steady-state error guarantee is needed. High-frequency poles are needed given the − 6 dB/octave final slope of the transfer function. Therefore, two compensation schemes (36.51) and (36.52) with integral action are tried here. The buck-boost converter controlled with integral plus zero-pole compensation presents, in closed-loop pole, two complex poles closer to the imaginary axes than in open-loop pole. These poles should not dominate the converter dynamics. Instead, the real pole resulting from the open-loop pole placed at the origin should be almost the dominant one, thus slightly lowering the calculated compensator gain. If the ω0db frequency is chosen too low, the integral plus zero-pole compensation turns into a pure integral compensator (ωz = ωm = ω0dτ). However, the obtained gains are too low, leading to very slow transient responses.
FIGURE 36.7 Block diagram of the linearized model of the closed-loop buck-boost converter.
FIGURE 36.8 Bode plots for the buck-boost converter. Trace 1 –switching power converter magnitude and phase; trace 2 –compensator magnitude and phase; trace 3 –resulting magnitude and phase of the compensated converter: (a) PI plus high-frequency pole compensation with 60° phase margin, Ω0dB = 500 rad/s and (b) PID notch filter compensation with 65° phase margin, Ω0dB = 1000 rad/s.
Results showing the transient responses to v0ref and VDC step changes, using the selected compensators and converter Bode plots (Fig. 36.8), are shown in Fig. 36.9. The compensated real converter transient behavior occurs in the buck and in the boost regions. Notice the nonminimum-phase behavior of the converter (mainly in Fig. 36.9b), the superior performance of the PID notch filter compensator, and the unacceptable behavior of the PI with high-frequency pole. Care should be taken with load changes, when using this compensator, since instability can easily occur.
FIGURE 36.9 Transient responses of the compensated buck-boost converter. At t = 0.005 s, v0ref step from 23 to 26 V. At t = 0.02 s, VDC step from 26 to 23 V. Top graphs: step reference v0ref and output voltage v0. Bottom graphs: trace starting at 20 is iL current; trace starting at zero is 10(v0ref –v0): (a) PI plus high-frequency pole compensation with 60° phase margin and Ω0dB = 500 rad/s and (b) PID notch filter compensation with 64 phase margin and Ω0dB = 1000 rad/s.
The compensator critical values, obtained with the root-locus studies, are Wcpcrit = 700 s− 1 for the integral plus zero-pole compensator, Tcpcrit = 0.0012 s for the PID notch filter, and WIcpcrit = 18 s− 1 for the integral compensation derived from the integral plus zero-pole compensator (ωz = ωμ). This confirms the Bode-plot design and allows stability estimation with changing loads and power supply.
EXAMPLE 36.5 Feedback design for the forward dc/dc converter
Consider the output voltage v0 of the forward converter (Fig. 36.4a) to be the controlled output. From Example 36.3 and Eqs. (36.45) and (36.47), the block diagram of Fig. 36.10 is obtained. As in Example 36.4, the modulator transfer function is considered a pure gain (Gm = 0.1). The magnitude and phase of the open-loop transfer function v0/uc (Fig. 36.11a, trace 1) show an open-loop stable system. Since integral action is needed to have some disturbance rejection of the voltage source VDC, the compensation schemes used in Example 36.4, obtained using the same procedure (Fig. 36.11), were also tested.
Results, showing the transient responses to v0ref and VDC step changes, are shown in Fig. 36.12. Both the compensators (36.51) and (36.52) are easier to design than the ones for the buck-boost converter and both have acceptable performances. Moreover, the PID notch filter presents a much faster response.
FIGURE 36.10 Block diagram of the linearized model of the closed-loop controlled forward converter.
FIGURE 36.11 Bode plots for the forward converter. Trace 1 –switching power converter magnitude and phase; trace 2 –compensator magnitude and phase; trace 3 –resulting magnitude and phase of the compensated converter: (a) PI plus high-frequency pole compensation with 115° phase margin, Ω0dB = 500 rad/s and (b) PID notch filter compensation with 85° phase margin, Ω0dB = 6000 rad/s.
FIGURE 36.12 Transient responses of the compensated forward converter. At t = 0.005 s, v0ref step from 4.5 to 5 V. At t = 0.01 s, VDC step from 300 to 260 V. Top graphs: step reference v0ref and output voltage v0. Bottom graphs: top traces iL current; bottom traces 10(v0ref –v0); (a) PI plus high-frequency pole compensation with 115° phase margin, Ω0dB = 500 rad/s and (b) PID notch filter compensation with 85° phase margin, Ω0dB = 6000 rad/s.
Alternatively, a PID feedback controller such as Eq. (36.53) can be easily hand-adjusted, starting with the proportional, integral, and derivative gains all set to zero. In the first step, the proportional gain is increased until the output presents an oscillatory response with nearly 50% overshoot. Next, the derivative gain is slowly increased until the overshoot is eliminated. Finally, the integral gain is increased to eliminate the steady-state error as quickly as possible.
EXAMPLE 36.6 Feedback design for phase-controlled rectifiers in the continuous mode
Phase-controlled, p pulse (p > 1), thyristor rectifiers (Fig. 36.13a), operating in the continuous mode, present an output voltage with p identical segments within the mains period T. Given this cyclic waveform, the A, B, C, and D matrices for all these p intervals can be written with the same form, in spite of the topological variation. Hence, the state-space averaged model is obtained simply by averaging all the variables within the period T/p. Assuming small variations, the mean value of the rectifier output voltage UDC can be written [10]:
(36.54)
where α is the triggering angle of the thyristors, and Up the maximum peak value of the rectifier output voltage, determined by the rectifier topology and the ac supply voltage. The α value can be obtained [α = (π/2) × (1 –uc/ucmax)] using the modulator shown in Fig. 36.6b, where ω = 2π/T is the mains frequency. From Eq. (36.54), the incremental gain Kr of the modulator plus rectifier yields the following:
FIGURE 36.13 (a) Block diagram of a p pulse phase-controlled rectifier feeding a separately excited dc motor and (b) equivalent averaged circuit.
For a given rectifier, this gain depends on uc and should be calculated for a certain quiescent point. However, for feedback design purposes, note that the rectifier could be required to be stable in all operating points, the maximum value of Kr, denoted Krm, can be used:
(36.56)
The operation of the modulator, coupled to the rectifier thyristors, introduces a non-negligible time delay, with mean value T/2p. Therefore, from Eq. (36.48) the modulator-rectifier transfer function GR(s) is
Considering zero Up perturbations, the rectifier equivalent averaged circuit (Fig. 36.13b) includes the loss-free rectifier output resistance Ri because of the overlap in the commutation phenomenon caused by the mains inductance. Usually, Ri ≈ pωl/π where l is the equivalent inductance of the lines paralleled during the overlap, half of the line inductance for most rectifiers, except for single-phase bridge rectifiers where l is the line inductance. Here, L0 is the smoothing reactor, and Rm, Lm, and E0 are, respectively, the armature internal resistance, inductance, and back electromotive force of a separately excited dc motor (typical load). Assuming the mean value of the output current as the controlled output, making Lt = L0 + Lm, Rt = Ri + Rm, Tt = Lt/Rt, and applying Laplace transforms to the differential equation obtained from the circuit of Fig. 36.13b, the output current transfer function will be
(36.58)
The rectifier and load are now represented by a perturbed (E0) second-order system (Fig. 36.14). To achieve zero steady-state error, which ensures steady-state insensitivity to the perturbations, and to obtain closed-loop second-order dynamics, a PI controller (36.50) was selected for Cp(s) (Fig. 36.14). Canceling the load pole (− 1/Tt) with the PI zero (− 1/TZ) yields the following:
(36.59)
FIGURE 36.14 Block diagram of a PI controlled p pulse rectifier.
The rectifier closed-loop transfer function i0(s)/ioref(s), with zero E0 perturbations, is
(36.60)
The final value theorem enables the verification of the zero steady-state error. Comparing the denominator of Eq. (36.60) to the second-order polynomial s2 +2τ ωns + ω2n yields:
(36.61)
Since only one degree of freedom is available (Tp), the damping factor 
is imposed. Usually, 
is selected since it often gives the best compromise between response speed and overshoot. Therefore, from Eq. (36.61), Eq. (36.62) arises:
(36.62)
Note that both Tz (36.59) and Tp (36.62) are dependent upon circuit parameters. They will have the correct values only for dc motors with parameters closed to the nominal load value. Using Eq. (36.62) in Eq. (36.60) yields Eq. (36.63), the second-order closed-loop transfer function of the rectifier, showing that, with loads close to the nominal value, the rectifier dynamics depend only on the mean delay time T/2p.
From Eq. (36.63), ωn = v2p/T results, which is the maximum frequency allowed by ωτ/2p < v2/2, the validity limit of Eq. (36.48). This implies that τ ≥ v2/2, which confirms the preceding choice. For Up = 300 V, p = 6, T = 20 ms, l = 0.8 mH, Rm = 0.5 ω, Lt = 50 mH, E0 = − 150 V, ucmax=10 V, and kI = 0.1, Fig. 36.15a shows the rectifier output voltage u0n (u0n = u0/Up) and the step response for the output current i0N(i0N = i0/40) in accordance with Eq. (36.63). Notice that the rectifier is operating in the inverter mode. Figure 36.15b shows the effect, in the i0 current, of a 50% reduction in the E0 value. The output current is initially disturbed, but the error vanishes rapidly with time.
FIGURE 36.15 Transient response of the compensated rectifier: (a) step response of the controlled current i0 and (b) the current i0 response to a step chance to 50% of the E0 nominal value during 1.5T.
This modeling and compensator design are valid for small perturbations. For large perturbations, the rectifier firing angles will either saturate at the zero value or originate large current overshoots. For large signals, antiwindup schemes (Fig. 36.16a) or error ramp limiters (or soft starters) and PI integral component limiters (Fig. 36.16b) must be used. These solutions will also work with other switching power converters.
FIGURE 36.16 (a) PI implementation with antiwindup (usually, 1/Kp ≤ kw ≤ Ki/Kp) to deal with rectifier saturation and (b) PI with ramp limiter/soft starter (kr Kp) and integral component limiter to deal with large perturbations.
To use this rectifier current controller as the inner control loop of a cascaded controller for the dc motor speed regulation, a useful first-order approximation of Eq. (36.63) is i0(s)/ioref(s) ≈ 1/(sT/p + 1).
Although allowing a straightforward compensator selection and precise calculation of its parameters, the rectifier modeling presented here is not suited for stability studies. The rectifier root locus will contain two complex conjugate poles in branches parallel to the imaginary axis. To study the current controller stability, at least the second-order term of Eq. (36.48) in Eq. (36.57) is needed. Alternative ways include the first-order Padé approximation of e−sT/2p, e−sT/2p ≈ (1 –sT/4p)/(1 + sT/4p), or the second-order approximation, e−sT/2p ≈ (1 –sT/4p + (sT/2p)2/12)/(1 + sT/4p + (sT/2p)2/12). These approaches introduce zeros in the right half-plane (nonminimum-phase systems), or extra poles, giving more realistic results. Taking a first-order approximation and root-locus techniques, it is found that the rectifier is stable for Tp > kRM KI T/(4pRt)(ζ > 0.25). Another approach uses the conditions of magnitude and angle of the delay function e−sT/2p to obtain the system root locus. Also, the switching power converter can be considered a sampled data system, at frequency p/T, and Z transform can be used to determine the critical gain and first frequency of instability p/(2T), usually half the switching frequency of the rectifier.
EXAMPLE 36.7 Buck-boost dc/dc converter feedback design in the discontinuous mode
The methodologies just described do not apply to switching power converters operating in the discontinuous mode. However, the derived equivalent averaged circuit approach can be used, calculating the mean value of the discontinuous current supplied to the load, to obtain the equivalent circuit. Consider the buck-boost converter of Example 36.1 (Fig. 36.1) with the new values Li = 40 μ τ, C0 = 1000 μ F, and R0 = 15 ω. The mean value of the current iL0, supplied to the output capacitor and resistor of the circuit operating in the discontinuous mode, can be calculated noting that if the input VDC and output v0 voltages are essentially constant (low ripple), the inductor current rises linearly from zero, peaking at Ip = (VDC/Li)δ1 T (Fig. 36.17a). As the mean value of iL0, supposed linear, is IL0 = (Ipδ2 T)/(2T), using the steady-state input-output relation VDCδ1 = V0δ2 and the above IP value, IL0 can be written as follows:
FIGURE 36.17 (a) Waveforms of the buck-boost converter in the discontinuous mode and (b) equivalent averaged circuit.
This is a nonlinear relation that could be linearized near an operating point. However, switching power converters in the discontinuous mode seldom operate just near an operating point. Therefore, using a quadratic modulator (Fig. 36.18), obtained integrating the ramp r(t) (Fig. 36.6a) and comparing the quadratic curve to the term ucpi v0/V2Dc (which is easily implemented using the Unitrode UC3854 integrated circuit), the duty cycle 
and a constant incremental factor KCV can be obtained:
(36.65)
FIGURE 36.18 Block diagram of a PI controlled (feedforward linearized) buck-boost converter operating in the discontinuous mode.
Considering zero-voltage perturbations and neglecting the modulator delay, the equivalent averaged circuit (Fig. 36.17b) can be used to derive the output voltage to input current transfer function v0(s)/iL0(s) = R0/(sC0R0 + 1). Using a PI controller (36.50), the closed-loop transfer function is
(36.66)
Since two degrees of freedom exist, the PI constants are derived imposing τ and ωn for the second-order denominator of Eq. (36.66), usually 
and ωn ≤ 2πfs/10. Therefore,
(36.67)
The transient behavior of this converter, with τ = 1 and ωn ≈ πfs/10, is shown in Fig. 36.19a. Compared to Example 36.2, the operation in the discontinuous conduction mode reduces, by 1, the order of the state-space averaged model and eliminates the zero in the right-half of the complex plane. The inductor current does not behave as a true state variable because during the interval δ3 T, this current is zero, and this value is always the iL0 current initial condition. Given the differences between these two examples, care should be taken to avoid the operation in the continuous mode of converters designed and compensated for the discontinuous mode. This can happen during turn-on or step load changes and, if not prevented, the feedback design should guarantee stability in both modes (Example 36.8, Fig. 36.20).
FIGURE 36.19 Transient response of the compensated buck-boost converter in the discontinuous mode. At t = 0.001 s, v0ref step from 23 to 26 V. At t = 0.011 s, v0ref step from 26 to 23 V. Top graphs: step reference v0ref and output voltage v0. Bottom graphs: pulses, iL current; trace peaking at 40, 10 × (v0ref –v0): (a) PI-controlled and feedforward linearized buck-boost converter with τ = 1 and Ωτ ≈ πfs/10 and (b) Current-mode-controlled buck-boost with τ = 1 and maximum value Ipmax = 15 A.
FIGURE 36.20 Block diagram of a current-mode-controlled buck-boost converter operating in the discontinuous mode.
EXAMPLE 36.8 Feedback design for the buck-boost dc/dc converter operating in the discontinuous mode and using current-mode control
The performances of the buck-boost converter operating in the discontinuous mode can be greatly enhanced if a current-mode control scheme is used, instead of the voltage-mode controller designed in Example 36.7. Current-mode control in switching power converters is the simplest form of state feedback. Current mode needs the measurement of the current iL (Fig. 36.1) but greatly simplifies the modulator design (compare Fig. 36.18 with Fig. 36.20) since no modulator linearization is used. The measured value, proportional to the current iL, is compared with the ucPI value given by the output voltage controller (Fig. 36.20). The modulator switches off the power semiconductor when kI IP = ucPI.
Expressed as a function of the peak iL current IP, IL0 becomes (Example 36.7) IL0 = IPδ1 VDC/(2 V0), or considering the modulator task, IL0 = ucPIδ1 VDC/(2kI V0). For small perturbations, the incremental gain is KCM = ∂IL0/∂ucPI = δ1 VDC/(2 KI V0). An ILo current delay Td = 1/(2fs), related to the switching frequency fs, can be assumed. The current-mode control transfer function Gcm(s) is
(36.68)
Using the approach of Example 36.6, the values for Tz and Tp are given by Eq. (36.69).
The transient behavior of this converter, with ζ = 1 and maximum value for Ip, and Ipmax = 15 A, is shown in Fig. 36.19b. The output voltage step response presents no overshoot, no steady-state error, and better dynamics compared with the response (Fig. 36.19a) obtained using the quadratic modulator (Fig. 36.18). With current-mode control, the converter behaves like a reduced order system and the right half-plane zero is not present.
The current-mode control scheme can be advantageously applied to converters operating in the continuous mode, ensuring short-circuit protection, system-order reduction, and better performances. However, for converters operating in the step-up (boost) regime, a stabilizing ramp with negative slope is required, to ensure stability. The stabilizing ramp will transform the signal ucPI in a new signal ucPI − rem(ksrt/T), where ksr is the needed amplitude for the compensation ramp, and the function rem is the remainder of the division of ksrt by T. In the next section, current control of switching power converters will be detailed.
Closed-loop control of resonant converters can be achieved using the outlined approaches if the resonant phases of operation last for small intervals compared to the fundamental period. Otherwise, the equivalent averaged circuit concept can often be used and linearized, now considering the resonant converter input-output relations, normally functions of the driving frequency and input or output voltages, to replace the δ1.
EXAMPLE 36.9 Output voltage control in three-phase voltage-source inverters using sinusoidal wave PWM (SPWM) and space vector modulation (SVM)
Sinusoidal wave PWM
Voltage-source three-phase inverters (Fig. 36.21) are often used to drive squirrel cage induction motors (IM) in variable speed applications.
FIGURE 36.21 IGBT-based voltage-sourced three-phase inverter with induction motor.
Considering almost ideal power semiconductors, the output voltage ubk(k ε {1, 2, 3}) dynamics of the inverter is negligible as the output voltage can hardly be considered a state variable in the time scale describing the motor behavior. Therefore, the best known method to create sinusoidal output voltages uses an open-loop modulator with low-frequency sinusoidal waveforms sin(ωt), with the amplitude defined by the modulation index mi, (mi ε [0, 1]), modulating high-frequency triangular waveforms r(t) (carriers), Figure 36.22, a process similar to the one described in Section 36.2.4. The frequency and phase of the triangular carriers should guarantee half-wave and quarter-wave symmetry for minimum harmonic distortion.
FIGURE 36.22 (a) SPWM modulator schematic and (b) main SPWM signals.
This sinusoidal wave PWM (SPWM) modulator gene rates the variable τk represented in Fig. 36.22 by the rectangular waveform, which describes the inverter k leg state:
(36.70)
The turn-on and turn-off signals for the k leg inverter switches are related with the variable τk as follows:
This applies constant-frequency sinusoidally weighted PWM signals to the gates of each insulated gate bipolar transistor (IGBT). The PWM signals for all the upper IGBTs (Suk, k ε {1, 2, 3}) must be 120° out of phase, and the PWM signal for the lower IGBT Slk must be the complement of the Suk signal. Since transistor turn-on times are usually shorter than turn-off times, some dead time must be included between the Suk and Slk pulses to prevent internal short circuits.
Sinusoidal PWM can be easily implemented using a microprocessor or two digital counters/timers generating the addresses for two lookup tables (one for the triangular function and another for supplying the per unit basis of the sine, whose frequency can vary). Tables can be stored in read-only memories, ROM, or erasable programmable ROM, EPROM. One multiplier for the modulation index (perhaps into the digital-to-analog [D/A] converter for the sine ROM output) and one hysteresis comparator must also be included.
With SPWM, the first harmonic maximum amplitude of the obtained line-to-line voltage is only about 86% of the inverter dc supply voltage Va. Since it is expectable that this amplitude should be closer to Va, different modulating voltages (for example, adding a third-order harmonic with one-fourth of the fundamental sine amplitude) can be used till the fundamental harmonic of the line-to-line voltage is kept sinusoidal. Another way is to not use SPWM and consider the eight possible inverter output voltages to use directly. This will lead to space vector modulation.
Space vector modulation
Space vector modulation (SVM) is based on the polar representation (Fig. 36.23) of the eight possible base output voltages of the three-phase inverter (Table 36.1, where vα and vβ are the vector components of vector 
g, g ε {0, 1, 2, 3, 4, 5, 6, 7}, obtained with Eq. (36.72). Therefore, since all the available voltages can be used, SVM does not present the voltage limitation of SPWM.
FIGURE 36.23 α, β space vector representation of the three-phase bridge inverter leg base vectors.
TABLE 36.1 The three-phase inverter with eight possible γk combinations, vector numbers, and respective α, β components
Furthermore, being a vector technique, SVM fits well with the vector control methods often used in IM drives.
Consider that the vector 
(magnitude Vs, angle 
) must be applied to the IM. Since there is no such vector available directly, SVM uses an averaging technique to apply the two vectors, 
and 
, closest to 
. The vector 
will be applied during δaTs, whereas vector 
will last δBTs (where 1/TS is the inverter switching frequency, δa and δb are duty cycles, δa, δb ε [0, 1]). If there is any leftover time in the PWM period Ts, then the zero vector is applied during time δ0Ts = Ts –δaTs –δbTs. Since there are two zero vectors (
and 
), a symmetric PWM can be devised, which uses both 
and 
, as shown in Fig. 36.24. Such a PWM arrangement minimizes the power semiconductor switching frequency and IM torque ripples.
FIGURE 36.24 Symmetrical SVM.
The input to the SVM algorithm is the space vector 
, into the sector sn, with magnitude Vs and angle Fs. This vector can be rotated to fit into sector 0 (Fig. 36.23) reducing Φs to the first sector, Φ = Φs –snπ/3. For any 
that is not exactly along one of the six nonnull inverter base vectors (Fig. 36.23), SVM must generate an approximation by applying the two adjacent vectors during an appropriate amount of time. The algorithm can be devised considering that the projections of 
, onto the two closest base vectors, are values proportional to δa and δb duty cycles. Using simple trigonometric relations in sector 0 (0 < F < π/3) (Fig. 36.23) and considering Kt, the proportional ratio, δa and δB are, respectively, 
and 
, yielding
(36.73)
The Kt value can be found when 
and δB = 0 (or when 
and δB = 1). Therefore,when 
or
when 
the KT constant
is KT = 
Hence,
(36.74)
The obtained resulting vector 
cannot extend beyond the hexagon of Fig. 36.23. This can be understood if the maximum magnitude Vsm of a vector with F = π/6 is calculated. For F = π/6 the maximum duty cycles are δa = 1/2 and δb = 1/2. Then, form Eq. (36.74) Vsm = Va/(2 is obtained. This magnitude is lower than that of the vector 
since the ratio between these magnitudes is (3/2. To generate sinusoidal voltages, the vector 
must be inside the inner circle of Fig. 36.23 so that it can be rotated without crossing the hexagon boundary. Vectors with tips between this circle and the hexagon are reachable but produce nonsinusoidal line-to-line voltages.
For sector 0, (Fig. 36.23) SVM symmetric PWM switching variables (γ1, γ2, γ3) and intervals (Fig. 36.24) can be obtained by comparing a triangular wave with amplitude ucmax, (Fig. 36.24, where r(t) = 2ucmax t/Ts, t ε [0, Ts/2]) with the following values:
(36.75)
Extension of Eq. (36.75) to all six sectors can be done if the sector number sn is considered together with the auxiliary matrix 
:
(36.76)
Generalization of the values C0, Ca, and CB, denoted C0sn,CAsn and CBsn, are written in Eq. (36.77), knowing that, for example, Ξ((sn+ 4)mod6+ 1) is the Ξ matrix row with number (sn + 4)mod6 + 1
Therefore, γ1, γ2, and γ3 are
(36.78)
Supposing that the space vector 
is now specified in the orthogonal coordinates 
instead of magnitude Vs and angle Fs, the duty cycles δa and δb can be easily calculated knowing that vα = Vs cos F, vβ = Vs sin F and using Eq. (36.74):
(36.79)
This equation enables the use of Eqs. (36.77) and (36.78) to obtain SVM in orthogonal coordinates.
Using SVM or SPWM, the closed-loop control of the inverter output currents (induction motor stator currents) can be performed using an approach similar to that outlined in Example 36.6 and decoupling the currents expressed in a d, q rotating frame.
36.3 Sliding-Mode Control of Switching Power Converters
36.3.1 Introduction
All the designed controllers for switching power converters are variable structure controllers, in the sense that the control action changes rapidly from one to another of, usually, two possible δ(t) values, cyclically changing the converter topology. This is accomplished by the modulator (Fig. 36.6), which creates the switching variable δ(t) imposing δ(t) = 1 or δ(t) = 0, to turn on or turn off the power semiconductors. As a consequence of this discontinuous control action, indispensable for efficiency reasons, state trajectories move back and forth around a certain average surface in the state space, and the state variables present some ripple. To avoid the effects of this ripple in the modeling and to apply linear control methodologies to time-variant systems, average values of state variables and state-space averaged models or circuits were presented (Section 36.2). However, a nonlinear approach to the modeling and control problem, taking advantage of the inherent ripple and variable structure behavior of switching power converters, instead of just trying to live with them, would be desirable, especially if enhanced performances could be attained.
In this approach, switching power converters topologies, as discrete nonlinear time-variant systems, are controlled to switch from one dynamics to another when needed. If this switching occurs at a very high frequency (theoretically infinite), the state dynamics, described as in Eq. (36.4), can be enforced to slide along a certain prescribed state-space trajectory. The converter is said to be in sliding mode, the allowed deviations from the trajectory (the ripple) imposing the practical switching frequency.
Sliding-mode control of variable structure systems, such as switching power converters, is particularly interesting because of the inherent robustness [11, 12], capability of system order reduction, and appropriateness to the on/off switching of power semiconductors. The control action, being the control equivalent of the management paradigm “Just in Time” (JIT), provides timely and precise control actions, determined by the control law and the allowed ripple. Therefore, the switching frequency is not constant over all operating regions of the converter.
This section considers the derivation of the control (sliding surface) and switching laws, robustness, stability, constant-frequency operation, and steady-state error elimination necessary for sliding-mode control of switching power converters, with some examples.
36.3.2 Principles of Sliding-Mode Control
Consider the state-space switched model Eq. (36.4) of a switching converter subsystem, and input-output linearization or another technique, to obtain, from state-space equations, one Eq. (36.80), for each controllable subsystem output y = x. In the controllability canonical form [13] (also known as input-output decoupled or companion form), Eq. (36.80) will be
(36.80)
where x = [xh,…, xj–1, xj]T is the subsystem state vector, fh(x) and bh(x) are functions of x, ph(t) represents the external disturbances, and uh(t) is the control input. In this special form of state-space modeling, the state variables are chosen so that the xi,+ 1 variable (i ε {h,…,j–1}) is the time derivative of xi, that is x = 
where m = j –h [14].
36.3.2.1 Control Law (Sliding Surface)
The required closed-loop dynamics for the subsystem output vector y = x can be chosen to verify Eq. (36.81) with selected ki values. This is a model reference adaptive control approach to impose a state trajectory that advantageously reduces the system order (j –h + 1).
Effectively, in a single-input single-output (SISO) subsystem, the order is reduced by unity, applying the restriction Eq. (36.81). In a multiple-input multiple-output (MIMO) system, in which v-independent restrictions could be imposed (usually with v degrees of freedom), the order could often be reduced in v units. Indeed, from Eq. (36.81), the dynamics of the jth term of x is linearly dependent from the j –h first terms:
(36.82)
The controllability canonical model allows the direct calculation of the needed control input to achieve the desired dynamics, Eq. (36.81). In fact, as the control action should enforce the state vector x, to follow the reference vector xr= 
the tracking error vector will be ε = 
or ε =
. Thus, equating the subexpressions for dxj/dt of Eqs. (36.80) and (36.81), the necessary control input uh(t) is
(36.83)
This expression is the required closed-loop control law, but unfortunately it depends on the system parameters and external perturbations, and is difficult to compute. Moreover, for some output requirements, Eq. (36.83) would give extremely high values for the control input uh(t), which would be impractical or almost impossible.
In most switching power converters, uh(t) is discontinuous. Yet, if we assume one or more discontinuity borders dividing the state space into subspaces, the existence and uniqueness of the solution is guaranteed out of the discontinuity borders since in each subspace the input is continuous. The discontinuity borders are subspace switching hypersurfaces, whose order is the space order minus one, along which the subsystem state slides since its intersections with the auxiliary equations defining the discontinuity surfaces can give the needed control input.
Within the sliding-mode control (SMC) theory, assuming a certain dynamic error driven to zero, one auxiliary equation (sliding surface) and the equivalent control input uh(t) can be obtained, integrating both sides of Eq. (36.82) with null initial conditions:
(36.84)
This equation represents the discontinuity surface (hyper-plane) and just defines the necessary sliding surface S(xi, t) to obtain the prescribed dynamics of Eq. (36.81):
(36.85)
In fact, by taking the first time derivative of S(xi, t), 
solving it for dxj/dt, and substituting the result in Eq. (36.83), the dynamics specified by Eq. (36.81) is obtained. This means that the control problem is reduced to a first-order problem since it is only necessary to calculate the time derivative of Eq. (36.85) to obtain the dynamics (36.81) and the needed control input uh(t).
The sliding surface Eq. (36.85), as the dynamics of the converter subsystem, must be a Routh-Hurwitz polynomial and verify the sliding manifold invariance conditions, 
(xi, t) = 0 and 
Consequently, the closed-loop controlled system behaves as a stable system of order j –h, whose dynamics is imposed by the coefficients ki, which can be chosen by pole placement of the poles of the order m = j –h polynomial. Alternatively, certain kinds of polynomials can be advantageously used [15]: Butterworth, Bessel, Chebyshev, elliptic (or Cauer), binomial, and minimum integral of time absolute error product (ITAE). Most useful are Bessel polynomials Be(s) shown in Eq. (36.88), which minimize the system response time tr, providing no overshoot, the polynomials Itae(s) shown in Eq. (36.87), which minimize the ITAE criterion for a system with desired natural oscillating frequency ω0, and binomial polynomials BI(s) shown in Eq. (36.86). For m> 1, ITAE polynomials give faster responses than binomial polynomials.
(36.86)
(36.87)
(36.88)
These polynomials can be the reference model for this model reference adaptive control method.
36.3.2.2 Closed-Loop Control Input-Output Decoupled Form
For closed-loop control applications, instead of the state variables xi, it is worthy to consider, as new state variables, the errors exi, components of the error vector e = 
of the state-space variables xi, relative to a given reference xir, Eq. (36.90). The new controllability canonical model of the system is
(36.89)
where fe(e),pe(t), and be(e) are functions of the error vector e. As the transformation of variables
(36.90)
is linear, the Routh-Hurwitz polynomial for the new sliding surface S(exi,t) is
(36.91)
Since exi+ 1(s) = sexi (s), this control law, from Eqs. (36.86) to (36.88), can be written as S(e, s) = exi (s + ω0)m, and is robust as it does not depend on circuit parameters, disturbances, or operating conditions but only on the imposed ki parameters and on the state variable errors exi, which can usually be measured or estimated. The control law Eq. (36.91) enables the desired dynamics of the output variable(s) if the semiconductor switching strategy is designed to guarantee the system stability. In practice, the finite switching frequency of the semiconductors will impose a certain dynamic error e steered to zero. The control law Eq. (36.91) is the required controller for the closed-loop SISO subsystem with output y.
36.3.2.3 Stability
Existence condition. The existence of the operation in sliding mode implies S(exi, t) = 0. Also, to stay in this regime, the control system should guarantee 
Therefore, the semiconductor switching law must ensure the stability condition for the system in sliding mode, written as
(36.92)
The fulfillment of this inequality ensures the convergence of the system state trajectories to the sliding surface S(exi, t) = 0 since
Hence, if Eq. (36.92) is verified, then S(exi,t) will converge to zero. This condition (36.92) is the manifold S(exi,t) invariance condition or the sliding-mode existence condition.
Given the state-space model Eq. (36.89) as a function of the error vector e and, from 
the equivalent average control input Ueq(t) that must be applied to the system in order that the system state slides along the surface Eq. (36.91), is given by
(36.93)
This control input Ueq(t) ensures the converter subsystem operation in the sliding mode.
Reaching condition. The fulfillment of S(exi,t) 
as S(exi,t) 
implies that the distance between the system state and the sliding surface will tend to zero since S2(exi,t) can be considered a measure for this distance. This means that the system will reach sliding mode. In addition, from Eq. (36.89), it can be written as follows:
(36.94)
From Eq. (36.91), Eq. (36.95) is obtained.
If S(exi,t) > 0, from the Routh-Hurwitz property of Eq. (36.91), then 
In this case, to reach S(exi,t) = 0, it is necessary to impose –be(e)uh(t) = –U in Eq. (36.94), with U chosen to guarantee dexj/dt < 0. After a certain time, exj. will be exj=dm,exh/dtm < 0 implying along with Eq. (36.95) that 
, thus verifying Eq. (36.92). Therefore, every term of S(exi,t) will be negative, which implies, after a certain time, an error 
and S(exi,t) < 0. Hence, the system will reach sliding mode, staying there if U = Ueq(t). This same reasoning can be made for S(exi,t) < 0; it is now being necessary to impose –be(e)uh(t) = +U, with U high enough to guarantee dexj/dt< 0.
To ensure that the system always reaches sliding-mode operation, it is necessary to calculate the maximum value of Ueq(t), Ueqmax, and also impose the reaching condition:
(36.96)
This means that the power supply voltage values U should be chosen high enough to additionally account for the maximum effects of the perturbations. With step inputs, even with U > Ueqmax, the converter usually loses sliding mode, but it will reach it again, even if the Ueqmax is calculated considering only the maximum steady-state values for the perturbations.
36.3.2.4 Switching Law
From the foregoing considerations, supposing a system with two possible structures, the semiconductor switching strategy must ensure 
Therefore, if S(exi,t) > 0, then 
which implies, as seen, –be(e)uh(t) = –U (the sign of be(e) must be known). Also, if S(exi,t) < 0, then 
which implies –be(e)uh(t) = + U. This imposes the switching between two structures at infinite frequency. Since power semiconductors can switch only at finite frequency, in practice, a small enough error for S(exi,t) must be allowed (–e < S(exi,t) < + e). Hence, the switching law between the two possible system structures might be
(36.97)
The condition in Eq. (36.97) determines that the control input to be applied and therefore represents the semiconductor switching strategy or switching function. This law determines a two-level pulse width modulator with JIT switching (variable frequency).
36.3.2.5 Robustness
The dynamics of a system, with closed-loop control using the control law Eq. (36.91) and the switching law Eq. (36.97), does not depend on the system operating point, load, circuit parameters, power supply, or bounded disturbances, as long as the control input uh(t) is large enough to maintain the converter subsystem in sliding mode. Therefore, it is said that the switching power converter dynamics, operating in sliding mode, is robust against changing operating conditions, variations of circuit parameters, and external disturbances. The desired dynamics for the output variable(s) is determined only by the ki coefficients of the control law Eq. (36.91), as long as the switching law (36.97) maintains the converter in sliding mode.
36.3.3 Constant-Frequency Operation
Prefixed switching frequency can be achieved, even with the sliding-mode controllers, at the cost of losing the JIT action. As the sliding-mode controller changes the control input when needed, and not at a certain prefixed rhythm, applications needing constant switching frequency (such as thyristor rectifiers or resonant converters) must compare 
(hysteresis width 2ι much narrower than 2ϵ) with auxiliary triangular waveforms (Fig. 36.25a), auxiliary sawtooth functions (Fig. 36.25b), three-level clocks (Fig. 36.25c), or phase-locked loop control of the comparator hysteresis variable width 2ϵ [16]. However, as illustrated in Fig. 36.25d, steady-state errors do appear. Often, they should be eliminated as described in Section 36.3.4.
FIGURE 36.25 Auxiliary functions and methods to obtain constant switching frequency with sliding-mode controllers.
36.3.4 Steady-State Error Elimination in Converters with Continuous Control Inputs
In the ideal sliding mode, state trajectories are directed toward the sliding surface (36.91) and move exactly along the discontinuity surface, switching between the possible system structures, at infinite frequency. Practical sliding modes cannot switch at infinite frequency, and therefore exhibit phase-plane trajectory oscillations inside a hysteresis band of width 2ε, centered in the discontinuity surface.
The switching law Eq. (36.91) permits no steady-state errors as long as 
tends to zero, which implies no restrictions on the commutation frequency. Control circuits operating at constant frequency, or needed continuous inputs, or particular limitations of the power semiconductors, such as minimum on or off times, can originate 
= ε1 ≠ 0. The steady-state error (exn) of the xh variable, xhr –xh = e1/kh, can be eliminated, increasing the system order by 1. The new state-space controllability canonical form, considering the error exi, between the variables and their references, as the state vector, is
(36.98)
The new sliding surface S(exi, t), written from Eq. (36.91) considering the new system Eq. (36.98), is
(36.99)
This sliding surface offers zero-state error, even if S(exi, t) = e1 due to the hardware errors or fixed (or limited) frequency switching. Indeed, at the steady state, the only nonzero term is 
Also, like Eq. (36.91), this closed-loop control law does not depend on system parameters or perturbations to ensure a prescribed closed-loop dynamics similar to Eq. (36.81) with an error approaching zero.
The approach outlined herein precisely defines the control law [sliding surface (36.91) or (36.99)] needed to obtain the selected dynamics and the switching law Eq. (36.97). As the control law allows the implementation of the system controller and the switching law gives the PWM modulator, there is no need to design linear or nonlinear controllers, based on linear converter models, or devise off-line PWM modulators. Therefore, sliding-mode control theory, applied to switching power converters, provides a systematic method to generate both the controller(s) (usually nonlinear) and the modulator(s) that will ensure a model reference robust dynamics, solving the control problem of switching power converters.
In the following examples, it is shown that the sliding-mode controllers use (nonlinear) state feedback, therefore, needing to measure the state variables and often other variables since they use more system information. This is a disadvantage since more sensors are needed. However, the straightforward control design and obtained performances are much better than those obtained with the averaged models, where the use of more sensors being really valued. State observers can be used as alternative to the extra sensors [13, 14].
36.3.5 Examples: Buck-Boost DC/DC Converter, Half-bridge Inverter, 12-Pulse Parallel Rectifiers, Audio Power Amplifiers, Near-Unity Power Factor Rectifiers, Multilevel Inverters, Matrix Converters
EXAMPLE 36.10 Sliding-mode control of the buck–boost dc/dc converter
Consider again the buck–boost converter of Fig. 36.1 and assuming the converter output voltage v0 to be the controlled output. From Section 36.2, using the switched state-space model of Eq. (36.11), making dv0/dt = θ, and calculating the first time derivative of θ, the controllability canonical model (36.100), where i0 = v0/R0, is obtained:
(36.100)
This model, written in the form of Eq. (36.80), contains two state variables, v0 and θ. Therefore, from Eq. (36.91) and considering 
the control law (sliding surface) is
(36.101)
This sliding surface depends on the variable δ(t), which should be precisely the result of the application, in Eq. (36.101), of a switching law similar to Eq. (36.97). Assuming an ideal up–down converter and slow variations, from Eq. (36.31) the variable δ(t) can be averaged to δ1 = v0/(v0 + VDC) Substituting this relation in Eq. (36.101) and rearranging, Eq. (36.102) is derived:
(36.102)
This control law shows that the power supply voltage VDC must be measured, as well as the output voltage v0 and the currents i0 and iL.
To obtain the switching law from stability considerations (36.92), the time derivative of S(exii>, t), supposing (vo + VDC)/v0 almost constant, is
(36.103)
If S(exi, t) > 0, then from Eq. (36.92), 
0 must hold. Analyzing Eq. (36.103), we can conclude that if 
is negative if, and only if, diL/dt > 0. Therefore, for positive errors evo < 0, the current iL must be increased, which implies δ(t) = 1. Similarly, for S(exi,t) < 0, diL/dt< 0 and δ(t) = 0. Thus, a switching law similar to Eq. (36.97) is obtained:
(36.104)
The same switching law could be obtained from knowing the dynamic behavior of this nonminimum-phase up–down converter: to increase (decrease) the output voltage, a previous increase (decrease) of the iL current is mandatory.
Equation (36.101) shows that if the buck–boost converter is into the sliding mode (S(exi, t) = 0), the dynamics of the output voltage error tends exponentially to zero with time constant k2/k1(k2/k1 > 0). Since during step transients, the converter is in the reaching mode, the time constant k2/k1 cannot be designed to originate error variations larger than the one allowed by the self-dynamics of the converter excited by a certain maximum permissible ii current. Given the polynomials (36.86–36.88) with m = 1, k1/k2 = ω0 should be much lower than the finite switching frequency (I/T) of the converter. Therefore, the time constant must obey k2/k1 T. Then, knowing that k2 and k1 are both imposed, the control designer can tailor the time constant as needed, provided that the above restrictions are observed.
Short-circuit-proof operation for the sliding-mode controlled buck–boost converter can be derived from Eq. (36.102), noting that all the terms to the left of iL represent the set point for this current. Therefore, limiting these terms (Fig. 36.26, saturation block, with iLmax = 40 A), the switching law (36.104) ensures that the output current will not increase above the maximum imposed limit. Given the converter nonminimum-phase behavior, this iL current limit is fundamental to reach the sliding mode of operation with step disturbances.
FIGURE 36.26 (a) Block diagram of the sliding-mode nonlinear controller for the buck–boost converter and (b) transient responses of the sliding-mode controlled buck–boost converter. At t = 0.005 s, voref step from 23 to 26 V. At t = 0.02 s, VDC step from 26 to 23 V. Top graph: step reference voref and output voltage v0. Bottom graph: trace starting at 20 is iL current; trace starting at zero is 10 × (voref–v0).
The block diagram (Fig. 36.26a) of the implemented control law Eq. (36.103) (with C0k1/k2 = 4) and switching law (36.103) (with e = 0.3) does not include the time derivative of the reference (dvvor/dt) since in a dc/dc converter, its value is considered zero. The controller hardware (or software), derived using just the sliding-mode approach, operates only in a closed loop.
The resulting performance (Fig. 36.26b) is much better than that obtained with the PID notch filter (compared to Example 36.4, Fig. 36.9b), with a higher response speed and robustness against power-supply variations.
EXAMPLE 36.11 Sliding-mode control of the single-phase half-bridge converter
Consider the half-bridge four-quadrant converter of Fig. 36.27 with the output filter and the inductive load (VDCmax = 300V; VDCmin = 230V; VDCmin = 230V; Ri = 0.1 ω; C0 = 470 μF; inductive load with nominal values R0 = 7 ω, L0 = 1 mH).
Assuming that power switches, output filter capacitor, and power supply are all ideal, and a generic load with allowed slow variations, the switched state-space model of the converter, with state variables v0 and iL, is
(36.105)
FIGURE 36.27 Half-bridge power inverter with insulated gate bipolar transistors, output filter, and load.
where i0 is the generic load current and vpwm = δ(t) VDC is the extended PWM output voltage (δ(t) = + 1 when one of the upper main semiconductors of Fig. 36.27is conducting and δ(t)= –1 when one of the lower semiconductors is on).
Output Current Control (Current-Mode Control)
To perform as a 
voltage-controlled iL current source (or sink) with transconductance gm (gm = iL/v
), this converter must supply a current iL to the output inductor, obeying iL = gmv
. Using a bounded v
voltage to provide output short-circuit protection, the reference current for a sliding-mode controller must be i
= gmv
Therefore, the controlled output is the iL, and the controllability canonical model (36.106) is obtained from the second equation of (36.105) since the dynamics of this subsystem, being governed by δ(t)VDC> is already in the controllability canonical form for this chosen output.
A suitable sliding surface (36.107) is obtained from Eq. (36.91), making eiL = iLr –iL.
The switching law Eq. (36.108) can be devised calculating the time derivative of Eq. (36.107), 
and applying Eq. (36.92). If S(eiL, t) > 0, then 
must hold to obtain 
implying δ(t) = 1.
The kp value and the allowed ripple e define the instantaneous value of the variable switching frequency. The sliding-mode controller is represented in Fig. 36.28a. Step response (Fig. 36.29a) shows the variable-frequency operation, a very short rise time (limited only by the available power supply), and confirms the expected robustness against supply variations.
FIGURE 36.28 (a) Implementation of short-circuit-proof sliding-mode current controller (variable frequency) and (b) implementation of fixed frequency, short-circuit-proof sliding-mode current controller using a triangular waveform.
FIGURE 36.29 Performance of the transconductance amplifier: response to a iLi step from –20 to 20 A at t = 0.001 s and to a VDC step from 300 to 230 V at t = 0.015 s: (a) variable-frequency sliding-mode controller and (b) fixed-frequency sliding-mode controller.
For systems where fixed-frequency operation is needed, a triangular wave, with frequency (10 kHz) slightly greater than the maximum variable frequency, can be added (Fig. 36.28b) to the sliding-mode controller, as explained in Section 36.3.3. Performances (Fig. 36.29b) are comparable to those of the variable-frequency sliding-mode controller (Fig. 36.29a). Figure 36.29b shows not only the constant switching frequency but also a steady-state error dependent on the operating point.
To eliminate this error, a new sliding surface Eq. (36.109), based on Eq. (36.99), should be used. The constants kp and k0 can be calculated, as discussed in Example 36.10.
The new constant-frequency sliding-mode current controller (Fig. 36.30a), with added antiwindup techniques (Example 36.6) since a saturation (errMax) is needed to keep the frequency constant, now presents no steady-state error (Fig. 36.30b). Performances are comparable to those of the variable-frequency controller, and no robustness loss is visible. The applied sliding-mode approach led to the derivation of the known average current-mode controller.
FIGURE 36.30 (a) Block diagram of the average current-mode controller (sliding mode) and (b) performance of the fixed-frequency sliding-mode controller with removed steady-state error: response to a iLr step from –20 to 20 A at t = 0.001 s and to a VDC step from 300 to 230 Vat t = 0.015 s.
Output Voltage Control
To obtain a power operational amplifier suitable for building uninterruptible power supplies, power filters, power gyrators, inductance simulators, or power factor active compensators, v0 must be the controlled converter output. Therefore, using the input–output linearization technique, it is seen that the first time derivative of the output (dv0/dt) = (iL, –i0)/C0 = τ does not explicitly contain the control input δ(t)VDC Then, the second derivative must be calculated. Taking into account Eq. (36.105), asτ = (iL –i0)/C0,Eq. (36.110) is derived.
This expression shows that the second derivative of the output depends on the control input δ(t)VDC No further time derivative is needed, and the state-space equations of the equivalent circuit, written in the phase canonical form, are
(36.111)
According to Eqs. (36.91), (36.111), and (36.105), considering that evo is the feedback error evo = vor –v0, a sliding surface, S(evo, t), can be chosen:
(36.112)
where β is the time constant of the desired first-order response of output voltage (β T > 0), as the strong relative degree [14] of this system is 2, and the sliding-mode operation reduces by one, the order of this system (the strong relative degree of a system is the least positive integer r for which the rth derivative of the output drv0/dtr is an explicit function of the control input u,beingdiv0/du = 0 for 0 ≤ i ≤ r –1 and drv0/du ≠ 0).
Calculating 
the control strategy (switching law) Eq. (36.113) can be devised since, if S(evo,t) > 0, then diL/dt then diL/dt must be positive to obtain 
implying δ(t) = 1. Otherwise S(t) = –1.
In the ideal sliding-mode dynamics, the filter input voltage vpwm switches between Vdc and –Vdc with the infinite frequency. This switching generates the equivalent control voltage Veq that must satisfy the sliding manifold invariance conditions, S(evo, t) = 0 and 
Therefore, from 
using Eqs. (36.112) and (36.105), (or from Eq. (36.110)), Veq is
(36.114)
This equation shows that only smooth input v0r signals (“smooth” functions) can be accurately reproduced at the inverter output, as it contains derivatives of the v0r signal. This fact is a consequence of the stored electromagnetic energy. The existence of the sliding-mode operation implies the following necessary and sufficient condition.
Equation (36.115) enables the determination of the minimum input voltage Vdc needed to enforce the sliding-mode operation. Moreover, even in the case of |Veq| > |VDC|, the system experiences only a saturation transient and eventually reaches the region of sliding-mode operation, except if the operating point and disturbances enforce |Veq| > |VDC| in steady state.
In the ideal sliding mode, at infinite switching frequency, state trajectories are directed toward the sliding surface and move exactly along the discontinuity surface. Practical switching power converters cannot switch at infinite frequency, so a typical implementation of Eq. (36.112) (Fig. 36.31a) with neglected 
features a comparator with hysteresis 2e, switching occurring at |S(evo, t)| > e with frequency depending on the slopes of iL. This hysteresis causes phase-plane trajectory oscillations of width 2ε around the discontinuity surface S(evo, t) = 0, but the Veq voltage is still correctly generated since the resulting duty cycle is a continuous variable (except for error limitations in the hardware or software, which can be corrected using the approach pointed out by Eq. (36.98)).
FIGURE 36.31 (a) Implementation of short-circuit-proof, sliding-mode output voltage controller (variable frequency) and (b) implementation of antiwindup PI current-mode (fixed frequency) controller.
The design of the compensator and the modulator is integrated with the same theoretical approach since the signal S(evo, t) applied to a comparator generates the pulses for the power semiconductors drives. If the short-circuit-proof operation is built into the power semiconductor drives, there is the possibility to measure only the capacitor current (iL –i0).
Short-Circuit Protection and Fixed-Frequency Operation of the Power Operational Amplifier
If we note that all the terms to the left of iL in Eq. (36.112) represent the value of iLr, a simple way to provide short-circuit protection is to bound the sum of all these terms (Fig. 36.31a with iLrmax = 100 A). Alternatively, the output current controllers of Fig. 36.28 can be used, comparing Eq. (36.107) with Eq. (36.112), to obtain iLr = S(evo, t Therefore, the block diagram of Fig. 36.31a provides the iLr output (for kp = 1) to be the input of the current controllers (Figs. 36.28a and 36.31a). As seen, the controllers of Figs. 36.28b and 36.30a also ensure fixed-frequency operation.
For comparison purposes, a proportional-integral (PI) controller, with antiwindup (Fig. 36.31b) for output voltage control, was designed, supposing the current-mode control of the half bridge (iLr = gm viL/(1 + sTd) considering a small delay Td), a pure resistive load R0, and using the approach outlined in Examples 36.6 and 36.8 (kv = 1,gm =,τ2 = 0.5, Td = 600 μs). The obtained PI Eq. (36.50) parameters are
(36.116)
Both variable-frequency (Fig. 36.32) and constant-frequency (Fig. 36.33) sliding-mode output voltage controllers present excellent performance and robustness with nominal loads. With loads much higher than the nominal value (Figs. 36.32b and 36.33b), the performance and robustness are also excellent. The sliding-mode constant-frequency PWM controller presents the additional advantage of injecting lower ripple in the load.
FIGURE 36.32 Performance of the power operational amplifier: response to a vor step from –200 to 200 V at t = 0.001 s and to a VDCsteP from 300 to 230 V at t = 0.015 s: (a) variable-frequency sliding mode (nominal load) and (b) variable-frequency sliding mode (R0 × 20).
FIGURE 36.33 Performance of the power operational amplifier; response to a vor step from –200 to 200 V at t = 0.001 s and to a VDCsteP from 300 to 230 V at t = 0.015 s: (a) fixed-frequency sliding mode (nominal load) and (b) fixed-frequency sliding mode (R0 × 20).
As expected, the PI regulator presents lower performance (Fig. 36.34). The response speed is lower, and the insensitivity to power supply and load variations (Fig. 36.34b) is not as high as with the sliding mode. Nevertheless, the PI performances are acceptable since its design was carried, considering a slow and fast manifold sliding-mode approach: the fixed-frequency sliding-mode current controller (36.109) for the fast manifold (the iL current dynamics) and the antiwindup PI for the slow manifold (the v0 voltage dynamics, usually much slower than the current dynamics).
FIGURE 36.34 Performance of the PI-controlled power operational amplifier: response to a vor step from –200 to 200 V at t = 0.001 s and to a VDC step from 300 to 230 Vat t = 0.015s: (a) PI current-mode controller (nominal load) and (b) PI current-mode controller (R0 × 20).
EXAMPLE 36.12 Constant-frequency sliding-mode control of p pulse parallel rectifiers
This example presents a new paradigm to the control of thyristor rectifiers. Since p pulse rectifiers are variable-structure systems, sliding-mode control is applied here to 12-pulse rectifiers, still useful for very high-power applications [3]. The design determines the variables to be measured and the controlled rectifier presents robustness, and much shorter response times, even with the parameter uncertainty, perturbations, noise, and non-modeled dynamics. These performances are not feasible using linear controllers, which are obtained here for comparison purposes.
Modeling the 12-Pulse Parallel Rectifier
The 12-pulse rectifier (Fig. 36.35a) is built with four 3-phase half-wave rectifiers, connected in parallel with current-sharing inductances l and l′ merged with capacitors l and C2, to obtain a second-order LC filter. This allows low-ripple output voltage and continuous mode of operation (laboratory model with l = 44 mH; l′ = 13 mH; C′ = C2 = 10 mF; star-delta connected ac sources with -Erms ≈ 65 V and power rating 2.2 kW load approximately resistive R0 ≈ 3 –5 ω).
FIGURE 36.35 (a) 12-pulse rectifier with interphase reactors and intermediate capacitors; (b) rectifier model neglecting the half-wave rectifier dynamics; and (c) low-order averaged equivalent circuit for the 12-pulse rectifier with the resulting output double LC filter.
To control the output voltage vC2, given the complexity of the whole system, the best approach is to derive a low-order model. By averaging the four half-wave rectifiers, neglecting the rectifier dynamics and mutual couplings, the equivalent circuit of Fig. 36.35b is obtained (l1 = l2 = l3 = l4 = l; l5 = l6 = l′; C11 = C12 = C′). Since the rectifiers are identical, the equivalent 12-pulse rectifier model of Fig. 36.35c is derived, simplifying the resulting parallel associations (L1 = l/4; L2 = 1/2; C1 = 2 C′).
Considering the load current i0 as an external perturbation and vi the control input, the state-space model of the equivalent circuit of Fig. 36.35c is
(36.117)
Sliding-Mode Control of the 12-Pulse Parallel Rectifier
Since the output voltage vc2 of the system must follow the reference vc2r, the system equations in the phase canonical (or controllability) form must be written, using the error ev2 = vc2r –vc2 and its time derivatives as new state error variables, as done in Example 36.11.
The sliding surface S(exi,t), designed to reduce the system order, is a linear combination of all the phase canonical state variables. Considering Eqs. (36.118) and (36.117) and the errors evc2, eθ, eγγ, and eβ, the sliding surface can be expressed as a combination of the rectifier currents, voltages, and their time derivatives:
(36.119)
Equation (36.119) shows the variables to be measured (vC2, vC1, i0, iL1, and iL2). Therefore, it can be concluded that the output current of each three-phase half-wave rectifier must be measured.
The existence of the sliding mode implies S(exi, t) = 0 and 
Given the state models (36.117, 36.118), and from 
the available voltage of the power supply vi, must exceed the equivalent average dc input voltage Veq (36.120), which should be applied at the filter input, in order that the system state slides along the sliding surface (36.119).
This means that the power supply root-mean-square (RMS) voltage values should be chosen high enough to account for the maximum effects of the perturbations. This is almost the same criterion adopted when calculating the RMS voltage values needed with linear controllers. However, as the Veq voltage contains the derivatives of the reference voltage, the system will not be able to stay in sliding mode with a step as the reference.
The switching law would be derived, considering that, from Eq. (36.118), be(e) > 0. Therefore, from Eq. (36.97), if S(exi,t)> + e, then vi,-(t) = Veqmax, else if S(exi, t) < –e, then vi(t) = –Veqmax. However, because of the lack of gate turn-off capability of the rectifier thyristors, power rectifiers cannot generate the high-frequency switching voltage vii(t) since the statistical mean delay time is T/2p(T = 20 ms) and reaches 7/2 when switching from + Veqmax to –Veqmax. To control mains switched rectifiers, the described constant-frequency sliding-mode operation method is used, in which the sliding surface S(exi, t), instead of being compared to zero, is compared to an auxiliary constant-frequency function r(t) (Fig. 36.6b) synchronized with the mains frequency. The new switching law is
(36.121)
Since now S(exi, t) is not near zero, butnear some value of r(t), a steady-state error 
appears (min[r(t)]/kp < 
< max[r(t)]/kp), as seen in Example 36.11. Increasing the value of kp (toward the ideal saturation control) does not overcome this drawback since oscillations would appear even for moderate kp gains because of the rectifier dynamics. Instead, the sliding surface (36.122), based on Eq. (36.99), should be used. It contains an integral term, which, given the canonical controllability form and the Routh–Hurwitz property, is the only nonzero term at steady state, enabling the complete elimination of the steady-state error.
To determine the k constants of Eq. (36.122), a pole-placement technique is selected, according to a fourth-order Bessel polynomial BE(s)m, m = 4, from Eq. (36.88), in order to obtain the smallest possible response time with almost no overshoot. For a delay characteristic as flat as possible, the delay fr is taken inversely proportional to a frequency fci just below the lowest cutoff frequency (fci < 8.44 Hz) of the double LC filter. For this fourth-order filter, the delay is tr = 2.8/(2πfci). By choosing fci = 7 Hz(tr ≈ 64 ms) and dividing all the Bessel polynomial terms by str, the characteristic polynomial (36.123) is obtained:
(36.123)
This polynomial must be applied to Eq. (36.123) to obtain the four sliding functions needed to derive the thyristor trigger pulses of the four 3-phase half-wave rectifiers. These sliding functions will enable the control of the output current (il1, il2, il3 and il4) of each half-wave rectifier, improving the current sharing among them (Fig. 36.35b). Supposing equal current share, the relation between the iL1 current and the output currents of each three-phase rectifier is iL1 = 4il1 = 4il2 = 4il3 = 4il4. Therefore, for the nth half-wave three-phase rectifier, since for n = 1 and n = 2, vc1 = vc11 and iL2 = 2il5 and for n = 3 and n = 4, vc1 = vc12 and iL2 = 2i16, the four sliding surfaces are (k1v = 1):
(36.124)
If an inexpensive analog controller is desired, the successive time derivatives of the reference voltage and the output current of Eq. (36.124) can be neglected (furthermore, their calculation is noise prone). Nonzero errors on the first, second, and third-order derivatives of the controlled variable will appear, worsening the response speed. However, the steady-state error is not affected.
To implement the four equations (36.124), the variables vc2,vc11,vc12,iO, il5,il6,il1,il2,il3 and il4 must be measured. Although this could be done easily, it is very convenient to further simplify the practical controller, keeping its complexity and cost at the level of linear controllers while maintaining the advantages of sliding mode. Therefore, the voltages vc11 and vc12 are assumed almost constant over one period of the filter input current, and vc11 = vc12 = vc2, meaning that il5 = il5 –io/2. With these assumptions, valid as the values of C' and C2 that are designed to provide an output voltage with very low ripple, the new sliding-mode functions are
These approximations disregard only the high-frequency content of vc11, vc12, il5, and il6 and do not affect the rectifier steady-state response, but the step response will be a little slower, although still much faster (150 ms, Fig. 36.39) than that obtained with linear controllers (280 ms, Fig. 36.38). Regardless of all the approximations, the low switching frequency of the rectifier would not allow the elimination of the dynamic errors. As a benefit of these approximations, the sliding-mode controller (Fig. 36.36a) will need only an extra current sensor (or a current observer) and an extra operational amplifier in comparison with linear controllers derived hereafter (which need four current sensors and six operational amplifiers). Compared to the total cost of the 12-pulse rectifier plus output filter, the control hardware cost is negligible in both the cases, even for medium-power applications.
FIGURE 36.39 Closed-loop constant-frequency sliding-mode controller performance: (a) 
, closed-loop currents and (b) closed output voltage Vl4 and erc2 output voltage error.
FIGURE 36.38 PI voltage controller performance: (a) 
, closed-loop currents and (b) closed output voltage Vc2 and lVc2 output voltage error.
FIGURE 36.36 (a) Sliding-mode controller block diagram and (b) linear control hierarchy for the 12-pulse rectifier.
Average Current-Mode Control of the 12-Pulse Rectifier
For comparison purposes, a PI-based controller structure is designed (Fig. 36.36b), considering that small mismatches of the line voltages or of the trigger angles can completely destroy the current share of the four paralleled rectifiers, inspite of the current equalizing inductances (l and l') Output voltage control sensing only the output voltage is, therefore, not feasible. Instead, the slow and fast manifold approach is selected. For the fast manifold, four internal current control loops guarantee the same dc current level in each three-phase rectifier and limit the short-circuit currents. For the output slow dynamics, an external cascaded output voltage control loop (Fig. 36.36b), measuring the voltage applied to the load, is the minimum.
For a straightforward design, given the much slower dynamics of the capacitor voltages compared to the input current, the PI current controllers are calculated as shown in Example 36.6, considering the capacitor voltage constant during a switching period, and rt ≈ 1 ω, the intrinsic resistance of the transformer windings, thyristor overlap, and inductor l. From Eq. (36.59), Tz = l/rt ≈ 0.044 s. From Eq. (36.62), with the common assumptions, Tp ≈ 016kI s (p = 3). These values guarantee a small overshoot (≈ 5%) and a current rise time of approximately T/3.
To design the external output voltage control loop, each current-controlled rectifier can be considered a voltage-controlled current source iL1 (s)/4 since each half-wave rectifier current response will be much faster than the filter output voltage response. Therefore, in the equivalent circuit of Fig. 36.35b, the current source iL1 (s) substitutes the input inductor, yielding the transfer function vc2 (s)/iL1 (s):
Given the real pole (pi = − 6.7) and two complex poles (p2,3 = − 6.65 ± j140.9) of Eq. (36.126), the PI voltage controller zero (1/Tzv = p1) can be chosen with a value equal to the transfer function real pole. The integral gain Tpv can be determined using a root-locus analysis to determine the maximum gain that still guarantees the stability of the closed-loop controlled system. The critical gain for the PI was found to be Tzv/Tpv ≈ 0.4, then Tpv > 0.37. The value Tpv ≈ 2 was selected to obtain weak oscillations, together with almost no overshoot.
The dynamic and steady-state responses of the output currents of the four rectifiers 
and the output voltage Vc2 were analyzed using a step input from 2 to 2.5 A applied at t = 1.1 s, for the currents, and from 40 to 50 V for the Vc2 voltage. The PI current controllers (Fig. 36.37) show good sharing of the total current, a slight overshoot (τ = 0.7) and response time 6.6ms (T/p).
FIGURE 36.37 PI current controller performance: (a) 
, closed-loop currents and (b) open-loop output voltage Vc2.
The open-loop voltage vc2 presents a rise time of 0.38 s. The PI voltage controller (Fig. 36.38) shows a response time of 0.4 s, no overshoot. The four 3-phase half-wave rectifier output currents (il1, il2, il3 and il4) present nearly the same transient and steady-state values, with no very high current peaks. These results validate the assumptions made in the PI design.
The closed-loop performance of the fixed-frequency sliding-mode controller (Fig. 36.39) shows that all the il1, il2, il3 and il4 currents are almost equal and have peak values only slightly higher than those obtained with the PI linear controllers. The output voltage presents a much faster response time (150 ms) than the PI linear controllers, negligible or no steady-state error, and no overshoot. From these waveforms, it can be concluded that the sliding-mode controller provides a much more effective control of the rectifier, as the output voltage response time is much lower than the obtained with PI linear controllers, without significantly increasing the thyristor currents, overshoots, or costs. Furthermore, sliding mode is an elegant way to know the variables to be measured and to design all the controller and the modulator electronics.
EXAMPLE 36.13 Sliding-mode control of pulse width modulation audio power amplifiers
Linear audio power amplifiers can be astonishing but have efficiencies as low as 15–20% with speech or music signals. To improve the efficiency of audio systems while preserving the quality, PWM switching power amplifiers, enabling the reduction of the power-supply cost, volume, and weight and compensating the efficiency loss of modern loudspeakers, are needed. Moreover, PWM amplifiers can provide a complete digital solution for audio power processing.
For high-fidelity systems, PWM audio amplifiers must present flat passbands of at least 16–20 kHz (± 0.5 dB), distortions less than 0.1% at the rated output power, fast dynamic response, and signal-to-noise ratios above 90 dB. This requires fast power semiconductors (usually metal-oxide semiconductor field effect transistor (MOS-FET) transistors), capable of switching at frequencies near 500 kHz, and fast nonlinear controllers to provide the precise and timely control actions needed to accomplish the mentioned requirements and to eliminate the phase delays in the LC output filter and loudspeakers.
A low-cost PWM audio power amplifier, able to provide over 80 W to 8ω loads (Vdd = 50 V), can be obtained using a half-bridge power inverter (switching at fPWM ≈ 450 kHz) coupled to an output filter for high-frequency attenuation (Fig. 36.40). A low-sensitivity, doubly terminated passive ladder (double LC), low-pass filter using fourth-order Chebyshev approximation polynomials is selected, given its ability to meet, while minimizing the number of inductors, the following requirements: passband edge frequency 21 kHz, passband ripple 0.5 dB, stopband edge frequency 300 kHz, and 90 dB minimum attenuation in the stop-band (L1 = 80 μH; L2 = 85 μH; C1 = 1.7 μF; C2 = 820 nF; R2 = 8 ω; r1 = 0.47 ω).
FIGURE 36.40 PWM audio amplifier with fourth-order Chebyshev low-pass output filter and loudspeaker load.
Modeling the PWM Audio Amplifier
The two half-bridge switches must always be in complementary states to avoid power supply internal short circuits. Their state can be represented by the time-dependent variable γ, which is γ = 1 when Ql is on and Q2 is off and is γ = –1 when Ql is off and Q2 is on.
Neglecting switch delays, on-state semiconductor voltage drops, auxiliary networks, and supposing small dead times, the half-bridge output voltage (vPWM) is vPWM = γVdd. Considering the state variables and circuit components of Fig. 36.40 and modeling the loudspeaker load as a disturbance represented by the current io (ensuring robustness to the frequency dependent impedance of the speaker), the switched state-space model of the PWM audio amplifier is
This model will be used to define the output voltage v0 controller.