Chapter 5. Low-Noise Amplifiers

Following our system- and architecture-level studies in previous chapters, we move farther down to the circuit level in this and subsequent chapters. Beginning with the receive path, we describe the design of low-noise amplifiers. While our focus is on CMOS implementations, most of the concepts can be applied to other technologies as well. The outline of the chapter is shown below.

5.1 General Considerations

As the first active stage of receivers, LNAs play a critical role in the overall performance and their design is governed by the following parameters.

Noise Figure

The noise figure of the LNA directly adds to that of the receiver. For a typical RX noise figure of 6 to 8 dB, it is expected that the antenna switch or duplexer contributes about 0.5 to 1.5 dB, the LNA about 2 to 3 dB, and the remainder of the chain about 2.5 to 3.5 dB. While these values provide a good starting point in the receiver design, the exact partitioning of the noise is flexible and depends on the performance of each stage in the chain. In modern RF electronics, we rarely design an LNA in isolation. Rather, we view and design the RF chain as one entity, performing many iterations among the stages.

To gain a better feel for a noise figure of 2 dB, consider the simple example in Fig. 5.1(a), where the noise of the LNA is represented by only a voltage source. Rearranging the input network as shown in Fig. 5.1(b), we have from Chapter 2

(5.1)-(5.2)

Figure 5.1 (a) LNA with input-referred noise voltage, (b) simplified circuit.

Thus, a noise figure of 2 dB with respect to a source impedance of 50Ω translates to , an extremely low value. For the gate-referred thermal noise voltage of a MOSFET, 4kTγ/g_m, to reach this value, the g_m must be as high as (29Ω)⁻¹ (if γ = 1). In this chapter, we assume R_S = 50Ω.

The low noise required of LNAs limits the choice of the circuit topology. This often means that only one transistor—usually the input device—can be the dominant contributor to NF, thus ruling out configurations such as emitter or source followers.

Gain

The gain of the LNA must be large enough to minimize the noise contribution of subsequent stages, specifically, the downconversion mixer(s). As described in Chapter 2, the choice of this gain leads to a compromise between the noise figure and the linearity of the receiver as a higher gain makes the nonlinearity of the subsequent stages more pronounced. In modern RF design, the LNA directly drives the downconversion mixer(s) with no impedance matching between the two. Thus, it is more meaningful and simpler to perform the chain calculations in terms of the voltage gain—rather than power gain—of the LNA.

It is important to note that the noise and IP₃ of the stage following the LNA are divided by different LNA gains. Consider the LNA/mixer cascade shown in Fig. 5.3(a), where the input-referred noise voltages are denoted by and and input noise currents are neglected. Assuming a unity voltage gain for the mixer for simplicity, we write the total output noise as . The overall noise figure is thus equal to

(5.7)-(5.8)

Figure 5.3 Appropriate choice of gain for referring (a) noise and (b) IP₃ of a mixer to LNA input.

In other words, for NF calculations, the noise of the second stage is divided by the gain from the input voltage source to the LNA output.

Now consider the same cascade repeated in Fig. 5.3(b) with the nonlinearity of the LNA expressed as a third-order polynomial. From Chapter 2, we have¹

(5.9)

In this case, α₁ denotes the voltage gain from the input of the LNA to its output. With input matching, we have R_in = R_S and α₁ = 2A_v1. That is, the mixer noise is divided by the lower gain and the mixer IP₃ by the higher gain—both against the designer’s wish.

Input Return Loss

The interface between the antenna and the LNA entails an interesting issue that divides analog designers and microwave engineers. Considering the LNA as a voltage amplifier, we may expect that its input impedance must ideally be infinite. From the noise point of view, we may precede the LNA with a transformation network to obtain minimum NF. From the signal power point of view, we may realize conjugate matching between the antenna and the LNA. Which one of these choices is preferable?

We make the following observations. (1) the (off-chip) band-select filter interposed between the antenna and the LNA is typically designed and characterized as a high-frequency device and with a standard termination of 50Ω. If the load impedance seen by the filter (i.e., the LNA input impedance) deviates from 50Ω significantly, then the pass-band and stopband characteristics of the filter may exhibit loss and ripple. (2) Even in the absence of such a filter, the antenna itself is designed for a certain real load impedance, suffering from uncharacterized loss if its load deviates from the desired real value or contains an imaginary component. Antenna/LNA co-design could improve the overall performance by allowing even non-conjugate matching, but it must be borne in mind that, if the antenna is shared with the transmitter, then its impedance must contain a negligible imaginary part so that it radiates the PA signal. (3) In practice, the antenna signal must travel a considerable distance on a printed-circuit board before reaching the receiver. Thus, poor matching at the RX input leads to significant reflections, an uncharacterized loss, and possibly voltage attenuation. For these reasons, the LNA is designed for a 50-Ω resistive input impedance. Since none of the above concerns apply to the other interfaces within the RX (e.g., between the LNA and the mixer or between the LO and the mixer), they are typically designed to maximize voltage swings rather than power transfer.

The quality of the input match is expressed by the input “return loss,” defined as the reflected power divided by the incident power. For a source impedance of R_S, the return loss is given by²

(5.10)

where Z_in denotes the input impedance. An input return loss of −10 dB signifies that one-tenth of the power is reflected—a typically acceptable value. Figure 5.4 plots contours of constant Γ in the Z_in plane. Each contour is a circle with its center shown. For example, Re{Z_in} = 1.22 × 50Ω = 61Ω and Im{Z_in} = 0.703 × 50Ω = 35.2Ω yield S₁₁ = −10 dB. In Problem 5.1, we derive the equations for these contours. We should remark that, in practice, a Γ of about −15 dB is targeted so as to allow margin for package parasitics, etc.

Figure 5.4 Constant-Γ contours in the input impedance plane.

Stability

Unlike the other circuits in a receiver, the LNA must interface with the “outside world,” specifically, a poorly-controlled source impedance. For example, if the user of a cell phone wraps his/her hand around the antenna, the antenna impedance changes.³ For this reason, the LNA must remain stable for all source impedances at all frequencies. One may think that the LNA must operate properly only in the frequency band of interest and not necessarily at other frequencies, but if the LNA begins to oscillate at any frequency, it becomes highly nonlinear and its gain is very heavily compressed.

A parameter often used to characterize the stability of circuits is the “Stern stability factor,” defined as

(5.11)

where Δ = S₁₁S₂₂ − S₁₂S₂₁. If K > 1 and Δ < 1, then the circuit is unconditionally stable, i.e., it does not oscillate with any combination of source and load impedances. In modern RF design, on the other hand, the load impedance of the LNA (the input impedance of the on-chip mixer) is relatively well-controlled, making K a pessimistic measure of stability. Also, since the LNA output is typically not matched to the input of the mixer, S₂₂ is not a meaningful quantity in such an environment.

The above example suggests that LNAs can be stabilized by maximizing their reverse isolation. As explained in Section 5.3, this point leads to two robust LNA topologies that are naturally stable and hence can be optimized for other aspects of their performance with no stability concerns. A high reverse isolation is also necessary for suppressing the LO leakage to the input of the LNA.

LNAs may become unstable due to ground and supply parasitic inductances resulting from the packaging (and, at frequencies of tens of gigahertz, the on-chip line inductances). For example, if the gate terminal of a common-gate transistor sees a large series inductance, the circuit may suffer from substantial feedback from the output to the input and become unstable at some frequency. For this reason, precautions in the design and layout as well as accurate package modeling are essential.

Linearity

In most applications, the LNA does not limit the linearity of the receiver. Owing to the cumulative gain through the RX chain, the latter stages, e.g., the baseband amplifiers or filters tend to limit the overall input IP₃ or P_1dB. We therefore design and optimize LNAs with little concern for their linearity.

An exception to the above rule arises in “full-duplex” systems, i.e., applications that transmit and receive simultaneously (and hence incorporate FDD). Exemplified by the CDMA systems studied in Chapter 3, full-duplex operation must deal with the leakage of the strong transmitted signal to the receiver. To understand this issue, let us consider the front end shown in Fig. 5.5, where a duplexer separates the TX and RX bands. Modeling the duplexer as a three-port network, we note that S₃₁ and S₂₁ represent the losses in the RX and TX paths, respectively, and are about 1 to 2 dB. Unfortunately, leakages through the filter and the package yield a finite isolation between ports 2 and 3, as characterized by an S₃₂ of about −50 dB. In other words, if the PA produces an average output power of +30 dBm (1 W), then the LNA experiences a signal level of −20 dBm in the TX band while sensing a much smaller received signal. Since the TX signal exhibits a variable envelope, its peak level may be about 2 dB higher. Thus, the receiver must remain uncompressed for an input level of −18 dBm. We must therefore choose a P_1dB of about −15 dBm to allow some margin.

Figure 5.5 TX leakage to RX in a full-duplex system.

Such a value for P_1dB may prove difficult to realize in a receiver. With an LNA gain of 15 to 20 dB, an input of −15 dBm yields an output of 0 to +5 dBm (632 to 1124 mV_pp), possibly compressing the LNA at its output. The LNA linearity is therefore critical. Similarly, the 1-dB compression point of the downconversion mixer(s) must reach 0 to +5 dBm. (The corresponding mixer IP₃ is roughly +10 to +15 dBm.) Thus, the mixer design also becomes challenging. For this reason, some CDMA receivers interpose an off-chip filter between the LNA and the mixer(s) so as to remove the TX leakage [1].

The linearity of the LNA also becomes critical in wideband receivers that may sense a large number of strong interferers. Examples include “ultra-wideband” (UBW), “software-defined,” and “cognitive” radios.

Bandwidth

The LNA must provide a relatively flat response for the frequency range of interest, preferably with less than 1 dB of gain variation. The LNA −3-dB bandwidth must therefore be substantially larger than the actual band so that the roll-off at the edges remains below 1 dB.

In order to quantify the difficulty in achieving the necessary bandwidth in a circuit, we often refer to its “fractional bandwidth,” defined as the total −3-dB bandwidth divided by the center frequency of the band. For example, an 802.11g LNA requires a fractional bandwidth greater than 80 MHz/2.44 GHz = 0.0328.

LNA designs that must achieve a relatively large fractional bandwidth may employ a mechanism to switch the center frequency of operation. Depicted in Fig. 5.7(a) is an example, where an additional capacitor, C₂, can be switched into the tank, thereby changing the center frequency from to [Fig. 5.7(b)]. We return to this concept in Section 5.5.

Figure 5.7 (a) Band switching, (b) resulting frequency response.

Power Dissipation

The LNA typically exhibits a direct trade-off among noise, linearity, and power dissipation. Nonetheless, in most receiver designs, the LNA consumes only a small fraction of the overall power. In other words, the circuit’s noise figure generally proves much more critical than its power dissipation.

5.2 Problem of Input Matching

As explained in Section 5.1, LNAs are typically designed to provide a 50-Ω input resistance and negligible input reactance. This requirement limits the choice of LNA topologies. In other words, we cannot begin with an arbitrary configuration, design it for a certain noise figure and gain, and then decide how to create input matching.

Let us first consider the simple common-source stage shown in Fig. 5.8, where C_F represents the gate-drain overlap capacitance. At very low frequencies, R_D is much smaller than the impedances of C_F and C_L and the input impedance is roughly equal to [(C_GS + C_F)s]⁻¹. At very high frequencies, C_F shorts the gate and drain terminals of M₁, yielding an input resistance equal to R_D||(1/g_m). More generally, the reader can prove that the real and imaginary parts of the input admittance are, respectively, equal to

(5.15)

(5.16)

Figure 5.8 Input admittance of a CS stage.

Is it possible to select the circuit parameters so as to obtain Re{Y_in} = 1/(50Ω)? For example, if C_F = 10 fF, C_L = 30 fF, g_mR_D = 4, and R_D = 100Ω, then Re{Y_in} = (7.8 kΩ)⁻¹ at 5 GHz, far from (50Ω)⁻¹. This is because C_F introduces little feedback at this frequency.

Can we employ simple resistive termination at the input? Illustrated in Fig. 5.9(a), such a topology is designed in three steps: (1) M₁ and R_D provide the required noise figure and gain, (2) R_P is placed in parallel with the input to provide Re{Z_in} = 50Ω, and (3) an inductor is interposed between R_S and the input to cancel Im{Z_in}. Unfortunately, as explained in Chapter 2, the termination resistor itself yields a noise figure of 1 + R_S/R_P. To calculate the noise figure at low frequencies, we can utilize Friis’ equation⁴ or simply treat the entire LNA as one circuit and, from Fig. 5.9(b), express the total output noise as

(5.17)

where channel-length modulation is neglected. Since the voltage gain from V_in to V_out in Fig. 5.9(a) is equal to −[R_P/(R_P + R_S)]g_mR_D, the noise figure is given by

(5.18)

Figure 5.9 (a) Use of resistive termination for matching, (b) simplified circuit.

For R_P ≈ R_S, the NF exceeds 3 dB—perhaps substantially.

The key point in the foregoing study is that the LNA must provide a 50-Ω input resistance without the thermal noise of a physical 50-Ω resistor. This becomes possible with the aid of active devices.

In summary, proper input (conjugate) matching of LNAs requires certain circuit techniques that yield a real part of 50Ω in the input impedance without the noise of a 50-Ω resistor. We study such techniques in the next section.

5.3 LNA Topologies

Our preliminary studies thus far suggest that the noise figure, input matching, and gain constitute the principal targets in LNA design. In this section, we present a number of LNA topologies and analyze their behavior with respect to these targets. Table 5.1 provides an overview of these topologies.

Table 5.1 Overview of LNA topologies.

5.3.1 Common-Source Stage with Inductive Load

As noted in Section 5.1, a CS stage with resistive load (Fig. 5.8) proves inadequate because it does not provide proper matching. Furthermore, the output node time constant may prohibit operation at high frequencies. In general, the trade-off between the voltage gain and the supply voltage in this circuit makes it less attractive as the latter scales down with technology. For example, at low frequencies,

(5.27)-(5.29)

where V_RD denotes the dc voltage drop across R_D and is limited by V_DD. With channel-length modulation, the gain is even lower.

In order to circumvent the trade-off expressed by Eq. (5.29) and also operate at higher frequencies, the CS stage can incorporate an inductive load. Illustrated in Fig. 5.11(a), such a topology operates with very low supply voltages because the inductor sustains a smaller dc voltage drop than a resistor does. (For an ideal inductor, the dc drop is zero.) Moreover, L₁ resonates with the total capacitance at the output node, affording a much higher operation frequency than does the resistively-loaded counterpart of Fig. 5.8.

Figure 5.11 (a) Inductively-loaded CS stage, (b) input impedance in the presence of C_F, (c) equivalent circuit.

How about the input matching? We consider the more complete circuit shown in Fig. 5.11(b), where C_F denotes the gate-drain overlap capacitance. Ignoring the gate-source capacitance of M₁ for now, we wish to compute Z_in. We redraw the circuit as depicted in Fig. 5.11(c) and note that the current flowing through the output parallel tank is equal to I_X − g_mV_X. In this case, the inductor loss is modeled by a series resistance, R_S, because this resistance varies much less with frequency than the equivalent parallel resistance does.⁵ The tank impedance is given by

(5.30)

and the tank voltage by (I_X − g_mV_X)Z_T. Adding the voltage drop across C_F to the tank voltage, we have

(5.31)

Substitution of Z_T from (5.30) gives

(5.32)

For s = jω,

(5.33)

Since the real part of a complex fraction (a + jb)/(c + jd) is equal to (ac + bd)/(c² + d²), we have

(5.34)

where D is a positive quantity. It is thus possible to select the values so as to obtain Re{Z_in} = 50Ω.

While providing the possibility of Re{Z_in} = 50Ω at the frequency of interest, the feedback capacitance in Fig. 5.11(b) gives rise to a negative input resistance at other frequencies, potentially causing instability. To investigate this point, let us rewrite Eq. (5.34) as

(5.35)

We note that the numerator falls to zero at a frequency given by

(5.36)

Thus, at this frequency (if it exists), Re{Z_in} changes sign. For example, if C_F = 10fF, C₁ = 30fF, g_m = (20Ω)⁻¹, L₁ = 5 nH, and R_S = 20Ω, then g_mL₁ dominates in the numerator, yielding and hence ω₁ ≈ 2π × (11.3 GHz).

It is possible to “neutralize” the effect of C_F in some frequency range through the use of parallel resonance (Fig. 5.12), but, since C_F is relatively small, L_F must assume a large value, thereby introducing significant parasitic capacitances at the input and output (and even between the input and output) and degrading the performance. For these reasons, this topology is rarely used in modern RF design.

Figure 5.12 Neutralization of C_F by L_F.

5.3.2 Common-Source Stage with Resistive Feedback

If the frequency of operation remains an order of magnitude lower than the f_T of the transistor, the feedback CS stage depicted in Fig. 5.13(a) may be considered as a possible candidate. Here, M₂ operates as a current source and R_F senses the output voltage and returns a current to the input. We wish to design this stage for an input resistance equal to R_S and a relatively low noise figure.

If channel-length modulation is neglected, we have from Fig. 5.13(b),

(5.37)

because R_F is simply in series with an ideal current source and M₁ appears as a diode-connected device. We must therefore choose

(5.38)

Figure 5.13 (a) CS stage with resistive feedback, (b) simplified circuit.

Figure 5.13(b) also implies that the small-signal drain current of M₁, g_m1V_X, entirely flows through R_F, generating a voltage drop of g_m1V_XR_F. It follows that

(5.39)

and hence

(5.40)-(5.41)

In practice, R_F R_S, and the voltage gain from V_in to V_out in Fig. 5.13(a) is equal to

(5.42)-(5.43)

In contrast to the resistively-loaded CS stage of Fig. 5.8, this circuit does not suffer from a direct trade-off between gain and supply voltage because R_F carries no bias current.

Let us determine the noise figure of the circuit, assuming that g_m1 = 1/R_S. We first compute the noise contributions of R_F, M₁, and M₂ at the output. From Fig. 5.14(a), the reader can show the noise of R_F appears at the output in its entirety:

(5.44)

Figure 5.14 Effect of noise of (a) R_F and (b) M₁ in CS stage.

The noise currents of M₁ and M₂ flow through the output impedance of the circuit, R_out, as shown in Fig. 5.14(b). The reader can prove that

(5.45)-(5.46)

It follows that

(5.47)

The noise of R_S is multiplied by the gain when referred to the output, and the result is divided by the gain when referred to the input. We thus have

(5.48)-(5.50)

For γ ≈ 1, the NF exceeds 3 dB even if 4R_S/R_F + γg_m2R_S 1.

5.3.3 Common-Gate Stage

The low input impedance of the common-gate (CG) stage makes it attractive for LNA design. Since a resistively-loaded stage suffers from the same gain-headroom trade-off as its CS counterpart, we consider only a CG circuit with inductive loading [Fig. 5.16(a)]. Here, L₁ resonates with the total capacitance at the output node (including the input capacitance of the following stage), and R₁ represents the loss of L₁. If channel-length modulation and body effect are neglected, R_in = 1/g_m. Thus, the dimensions and bias current of M₁ are chosen so as to yield g_m = 1/R_S = (50Ω)⁻¹. The voltage gain from X to the output node at the output resonance frequency is then equal to

(5.53)-(5.54)

and hence V_out/V_in = R₁/(2R_S).

Figure 5.16 (a) CG stage, (b) effect of noise of M₁.

Let us now determine the noise figure of the circuit under the condition g_m = 1/R_S and at the resonance frequency. Modeling the thermal noise of M₁ as a voltage source in series with its gate, [Fig. 5.16(b)], and multiplying it by the gain from the gate of M₁ to the output, we have

(5.55)-(5.56)

The output noise due to R₁ is simply equal to 4kTR₁. To obtain the noise figure, we divide the output noise due to M₁ and R₁ by the gain and 4kTR_S and add unity to the result:

(5.57)-(5.58)

Even if 4R_S/R₁ 1 + γ, the NF still reaches 3 dB (with γ ≈ 1), a price paid for the condition g_m = 1/R_S. In other words, a higher g_m yields a lower NF but also a lower input resistance. In Problem 5.8, we show that the NF can be lower if some impedance mismatch is permitted at the input.

In deep-submicron CMOS technologies, channel-length modulation significantly impacts the behavior of the CG stage. As shown in Fig. 5.19, the positive feedback through r_O raises the input impedance. Since the drain-source current of M₁ (without r_O) is equal to −g_mV_X (if body effect is neglected), the current flowing through r_O is given by I_X − g_mV_X, yielding a voltage drop of r_O(I_X − g_mV_X) across it. Also, I_X flows through the output tank, producing a voltage of I_XR₁ at the resonance frequency. Adding this voltage to the drop across r_O and equating the result to V_X, we obtain

(5.63)

Figure 5.19 Input impedance of CG stage in the presence of r_O.

That is,

(5.64)

If the intrinsic gain, g_mr_O, is much greater than unity, then V_X/I_X ≈ 1/g_m + R₁/(g_mr_O). However, in today’s technology, g_mr_O hardly exceeds 10. Thus, the term R₁/(g_mr_O) may become comparable with or even exceed the term 1/g_m, yielding an input resistance substantially higher than 50Ω.

With the strong effect of R₁ on R_in, we must equate the actual input resistance to R_S to guarantee input matching:

(5.65)

The reader can prove that the voltage gain of the CG stage shown in Fig. 5.16(a) with a finite r_O is expressed as

(5.66)

which, from Eq. (5.65), reduces to

(5.67)

This is a disturbing result! If r_O and R₁ are comparable, then the voltage gain is on the order of g_mr_O/4, a very low value.

In summary, the input impedance of the CG stage is too low if channel-length modulation is neglected and too high if it is not! A number of circuit techniques have been introduced to deal with the former case (Section 5.3.5), but in today’s technology, we face the latter case.

In order to alleviate the above issue, the channel length of the transistor can be increased, thus reducing channel-length modulation and raising the achievable g_mr_O. Since the device width must also increase proportionally so as to retain the transconductance value, the gate-source capacitance of the transistor rises considerably, degrading the input return loss.

Cascode CG Stage

An alternative approach to lowering the input impedance is to incorporate a cascode device as shown in Fig. 5.21. Here, the resistance seen looking into the source of M₂ is given by Eq. (5.64):

(5.68)

Figure 5.21 Cascode CG stage.

This load resistance is now transformed to a lower value by M₁, again according to (5.64):

(5.69)

If g_mr_O 1, then

(5.70)

Since R₁ is divided by the product of two intrinsic gains, its effect remains negligible. Similarly, the third term is much less than the first if g_m1 and g_m2 are roughly equal. Thus, R_in ≈ 1/g_m1.

The addition of the cascode device entails two issues: the noise contribution of M₂ and the voltage headroom limitation due to stacking two transistors. To quantify the former, we consider the equivalent circuit shown in Fig. 5.22(a), where R_S ( = 1/g_m1) and M₁ are replaced with an output resistance equal to 2r_O1 (why?), and C_X = C_DB1 + C_GD1 + C_SB2. For simplicity, we have also replaced the tank with a resistor R₁, i.e., the output node has a broad bandwidth. Neglecting the gate-source capacitance, channel-length modulation, and body effect of M₂, we express the transfer function from V_n2 to the output at the resonance frequency as

(5.71)-(5.72)

Figure 5.22 (a) Cascode transistor noise, (b) output contribution as a function of frequency.

Figure 5.22(b) plots the frequency response, implying that the noise contribution of M₂ is negligible for frequencies up to the zero frequency, (2r_O1C_X)⁻¹, but begins to manifest itself thereafter. Since C_X is comparable with C_GS and 2r_O1 1/g_m, we note that (2r_O1C_X)⁻¹ g_m/C_GS (≈ ω_T). That is, the zero frequency is much lower than the f_T of the transistors, making this effect potentially significant.

The second issue stemming from the cascode device relates to the limited voltage headroom. To quantify this limitation, let us determine the required or allowable values of V_b1 and V_b2 in Fig. 5.21. Since the drain voltage of M₂ begins at V_DD and can swing below its gate voltage by as much as V_TH2 while keeping M₂ in saturation, we can simply choose V_b2 = V_DD. Now, V_X = V_DD − V_GS2, allowing a maximum value of V_DD − V_GS2 + V_TH1 for V_b1 if M₁ must remain saturated. Consequently, the source voltage of M₁ cannot exceed V_DD − V_GS2 − (V_GS1 − V_TH1). We say the two transistors consume a voltage headroom of one V_GS plus one overdrive (V_GS1 − V_TH1).

It may appear that, so long as V_DD > V_GS2 + (V_GS1 − V_TH1), the circuit can be properly biased, but how about the path from the source of M₁ to ground? In comparison with the CG stages in Fig. 5.17, the cascode topology consumes an additional voltage headroom of V_GS1 − V_TH1, leaving less for the biasing transistor or resistor and hence raising their noise contribution. For example, suppose I_D1 = I_D2 = 2 mA. Since g_m1 = (50Ω)⁻¹ = 2I_D/(V_GS1 − V_TH1), we have V_GS1 − V_TH1 = 200 mV. Also assume V_GS2 ≈ 500 mV. Thus, with V_DD = 1 V, the voltage available for a bias resistor, R_B, tied between the source of M₁ and ground cannot exceed 300 mV/2mA = 150Ω. This value is comparable with R_S = 50Ω and degrades the gain and noise behavior of the circuit considerably.

In order to avoid the noise-headroom trade-off imposed by R_B, and also cancel the input capacitance of the circuit, CG stages often employ an inductor for the bias path. Illustrated in Fig. 5.24 with proper biasing for the input transistor, this technique minimizes the additional noise due to the biasing element (L_B) and significantly improves the input matching. In modern RF design, both L_B and L₁ are integrated on the chip.

Figure 5.24 Biasing of cascode CG stage.

Design Procedure

With so many devices present in the circuit of Fig. 5.24, how do we begin the design? We describe a systematic procedure that provides a “first-order” design, which can then be refined and optimized.

The design procedure begins with two knowns: the frequency of operation and the supply voltage. In the first step, the dimensions and bias current of M₁ must be chosen such that a transconductance of (50Ω)⁻¹ is obtained. The length of the transistor is set to the minimum allowable by the technology, but how should the width and the drain current be determined?

Using circuit simulations, we plot the transconductance and f_T of an NMOS transistor with a given width, W₀, as a function of the drain current. For long-channel devices, , but submicron transistors suffer from degradation of the mobility with the vertical field in the channel, exhibiting the saturation behavior shown in Fig. 5.25. To avoid excessive power consumption, we select a bias current, I_D0, that provides 80 to 90% of the saturated g_m. That is, the combination of W₀ and I_D0 (the “current density”) is nearly optimum in terms of speed (transistor capacitances) and power consumption.

Figure 5.25 Behavior of g_m and f_T as a function of drain current.

With W₀ and I_D0 known, any other value of transconductance can be obtained by simply scaling the two proportionally. The reader can prove that if W₀ and I_D0 scale by a factor of α, then so does g_m, regardless of the type and behavior of the transistor. We thus arrive at the required dimensions and bias current of M₁ (for 1/g_m1 = 50Ω), which in turn yield its overdrive voltage.

In the second step, we compute the necessary value of L_B in Fig. 5.24. As shown in Fig. 5.26, the input of the circuit sees a pad capacitance to the substrate.⁶ Thus, L_B must resonate with C_pad + C_SB1 + C_GS1 and its own capacitance at the frequency of interest. (Here, R_p models the loss of L_B.) Since the parasitic capacitance of L_B is not known a priori, some iteration is required. (The design and modeling of spiral inductors are described in Chapter 7.)

Figure 5.26 Effect of pad capacitance on CG stage.

Does L_B affect the performance of the circuit at resonance? Accompanying L_B is the parallel equivalent resistance R_p = QL_Bω, which contributes noise and possibly attenuates the input signal. Thus, R_p must be at least ten times higher than R_S = 50Ω. In other words, if the total capacitance at the input is so large as to dictate an excessively small inductor and R_p, then the noise figure is quite high. This situation may arise only at frequencies approaching the f_T of the technology.

In the third step, the bias of M₁ is defined by means of M_B and I_REF in Fig. 5.24. For example, W_B = 0.2W₁ and I_REF = 0.2I_D1 so that the bias branch draws only one-fifth of the current of the main branch.⁷ Capacitor C_B provides a sufficiently low impedance (much less than 50Ω) from the gate of M₁ to ground and also bypasses the noise of M_B and I_B to ground. The choice of a solid, low-inductance ground is critical here because the high-frequency performance of the CG stage degrades drastically if the impedance seen in series with the gate becomes comparable with R_S.

Next, the width of M₂ in Fig. 5.24 must be chosen (the length is the minimum allowable value). With the bias current known (I_D2 = I_D1), if the width is excessively small, then V_GS2 may be so large as to drive M₁ into the triode region. On the other hand, as W₂ increases, M₂ contributes an increasingly larger capacitance to node X while its g_m reaches a nearly constant value (why?). Thus, the optimum width of M₂ is likely to be near that of M₁, and that is the initial choice. Simulations can be used to refine this choice, but in practice, even a twofold change from this value negligibly affects the performance.

In order to minimize the capacitance at node X in Fig. 5.24, transistors M₁ and M₂ can be laid out such that the drain area of the former is shared with the source area of the latter. Furthermore, since no other connection is made to this node, the shared area need not accommodate contacts and can therefore be minimized. Depicted in Fig. 5.27 and feasible only if W₁ = W₂, such a structure can be expanded to one with multiple gate fingers.

Figure 5.27 Layout of cascode devices.

In the last step, the value of the load inductor, L₁, must be determined (Fig. 5.24). In a manner similar to the choice of L_B, we compute L₁ such that it resonates with C_GD2 + C_DB2, the input capacitance of the next stage, and its own capacitance. Since the voltage gain of the LNA is proportional to R₁ = QL₁ω, R₁ must be sufficiently large, e.g., 500 to 1000Ω. This condition is met in most designs without much difficulty.

The design procedure outlined above leads to a noise figure around 3 dB [Eq. (5.58)] and a voltage gain, V_out/V_in = R₁/(2R_S), of typically 15 to 20 dB. If the gain is too high, i.e., if it dictates an unreasonably high mixer IP₃, then an explicit resistor can be placed in parallel with R₁ to obtain the required gain. As studied in Section 5.7, this LNA topology displays a high IIP₃, e.g., +5to +10 dBm.

5.3.4 Cascode CS Stage with Inductive Degeneration

Our study of the CS stage of Fig. 5.11(a) indicates that the feedback through the gate-drain capacitance many be exploited to produce the required real part, but it also leads to a negative resistance at lower frequencies. We must therefore seek a topology in which the input is “isolated” from the inductive load and the input resistance is established by means other than C_GD.

Let us first develop the latter concept. As mentioned in Section 5.2, we must employ active devices to provide a 50-Ω input resistance without the noise of a 50-Ω resistor. One such method employs a CS stage with inductive degeneration, as shown in Fig. 5.31(a). We first compute the input impedance of the circuit while neglecting C_GD and C_SB.⁹ Flowing entirely through C_GS1, I_X generates a gate-source voltage of I_X/(C_GS1s) and hence a drain current of g_mI_X/(C_GS1s). These two currents flow through L₁, producing a voltage

(5.76)

Figure 5.31 (a) Input impedance of inductively-degenerated CS stage, (b) use of bond wire for degeneration.

Since V_X = V_GS1 + V_P, we have

(5.77)

Interestingly, the input impedance contains a frequency-independent real part given by g_mL₁/C_GS1. Thus, the third term can be chosen equal to 50Ω.

The third term in Eq. (5.77) carries a profound meaning: since g_m/C_GS1 ≈ ω_T(= 2πf_T), the input resistance is approximately equal to L₁ω_T and directly related to the f_T of the transistor. For example, in 65-nm technology, ω_T ≈ 2π × (160 GHz), dictating L₁ ≈ 50 pH (!) for a real part of 50Ω.

In practice, the degeneration inductor is often realized as a bond wire with the reasoning that the latter is inevitable in packaging and must be incorporated in the design. To minimize the inductance, a “downbond” can directly connect the source pad to a ground plane in the package [Fig. 5.31(b)], but even this geometry yields a value in the range of 0.5 to 1 nH—far from the 50-pH amount calculated above! That is, the input resistance provided by modern MOSFETs tends to be substantially higher than 50Ω if a bond wire inductance is used.¹⁰

How do we obtain a 50-Ω resistance with L₁ ≈ 0.5 nH? At operation frequencies far below f_T of the transistor, we can reduce the f_T. This is accomplished by increasing the channel length or simply placing an explicit capacitor in parallel with C_GS. For example, if L₁ = 0.5 nH, then f_T must be lowered to about 16 GHz.

Effect of Pad Capacitance

In addition to C_GD, the input pad capacitance of the circuit also lowers the input resistance. To formulate this effect, we construct the equivalent circuit shown in Fig. 5.33(a), where C_GS1, L₁, and R₁ represent the three terms in Eq. (5.77), respectively. Denoting the series combination jL₁ω − j/(C_GS1ω) by jX₁ and −j/(C_padω) by jX₂, we first transform jX₁ + R₁ to a parallel combination [Fig. 5.33(b)]. From Chapter 2,

(5.82)

Figure 5.33 (a) Equivalent circuit for inclusion of pad capacitance, (b) simplified circuit of (a), (c) simplified circuit of (b).

We now merge the two parallel reactances into jX₁X₂/(X₁ + X₂) and transform the resulting circuit to a series combination [Fig. 5.33(c)], where

(5.83)-(5.84)

In most cases, we can assume L₁ω 1/(C_GS1ω) + 1/(C_padω) at the frequency of interest, obtaining

(5.85)

For example, if C_GS1 ≈ C_pad, then the input resistance falls by a factor of four.

We can now make two observations. First, the effect of the gate-drain and pad capacitance suggests that the transistor f_T need not be reduced so much as to create R₁ = 50Ω. Second, since the degeneration inductance necessary for Re{Z_in} = 50Ω is insufficient to resonate with C_GS1 + C_pad, another inductor must be placed in series with the gate as shown in Fig. 5.34, where it is assumed L_G is off-chip.

Figure 5.34 Addition of L_G for input matching.

NF Calculation

Let us now compute the noise figure of the CS circuit, excluding the effect of channel-length modulation, body effect, C_GD, and C_pad for simplicity (Fig. 5.35). The noise of M₁ is represented by I_n1. For now, we assume the output of interest is the current I_out. We have

(5.86)

Figure 5.35 Equivalent circuit for computation of NF.

Also, since L₁ sustains a voltage of L₁s(I_out + V₁C_GS1s), a KVL around the input loop yields

(5.87)

Substituting for V₁ from (5.86) gives

(5.88)

The input network is designed to resonate at the frequency of interest, ω₀. That is, and hence, (L₁ + L_G)C_GS1s² + 1 = 0 at s = jω₀. We therefore obtain

(5.89)

The coefficient of I_out represents the transconductance gain of the circuit (including R_S):

(5.90)

Now, recall from Eq. (5.77) that, for input matching, g_mL₁/C_GS1 = R_S. Since g_m/C_GS1 ≈ ω_T,

(5.91)

Interestingly, the transconductance of the circuit remains independent of L₁, L_G, and g_m so long as the input is matched.

Setting V_in to zero in Eq. (5.89), we compute the output noise due to M₁:

(5.92)

which, for g_mL₁/C_GS1 = R_S, reduces to

(5.93)

and hence

(5.94)

Dividing the output noise current by the transconductance of the circuit and by 4kTR_S and adding unity to the result, we arrive at the noise figure of the circuit [2]:

(5.95)

It is important to bear in mind that this result holds only at the input resonance frequency and if the input is matched.

The above example suggests that maximizing L_G can minimize the noise figure by providing voltage gain from V_in to the gate of M₁. The reader can prove that this gain is given by

(5.96)

Note that L_Gω₀/R_S represents the Q of the series combination of L_G and R_S. Indeed, as explained below, the design procedure begins with the maximum available value of L_G (typically an off-chip inductor) whose parasitic capacitances are negligible. The voltage gain in the input network (typically as high as 6 dB) does lower the IP₃ and P_1dB of the LNA, but the resulting values still prove adequate in most applications.

We now turn our attention to the output node of the circuit. As explained in Section 5.3.1, an inductive load attached to a common-source stage introduces a negative resistance due to the feedback through C_GD. We therefore add a cascode transistor in the output branch to suppress this effect. Figure 5.37 shows the resulting circuit, where R₁ models the loss of L_D. The voltage gain is equal to the product of the circuit’s transconductance [Eq. (5.91)] and the load resistance, R₁:¹²

(5.97)-(5.98)

Figure 5.37 Inductively-degenerated cascode CS LNA.

The effect of C_GD1 on the input impedance may still require attention because the impedance seen at the source of M₂, R_X, rises sharply at the output resonance frequency. From Eq. (5.64),

(5.99)

Using the transconductance expression in (5.90) and V_G/V_in in (5.96), we compute the voltage gain from the gate to the drain of M₁:

(5.100)

Since R_S L₁ω₀ (why?) and the second fraction is typically near or higher than unity, C_GD1 may suffer from substantial Miller multiplication at the output resonance frequency.

In the foregoing noise figure calculation, we have not included the noise contribution of M₂. As formulated for the cascode CG stage in Section 5.3.3, the noise of the cascode device begins to manifest itself if the frequency of operation exceeds roughly (2r_O1C_X)⁻¹.

Design Procedure

Having developed a good understanding of the cascode CS LNA of Fig. 5.37, we now describe a procedure for designing the circuit. The reader is encouraged to review the CG design procedure. The procedure begins with four knowns: the frequency of operation, ω₀, the value of the degeneration inductance, L₁, the input pad capacitance, C_pad, and the value of the input series inductance, L_G. Each of the last three knowns is somewhat flexible, but it is helpful to select some values, complete the design, and iterate if necessary.

Governing the design are the following equations:

(5.102)-(5.103)

With ω₀ known, C_GS1 is calculated from (5.102), and ω_T and g_m (=ω_TC_GS1) from (5.103). We then return to the plots of g_m and f_T in Fig. 5.25 and determine whether a transistor width can yield the necessary g_m and f_T simultaneously. In deep-submicron technologies and for operation frequencies up to a few tens of gigahertz, the f_T is likely to be “too high,” but the pad capacitance alleviates the issue by transforming the input resistance to a lower value. If the requisite f_T is quite low, a capacitance can be added to C_pad. On the other hand, if the pad capacitance is so large as to demand a very high f_T, the degeneration inductance can be increased.

In the next step, the dimensions of the cascode device are chosen equal to those of the input transistor. As mentioned in Section 5.3.3 for the cascode CG stage, the width of the cascode device only weakly affects the performance. Also, the layout of M₁ and M₂ can follow the structure shown in Fig. 5.27 to minimize the capacitance at node X.

The design procedure now continues with selecting a value for L_D such that it resonates at ω₀ with the drain-bulk and drain-gate capacitances of M₂, the input capacitance of the next stage, and the inductors’s own parasitic capacitance. If the parallel equivalent resistance of L_D results in a gain, R₁/(2L₁ω₀), greater than required, then an explicit resistor can be placed in parallel with L_D to lower the gain and widen the bandwidth.

In the last step of the design, we must examine the input match. Due to the Miller multiplication of C_GD1 (Example 5.12), it is possible that the real and imaginary parts depart from their ideal values, necessitating some adjustment in L_G.

The foregoing procedure typically leads to a design with a relatively low noise figure, around 1.5 to 2 dB—depending on how large L_G can be without displaying excessive parasitic capacitances. Alternatively, the design procedure can begin with known values for NF and L₁ and the following two equations:

(5.104)-(5.105)

where the noise of the cascode transistor and the load is neglected. The necessary values of ω_T and g_m1 can thus be computed (g_m1/C_GS1 ≈ ω_T). If the plots in Fig. 5.25 indicate that the device f_T is too high, then additional capacitance can be placed in parallel with C_GS1. Finally, L_G is obtained from Eq. (5.102). (If advanced packaging minimizes inductances, then L₁ can be integrated on the chip and assume a small value.)

The overall LNA appears as shown in Fig. 5.38, where the antenna is capacitively tied to the receiver to isolate the LNA bias from external connections. The bias current of M₁ is established by M_B and I_B, and resistor R_B and capacitor C_B isolate the signal path from the noise of I_B and M_B. The source-bulk capacitance of M₁ and the capacitance of the pad at the source of M₁ may slightly alter the input impedance and must be included in simulations.

Figure 5.38 Inductively-degenerated CS stage with pads and bias network.

The choice between the CG and CS LNA topologies is determined by the trade-off between the robustness of the input match and the lower bound on the noise figure. The former provides an accurate input resistance that is relatively independent of package parasitics, whereas the latter exhibits a lower noise figure. We therefore select the CG stage if the required LNA noise figure can be around 4 dB, and the CS stage for lower values.

An interesting point of contrast between the CG and CS LNAs relates to the contribution of the load resistor, R₁, to the noise figure. Equation (5.58) indicates that in a CG stage, this contribution, 4R_S/R₁, is equal to 4 divided by the voltage gain from the input source to the output. Thus, for a typical gain of 10, this contribution reaches 0.4, a significant amount. For the inductively-degenerated CS stage, on the other hand, Eq. (5.101) reveals that the contribution is equal to 4R_S/R₁ multiplied by (ω₀/ω_T)². Thus, for operation frequencies well below the f_T of the transistor, the noise contribution of R₁ becomes negligible.

5.3.5 Variants of Common-Gate LNA

As revealed by Eq. (5.57), the noise figure and input matching of the CG stage are inextricably related if channel-length modulation is negligible, a common situation in older CMOS technologies. For this reason, a number of efforts have been made to add another degree of freedom to the design so as to avoid this relationship. In this section, we describe two such examples.

Figure 5.43 shows a topology incorporating voltage-voltage feedback [3].¹³ The block having a gain (or attenuation factor) of α senses the output voltage and subtracts a fraction thereof from the input. (Note that M₁ operates as a subtractor because I_D1 ∝ V_F − V_in.) The loop transmission can be obtained by breaking the loop at the gate of M₁ and is equal to g_mZ_L · α.¹⁴ If channel-length modulation and body effect are neglected, the closed-loop input impedance is equal to the open-loop input impedance, 1/g_m, multiplied by 1+g_mZ_Lα:

(5.113)

Figure 5.43 CG LNA with feedback.

At resonance,

(5.114)

The input resistance can therefore be substantially higher than 1/g_m, but how about the noise figure? We first calculate the gain with the aid of the circuit depicted in Fig. 5.44(a). The voltage gain from X to the output is equal to the open-loop gain, g_mR₁, divided by 1 + αg_mR₁ (at the resonance frequency). Thus,

(5.115)-(5.116)

Figure 5.44 (a) Input impedance and (b) noise behavior of CG stage with feedback.

which reduces to R₁/(2R_S) if the input is matched.

For output noise calculation, we construct the circuit of Fig. 5.44(b), where V_n1 represents the noise voltage of M₁ and noise of the feedback circuit is neglected. Since R_S carries a current equal to −V_n,out/R₁ (why?), we recognize that V_GS1 = αV_n,out + V_n1 + V_n,outR_S/R₁. Equating g_mV_GS1 to −V_n,out/R₁ yields

(5.117)

and hence

(5.118)

The noise current of R₁ is multiplied by the output impedance of the circuit, R_out. The reader can show that R_out is equal to R₁ in parallel with (1 + g_mR_S)/(αg_m). Summing this noise and that of M₁, dividing the result by the square of (5.116) and 4kTR_S, and assuming the input is matched, we have

(5.119)

That is, the NF can be lowered by raising g_m. Note that this result is identical to that expressed by Eq. (5.57) for the simple CG stage, except that g_mR_S need not be equal to unity here. For example, if g_mR_S = 4 and γ = 1, then the first two terms yield a noise figure of 0.97 dB. In Problem 5.15 we reexamine these results if channel-length modulation is not neglected.

Another variant of the CG LNA employs feedforward to avoid the tight relationship between the input resistance and the noise figure [4]. Illustrated in Fig. 5.45(a), the idea is to amplify the input by a factor of −A and apply the result to the gate of M₁. For an input voltage change of ΔV, the gate-source voltage changes by −(1 + A)ΔV and the drain current by −(1 + A)g_mΔV. Thus, the g_m is “boosted” by a factor of 1 + A [4], lowering the input impedance to R_in = [g_m(1 + A)]⁻¹ and raising the voltage gain from the source to the drain to (1 + A)g_mR₁ (at resonance).

Figure 5.45 (a) CG stage with feedforward, (b) calculation of NF.

We now compute the noise figure with the aid of the equivalent circuit shown in Fig. 5.45(b). Since the current flowing through R_S is equal to −V_n,out/R₁, the source voltage is given by −V_n,outR_S/R₁ and the gate voltage by (−V_n,outR_S/R₁)(−A) + V_n1. Multiplying the gate-source voltage by g_m and equating the result to −V_n,out/R₁, we have

(5.121)

and hence

(5.122)

This expression reduces to −g_mR₁V_n1/2 if the input is matched, indicating that half of the noise current of M₁ flows through R₁.¹⁵ With input matching, the voltage gain from the left terminal of R_S in Fig. 5.45(b) to the output is equal to (1 + A)g_mR₁/2. We therefore sum the output noise contribution of M₁ and R₁, divide the result by the square of this gain and the noise of R_S, and add unity:

(5.123)

This equation reveals that the NF can be lowered by raising A with the constraint (for input matching).

The above analysis has neglected the noise of the gain stage A in Fig. 5.45(a). We show in Problem 5.17 that the input-referred noise of this stage, , is multiplied by A and added to V_n1 in Eq. (5.122), leading to an overall noise figure equal to

(5.124)

In other words, is referred to the input by a factor of A²/(1 + A)², which is not much less than unity. For this reason, it is difficult to realize A by an active circuit.

It is possible to obtain the voltage gain through the use of an on-chip transformer. As shown in Fig. 5.46 [4], for a coupling factor of k between the primary and the secondary and a turns ratio of , the transformer provides a voltage gain of kn. The direction of the currents is chosen so as to yield a negative sign. However, on-chip transformer geometries make it difficult to achieve a voltage gain higher than roughly 3, even with stacked spirals [5]. Also, the loss in the primary and secondary contributes noise.

Figure 5.46 CG stage with transformer feedforward.

5.3.6 Noise-Cancelling LNAs

In our previous derivations of the noise figure of LNAs, we have observed three terms: a value of unity arising from the noise of R_S itself, a term representing the contribution of the input transistor, and another related to the noise of the load resistor. “Noise-cancelling LNAs” aim to cancel the second term [6]. The underlying principle is to identify two nodes in the circuit at which the signal appears with opposite polarities but the noise of the input transistor appears with the same polarity. As shown in Fig. 5.47, if nodes X and Y satisfy this condition, then their voltages can be properly scaled and summed such that the signal components add and the noise components cancel.

Figure 5.47 Conceptual illustration of noise-cancelling LNAs.

The CS stage with resistive feedback studied in Section 5.3.2 serves as a good candidate for noise cancellation because, as shown in Fig. 5.48(a), the noise current of M₁ flows through R_F and R_S, producing voltages at the gate and drain of the transistor with the same polarity. The signal, on the other hand, experiences inversion. Thus, as conceptually shown in Fig. 5.48(b), if V_X is amplified by −A₁ and added to V_Y, the noise of M₁ can be removed [6]. Since the noise voltages at nodes Y and X bear a ratio of 1 + R_F/R_S (why?), we choose A₁ = 1+R_F/R_S. The signal experiences two additive gains: the original gain, V_Y/V_X = 1 − g_mR_F = 1 − R_F/R_S (if the input is matched), and the additional gain, −(1 + R_F/R_S). It follows that

(5.125)-(5.126)

if the input is matched. The gain V_out/V_in is half of this value.

Figure 5.48 (a) Noise of input transistor in a feedback CS stage, (b) cancellation of noise of M₁.

Let us now compute the noise figure of the circuit, assuming that the auxiliary amplifier exhibits an input-referred noise voltage V_nA1 and a high input impedance. Recall from Section 5.3.2 that the noise voltage of R_F appears directly at the output as 4kTR_F. Adding this noise to , dividing the result by (R_F/R_S)² and 4kTR_S, and adding unity, we obtain the noise figure as

(5.127)

Since A₁ = 1 + R_F/R_S,

(5.128)

The NF can therefore be minimized by maximizing R_F and minimizing . Note that R_S/R_F is the inverse of the gain and hence substantially less than unity, making the third term approximately equal to . That is, the noise of the auxiliary amplifier is directly referred to the input and must therefore be much less than that of R_S.

The input capacitance, C_in, arising from M₁ and the auxiliary amplifier degrades both S₁₁ and the noise cancellation, thereby requiring a series (or parallel) inductor at the input for operation at very high frequencies. It can be proved [6] that the frequency-dependent noise figure is expressed as

(5.129)

where NF(0) is given by (5.128) and f₀ = 1/(πR_SC_in).

Figure 5.49 depicts an implementation of the circuit [6]. Here, M₂ and M₃ serve as a CS amplifier, providing a voltage gain of g_m2/(g_m3 + g_mb3), and also as the summing circuit. Transistor M₃ operates as a source follower, sensing the signal and noise at the drain of M₁. The first stage is similar to that studied in Example 5.7.

Figure 5.49 Example of noise-cancelling LNA.

The principal advantage of the above noise cancellation technique is that it affords the broadband characteristics of feedback or CG stages but with a lower noise figure. It is therefore suited to systems operating in different frequency bands or across a wide frequency range, e.g., 900 MHz to 5 GHz.

5.3.7 Reactance-Cancelling LNAs

It is possible to devise an LNA topology that inherently cancels the effect of its own input capacitance. Illustrated in Fig. 5.51(a) [7], the idea is to exploit the inductive input impedance of a negative-feedback amplifier so as to cancel the input capacitance, C_in. If the open-loop transfer function of the core amplifier is modeled by a one-pole response, A₀/(1 + s/ω₀), then the input admittance is given by

(5.134)

Figure 5.51 (a) Reactance-cancelling LNA topology, (b) behavior of components of Y₁ with frequency.

It follows that

(5.135)

(5.136)

At frequencies well below ω₀, 1/Re{Y₁} reduces to R_F/(1 + A₀), which can be set equal to R_S, and Im{Y₁} is roughly −A₀ω/(R_Fω₀), which can be chosen to cancel C_inω. Figure 5.51(b) illustrates the behavior of 1/Re{Y₁} and −Im{Y₁}.

The input matching afforded by the above technique holds for frequencies up to about ω₀, dictating that the open-loop bandwidth of the core amplifier reach the maximum frequency of interest. The intrinsic speed of deep-submicron devices provides the gain and bandwidth required here.

The reader may wonder if our modeling of the core amplifier by a one-pole response applies to multistage implementations as well. We return to this point below.

Figure 5.52 shows a circuit realization of the amplifier concept for the frequency range of 50 MHz to 10 GHz [7]. Three common-source stages provide gain and allow negative feedback. Cascodes and source followers are avoided to save voltage headroom. The input transistor, M₁, has a large width commensurate with flicker noise requirements at 50 MHz, thus operating with a V_GS of about 200 mV. If this voltage also appears at node Y, it leaves no headroom for output swings, limiting the linearity of the circuit. To resolve this issue, current I₁ is drawn from R_F so as to shift up the quiescent voltage at Y by approximately 250 mV. Since R_F = 1 kΩ, I₁ need be only 200 μA, contributing negligible noise at the LNA input.¹⁶

Figure 5.52 Implementation of reactance-cancelling LNA.

With three gain stages, the LNA can potentially suffer from a small phase margin and exhibit substantial peaking in its frequency response. In this design, the open-loop poles at nodes A, B, X, and Y lie at 10 GHz, 24.5 GHz, 22 GHz, and 75 GHz, respectively, creating a great deal of phase shift. Nonetheless, due to the small feedback factor, R_S/(R_S + R_F) = 0.048, simulations indicate that the circuit provides a phase margin of about 50° and a peaking of 1 dB in its closed-loop frequency response.

The multi-pole LNA of Fig. 5.52 contains an inductive component in its input impedance but with a behavior more complex than the above analysis suggests. Fortunately, behavioral simulations confirm that, if the poles at B, X, and Y are “lumped” (i.e., their time constants are added), then the one-pole approximation still predicts the input admittance accurately. The pole frequencies mentioned above collapse to an equivalent value of ω₀ = 2π (9.9 GHz), suggesting that the real and imaginary parts of Y₁ retain the desired behavior up to the edge of the cognitive radio band.

The LNA output is sensed between nodes X and Y. Even though these nodes provide somewhat unequal swings and a phase difference slightly greater than 180°, the pseudo-differential sensing still raises both the gain and the IP₂, the latter because second-order distortion at X also appears at Y and is thus partially cancelled in V_Y − V_X.¹⁷

5.4 Gain Switching

The dynamic range of the signal sensed by a receiver may approach 100 dB. For example, a cell phone may receive a signal level as high as −10 dBm if it is close to a base station or as low as −110 dBm if it is in an underground garage. While designed for the highest sensitivity, the receiver chain must still detect the signal correctly as the input level continues to increase. This requires that the gain of each stage be reduced so that the subsequent stages remain sufficiently linear with the large input signal. Of course, as the gain of the receiver is reduced, its noise figure rises. The gain must therefore be lowered such that the degradation in the sensitivity is less than the increase in the received signal level, i.e., the SNR does not fall. Figure 5.53 shows a typical scenario.

Figure 5.53 Effect of gain switching on NF and P_1dB.

Gain switching in an LNA must deal with several issues: (1) it must negligibly affect the input matching; (2) it must provide sufficiently small “gain steps”; (3) the additional devices performing the gain switching must not degrade the speed of the original LNA; (4) for high input signal levels, gain switching must also make the LNA more linear so that this stage does not limit the receiver linearity. As seen below, some LNA topologies lend themselves more easily to gain switching than others do.

Let us first consider a common-gate stage. Can we reduce the transconductance of the input transistor to reduce the gain? To switch the gain while maintaining input matching, we can insert a physical resistance in parallel with the input as g_m is lowered. Figure 5.54 shows an example [8], where the input transistor is decomposed into two, M_1x and M_1y, and transistor M₂ introduces a parallel resistance if it is on. In the “high-gain mode,” the gain select line, GS, is high, placing M_1x and M_1y in parallel, and M₂ is off. In the “low-gain mode,” M_1y turns off, reducing the gain, and M₂ turns on, ensuring that R_on2||(g_m1x + g_mb1x)⁻¹ = R_S. For example, to reduce the gain by 6 dB, we choose equal dimensions for M_1x and M_1y and R_on2 = (g_m1x + g_mb1x)⁻¹ = 2R_S (why?). Also, the gate of M_1y is secured to ground by a capacitor to avoid the on-resistance of the switch at high frequencies.

Figure 5.54 Example of gain switching in CG stage.

In the above calculation, we have neglected the effect of channel-length modulation. If the upper bound expressed by Eq. (5.67) restricts the design, then the cascode CG stage of Fig. 5.24 can be used.

Another approach to switching the gain of a CG stage is illustrated in Fig. 5.55, where the on-resistance of M₂ appears in parallel with R₁. With input matching and in the absence of channel-length modulation, the gain is given by

(5.139)

Figure 5.55 Effect of load switching on input impedance.

For multiple gain steps, a number of PMOS switches can be placed in parallel with R₁. The following example elaborates on this point.

The principal difficulty with switching the load resistance in a CG stage is that it alters the input resistance, as expressed by R_in = (R₁ + r_O)/(1 + g_mr_O). This effect can be minimized by adding a cascode transistor as in Fig. 5.24. The use of a cascode transistor also permits a third method of gain switching. Illustrated in Fig. 5.57, the idea is to route part of the drain current of the input device to V_DD—rather than to the load—by means of another cascode transistor, M₃. For example, if M₂ and M₃ are identical, then turning M₃ on yields α = 0.5, dropping the voltage gain by 6 dB.

Figure 5.57 Gain switching by cascode device.

The advantage of the above technique over the previous two is that the gain step depends only on W₃/W₂ (if M₂ and M₃ have equal lengths) and not the absolute value of the on-resistance of a MOS switch. The bias and signal currents produced by M₁ split between M₃ and M₂ in proportion to W₃/W₂, yielding a gain change by a factor of 1 + W₃/W₂. As a result, gain steps in the circuit of Fig. 5.57 are more accurate than those in Figs. 5.54 and 5.55. However, the capacitance introduced by M₃ at node Y degrades the performance at high frequencies. For a single gain step of 6 dB, we have W₃ = W₂, nearly doubling the capacitance at this node. For a gain reduction by a factor of N, W₃ = (N − 1)W₂, possibly degrading the performance considerably.

In order to reduce the capacitance contributed by the gain switching transistor, we can turn off part of the main cascode transistor so as to create a greater imbalance between the two. Shown in Fig. 5.58 (on page 310) is an example where M₂ is decomposed into two devices so that, when M₃ is turned on, M_2a is turned off. Consequently, the gain drops by a factor of 1 + W₃/W_2b rather than 1 + W₃/(W_2b + W_2a).

Figure 5.58 Gain switching by programmable cascode devices.

We now turn our attention to gain switching in an inductively-degenerated cascode LNA. Can we switch part of the input transistor to switch the gain (Fig. 5.59)? Turning M_1b off does not alter ω_T because the current density remains constant. Thus, Re{Z_in} = L₁ω_T is relatively constant, but Im{Z_in} changes, degrading the input match. If the input match is somehow restored, then the voltage gain, R₁/(2L₁ω), does not change! Furthermore, the thermal noise of S₁ degrades the noise figure in the high gain mode. For these reasons, gain switching must be realized in other parts of the circuit.

Figure 5.59 Gain switching in CS stage.

As with the CG LNA of Fig. 5.55, the gain can be reduced by placing one or more PMOS switches in parallel with the load [Fig. 5.60(a)]. Alternatively, the cascode switching scheme of Fig. 5.57 can be applied here as well [Fig. 5.60(b)]. The latter follows the calculations outlined in Example 5.24, providing well-defined gain steps with a moderate additional capacitance at node Y. It is important to bear in mind that cascode switching is attractive because it reduces the current flowing through the load by a well-defined ratio and it negligibly alters the input impedance of the LNA.

Figure 5.60 Gain switching in cascode CS stage by (a) load switching, (b) additional cascode device.

For the two variants of the CG stage studied in Section 5.3.3, gain switching can be realized by cascode devices as illustrated in Fig. 5.57. The use of feedback or feedforward in these topologies makes it difficult to change the gain through the input transistor without affecting the input match.

Lastly, let us consider gain switching in the noise-cancelling LNA of Fig. 5.48(b). Since V_Y/V_X = 1 − R_F/R_S and R_in is approximately equal to 1/g_m1 and independent of R_F, the gain can be reduced simply by lowering the value of R_F. Though not essential in the low-gain mode, noise cancellation can be preserved by adjusting A₁ so that it remains equal to 1 + R_F/R_S.

Which one of the foregoing gain reduction techniques also makes the LNA more linear? None, except for the last one! Since the CG and CS stages retain the gate-source voltage swing (equal to half of the input voltage swing), their linearity improves negligibly. In the feedback LNA of Fig. 5.48(b), on the other hand, a lower R_F strengthens the negative feedback, raising the linearity to some extent.

Receiver designs in which the LNA nonlinearity becomes problematic at high input levels can “bypass” the LNA in very-low-gain modes. Illustrated conceptually in Fig. 5.61, the idea is to omit the LNA from the signal path so that the mixer (presumably more linear) directly senses the received signal. The implementation is not straightforward if input matching must be maintained. Figure 5.62 depicts a common-gate example, where M₁ is turned off, M₂ is turned on to produce a 50-Ω resistance, and M₃ is turned on to route the signal to the mixer.

Figure 5.61 LNA bypass.

Figure 5.62 Realization of LNA bypass.

5.5 Band Switching

As mentioned in Section 5.1, LNAs that must operate across a wide bandwidth or in different bands can incorporate band switching. Figure 5.63(a) repeats the structure of Fig. 5.7(a), with the switch realized by a MOS transistor. Since the bias voltage at the output node is near V_DD, the switch must be a PMOS device, thus contributing a larger capacitance for a given on-resistance than an NMOS transistor. This capacitance lowers the tank resonance frequency when S₁ is off, reducing the maximum tolerable value of C₁ and hence limiting the size of the input transistor of the following stage. (If L₁ is reduced to compensate for the higher capacitance, then so are R₁ and the gain.) For this reason, we prefer the implementation in Fig. 5.63(b), where S₁ is formed as an NMOS device tied to ground.

Figure 5.63 (a) Band switching, (b) effect of switch parasitics.

The choice of the width of S₁ in Fig. 5.63(b) proves critical. For a very narrow transistor, the on-resistance, R_on1, remains so high that the tank does not “feel” the presence of C₂ when S₁ is on. For a moderate device width, R_on1 limits the Q of C₂, thereby lowering the Q of the overall tank and hence the voltage gain of the LNA. This can be readily seen by transforming the series combination of C₂ and R_on1 to a parallel network consisting of C₂ and R_P1 ≈ Q²R_on1, where Q = (C₂ωR_on1)⁻¹. That is, R₁ is now shunted by a resistance .

The foregoing observation implies that R_on1 must be minimized such that R_P1 R₁. However, as the width of S₁ in Fig. 5.63(b) increases, so does the capacitance that it introduces in the off state. The equivalent capacitance seen by the tank when S₁ is off is equal to the series combination of C₂ and C_GD1 + C_DB1, which means C₁ must be less than its original value by this amount. We therefore conclude that the width of S₁ poses a trade-off between the tolerable value of C₁ when S₁ is off and the reduction of the gain when S₁ is on. (Recall that C₁ arises from M_a, the input capacitance of the next stage, and the parasitic capacitance of L₁.)

An alternative method of band switching incorporates two or more tanks as shown in Fig. 5.64 [8]. To select one band, the corresponding cascode transistor is turned on while the other remains off. This scheme requires that each tank drive a copy of the following stage, e.g., a mixer. Thus, when M₁ and band 1 are activated, so is mixer MX₁. The principal drawback of this approach is the capacitance contributed by the additional cascode device(s) to node Y. Also, the spiral inductors have large footprints, making the layout and routing more difficult.

Figure 5.64 Band switching by programmable cascode branches.

5.6 High-IP₂ LNAs

As explained in Chapter 4, even-order distortion can significantly degrade the performance of direct-conversion receivers. Since the circuits following the downconversion mixers are typically realized in differential form,¹⁸ they exhibit a high IP₂, leaving the LNA and the mixers as the IP₂ bottleneck of the receivers. In this section, we study techniques of raising the IP₂ of LNAs, and in Chapter 6, we do the same for mixers.

5.6.1 Differential LNAs

Differential LNAs can achieve high IP₂’s because, as explained in Chapter 2, symmetric circuits produce no even-order distortion. Of course, some (random) asymmetry plagues actual circuits, resulting in a finite, but still high, IP₂.

In principle, any of the single-ended LNAs studied thus far can be converted to differential form. Figure 5.65 depicts two examples. Not shown here, the bias network for the input transistors is similar to those described in Sections 5.3.3 and 5.3.4.

Figure 5.65 Differential (a) CG and (b) CS stages.

But what happens to the noise figure of the circuit if it is converted to differential form? Before answering this question, we must determine the source impedance driving the LNA. Since the antenna and the preselect filter are typically single-ended, a transformer must precede the LNA to perform single-ended to differential conversion. Illustrated in Fig. 5.66(a), such a cascade processes the signal differentially from the input port of the LNA to the end of the baseband section. The transformer is called a “balun,” an acronym for “balanced-to-unbalanced” conversion because it can also perform differential to single-ended conversion if its two ports are swapped.

Figure 5.66 (a) Use of balun at RX input, (b) simplified circuit.

If the source impedance provided by the antenna and the band-pass filter in Fig. 5.66(a) is R_S1 (e.g., 50Ω), what is the differential source impedance seen by the LNA, R_S2? For a lossless 1-to-1 balun, i.e., for a lossless transformer with an equal number of turns in its primary and secondary, we have R_S2 = R_S1. We must thus obtain the noise figure of the differential LNA with respect to a differential source impedance of R_S1. Figure 5.66(b) shows the setup for output noise calculation.

Note that the differential input impedance of the LNA, R_in, must be equal to R_S1 for proper input matching. Thus, in the LNAs of Figs. 5.66(a) and (b), the single-ended input impedance of each half circuit must be equal to R_S1/2, e.g., 25Ω.

Differential CG LNA

We now calculate the noise figure of the differential CG LNA of Fig. 5.65(a), assuming it is designed such that the impedance seen between each input node and ground is equal to R_S1/2. In other words, each CG transistor must provide an input resistance of 25Ω. Figure 5.67(a) shows the simplified environment, emphasizing that the noise figure is calculated with respect to a source impedance of R_S1. Redrawing Fig. 5.67(a) as shown in Fig. 5.67(b), we recognize from the symmetry of the circuit that we can compute the output noise of each half circuit as in Fig. 5.67(c) and add the output powers:

(5.148)

Figure 5.67 (a) Cascade of balun and LNA, (b) simplified circuit of (a), and (c) simplified circuit of (b).

Since each half circuit provides matching at the input, the CG results of Section 5.3.3 apply here as well with the substitution R_S = R_S1/2. Specifically, the voltage gain from X to Y is equal to R₁/(2R_S1/2), where R₁ denotes the load resistance of the CG half circuit. The output noise consists of (1) the input transistor contribution, given by Eq. (5.56), (2) the load resistor contribution, 4kTR₁, and (3) the source impedance contribution, (4kTR_S1/2)[R₁/(2R₁/2)]:

(5.149)

From Eq. (5.148), the total output noise power is twice this amount. Noting that the total voltage gain A_v = (V_Y − V_W)/(V_X − V_Z) is equal to that of half of the circuit, V_Y/V_X( = R₁/R_S1), we compute the noise figure with respect to a source impedance of R_S1 as

(5.150)-(5.151)

Interestingly, this value is lower than that of the single-ended counterpart [Eq. (5.58)]. But why? Since in Fig. 5.67(c), V_Y/V_X = R₁/(2R_S1/2) = R₁/R_S1, we observe that the voltage gain is twice that of the single-ended CG LNA. (After all, the transconductance of the input transistor is doubled to lower the input impedance to R_S1/2.) On the other hand, the overall differential circuit contains two R₁’s at its output, each contributing a noise power of 4kTR₁. The total, 8kTR₁, divided by (R₁/R_S1)² and 4kTR_S1 yields 2R_S1/R₁. Of course, the value stipulated by Eq. (5.151) can be readily obtained in a single-ended CG LNA by simply doubling the load resistance. Figure 5.68 summarizes the behavior of the two circuits, highlighting the greater voltage gain in the differential topology. If identical gains are desired, the value of the load resistors in the differential circuit must be halved, thereby yielding identical noise figures.

Figure 5.68 Comparison of (a) single-ended and (b) differential CG LNAs.

In summary, a single-ended CG LNA can be converted to differential form according to one of three scenarios: (1) simply copy the circuit, in which case the differential input resistance reaches 100Ω, failing to provide matching with a 1-to-1 balun; (2) copy the circuit but double the transconductance of the input transistors, in which case the input is matched but the overall voltage gain is doubled; (3) follow the second scenario but halve the load resistance to retain the same voltage gain. The second choice is generally preferable. Note that, for a given noise figure, a differential CG LNA consumes four times the power of a single-ended stage.¹⁹

Our NF calculations have assumed an ideal balun. In reality, even external baluns have a loss as high as 0.5 dB, raising the NF by the same amount.

Differential CS LNA

The differential CS LNA of Fig. 5.65(b) behaves differently from its CG counterpart. From Section 5.3.4, we recall that the input resistance of each half circuit is equal to L₁ω_T and must now be halved. This is accomplished by halving L₁. With input matching and a degeneration inductance of L₁, the voltage gain was found in Section 5.3.4 to be R₁/(2L₁ω₀), which is now doubled. Figure 5.70(a) illustrates the overall cascade of the balun and the differential LNA. We assume that the width and bias current of each input transistor are the same as those of the single-ended LNA.

Figure 5.70 (a) Differential CS LNA and (b) its half circuit.

To compute the noise figure, let us first determine the output noise of the half circuit depicted in Fig. 5.70(b). Neglecting the contribution of the cascode device, we note from Section 5.3.4 that, if the input is matched, half of the noise current of the input transistor flows from the output node. Thus,

(5.156)

Multiplying this power by two, dividing it by and 4kTR_S1, and noting that L₁ω_T/2 = R_S1/2, we have

(5.157)

How does this compare with the noise figure of the original single-ended LNA [Eq. (5.101)]? We observe that both the transistor contribution and the load contribution are halved. The transistor contribution is halved because g_m1 and hence the transistor noise current remain unchanged while the overall transconductance of the circuit is doubled. To understand this point, recall from Section 5.3.4 that G_m = ω_T/(2ω₀R_S) for the original single-ended circuit. Now consider the equivalent circuit shown in Fig. 5.71, where the differential transconductance, (I₁ − I₂)/V_in, is equal to ω_T/(ω₀R_S1) (why?). The differential output current contains the noise currents of both M₁ and M₂ and is equal to 2(kT_γgm1). If this power is divided by the square of the transconductance and 4kTR_S1, the first term in Eq. (5.157) is obtained.

Figure 5.71 Differential CS stage viewed as a transconductor.

The reduction of the input transistor noise contribution in Eq. (5.157) is a remarkable property of differential operation, reinforcing the NF advantage of the degenerated CS stage over the CG LNA. However, this result holds only if the design can employ two degeneration inductors, each having half the value of that in the single-ended counterpart. This is difficult with bond wires as their physical length cannot be shortened arbitrarily. Alternatively, the design can incorporate on-chip degeneration inductors while converting the effect of the (inevitable) bond wire to a common-mode inductance. Figure 5.72 shows such a topology. With perfect symmetry, the bond wire inductance has no effect on the differential impedance seen between the gates. Nonetheless, as explained in Chapter 7, on-chip inductors suffer from a low quality factor (e.g., a high series resistance), possibly degrading the noise figure. We compare the power consumptions of the single-ended and differential implementations in Problem 5.22.

Figure 5.72 Differential CS stage with on-chip degeneration inductors.

The NF advantage implied by Eq. (5.157) may not materialize in reality because the loss of the balun is not negligible.

Is it possible to use a differential pair to convert the single-ended antenna signal to differential form? As shown in Fig. 5.73(a), the signal is applied to one input while the other is tied to a bias voltage. At low to moderate frequencies, V_X and V_Y are differential and the voltage gain is equal to g_m1,2R_D. At high frequencies, however, two effects degrade the balance of the phases: the parasitic capacitance at node P attenuates and delays the signal propagating from M₁ to M₂, and the gate-drain capacitance of M₁ provides a non-inverting feedforward path around M₁ (whereas M₂ does not contain such a path).

Figure 5.73 Single-ended to differential conversion by (a) a simple differential pair, (b) a differential pair including tail resonance.

The capacitance at P can be nulled through the use of a parallel inductor [Fig. 5.73(b)] [9], but the C_GD1 feedforward persists. The tail inductor can be realized on-chip because its parallel equivalent resistance at resonance (R_P = QL_Pω₀) is typically much greater than 1/g_m1,2.

The topology of Fig. 5.73(b) still does not provide input matching. We must therefore insert (on-chip) inductances in series with the sources of M₁ and M₂ (Fig. 5.75). Here, L_P1 and L_P2 resonate with C_P1 and C_P2, respectively, and L_S1 + L_S2 provides the necessary input resistance. Of course, L_S1 + L_S2 is realized as one inductor. However, as explained in Section 5.7, this topology exhibits a lower IP₃ than that of Fig. 5.65(b).

Figure 5.75 Use of on-chip inductors for resonance and degeneration.

Balun Issues

The foregoing development of differential LNAs has assumed ideal 1-to-1 baluns. Indeed, external baluns with a low loss (e.g., 0.5 dB) in the gigahertz range are available from manufacturers, but they consume board space and raise the cost. Integrated baluns, on the other hand, suffer from a relatively high loss and large capacitances. Shown in Fig. 5.76 is an example, where two spiral inductors L_AC and L_CB are intertwined to create a high mutual coupling. As explained in Chapter 7, the resistance and capacitance associated with the spirals and the sub-unity coupling factor make such baluns less attractive.

Figure 5.76 Simple planar 1-to-1 balun.

The reader may wonder if an N-to-1 (rather than 1-to-N) balun proves beneficial in the above example as it would multiply the first two terms of Eq. (5.160) by 1/N² rather than N². Indeed, off-chip baluns may provide a lower noise figure if L₁ (a bond wire) can be reduced by a factor of N². On the other hand, on-chip baluns with a non-unity turns ratio are difficult to design and suffer from a higher loss and a lower coupling factor. Figure 5.78(a) shows an example [5], where one spiral forms the primary (secondary) of the balun and the series combination of two spirals constitutes the secondary (primary). Alternatively, as shown in Fig. 5.78(b), spirals having different numbers of turns can be embedded [10].

Figure 5.78 Realization of 1-to-2 balun as (a) stacked spirals, (b) embedded spirals.

5.6.2 Other Methods of IP₂ Improvement

The difficulty with the use of off-chip or on-chip baluns at the input of differential LNAs makes single-ended topologies still an attractive choice. A possible approach to raising the IP₂ entails simply filtering the low-frequency second-order intermodulation product, called the beat component in Chapter 4. Illustrated in Fig. 5.79, the idea is to remove the beat by a simple high-pass filter (HPF) following the LNA. For example, suppose two interferers are located at the edges of the 2.4-GHz band, f₁ = 2.4 GHz and f₂ = 2.480 GHz. The beat therefore lies at 80 MHz and is attenuated by approximately a factor of 2400/80 = 30 for a first-order HPF. With this substantial suppression, the IP₂ of the LNA is unlikely to limit the RX performance, calling for techniques that improve the IP₂ of mixers (Chapter 6).

Figure 5.79 Removal of low-frequency beat by first-order high-pass filter.

The filtration of the IM₂ product becomes less effective for wider communication bands. For example, if a receiver must accommodate frequencies from 1 GHz to 10 GHz, then two interferers can produce a beat within the band, prohibiting the use of filters to remove the beat. In this case, the LNA may become the receiver’s IP₂ bottleneck.

5.7 Nonlinearity Calculations

The general behavior of nonlinear systems was formulated in Chapter 2. In this section, we develop a methodology for computing the nonlinear characteristics of some circuits.

Recall from Chapter 2 that systems with weak static nonlinearity can be approximated by a polynomial such as y = α₁x + α₂x² + α₃x³. Let us devise a method for computing α₁-α₃ for a given circuit. In many circuits, it is difficult to derive y as an explicit function of x. However, we recognize that

(5.161)

(5.162)

(5.163)

These expressions prove useful because we can obtain the derivatives by implicit differentiation. It is important to note that in most cases, x = 0 in fact corresponds to the bias point of the circuit with no input perturbation. In other words, the total y may not be zero for x = 0. For example, in the common-source stage of Fig. 5.80, M₁ is biased at a gate-source voltage of V_GS0 = V_b and V_in is superimposed on this voltage.

Figure 5.80 CS stage with gate bias.

5.7.1 Degenerated CS Stage

As an example, let us study the resistively-degenerated common-source stage shown in Fig. 5.81, assuming the drain current is the output of interest. We wish to compute the IP₃ of the circuit. For a simple square-law device

(5.164)

where K = (1/2)μ_nC_ox(W/L) and channel-length modulation and body effect are neglected. Since V_GS = V_in − R_SI_D,

(5.165)

and hence

(5.166)

Figure 5.81 CS stage for nonlinearity calculations.

We also note that

(5.167)-(5.168)

where V_in0 ( = V_b) and I_D0 denote the bias values. Thus, in the absence of signals,

(5.169)

an expected result.

We now compute the second derivative from Eq. (5.166):

(5.170)

With no signals, (5.168) and (5.169) can be substituted in (5.170) to produce

(5.171)

Lastly, we determine the third derivative from (5.170):

(5.172)

which, from (5.169) and (5.171) reduces to

(5.173)

While lengthy, the foregoing calculations lead to interesting results. Equation (5.173) reveals that α₃ = 0 if R_S = 0, an expected outcome owing to the square-law behavior assumed for the transistor. Additionally, α₁ and α₃ have opposite signs, implying a compressive characteristic—whereas the undegenerated transistor would exhibit an expansive behavior. In other words, resistive degeneration of a square-law device creates third-order distortion.

To compute the IP₃ of the stage, we write from Chapter 2,

(5.174)-(5.175)

The 1-dB compression point follows the same expression but lowered by a factor of 3.03 (9.6 dB).

The reader may wonder if the above analysis of nonlinearity confuses large-signal and small-signal operations by expression α₁-α₃ in terms of the device transconductance. It is helpful to bear in mind that g_m in the above expressions is merely a short-hand notation for a constant value, 2K(V_in0 − R_SI_D0 − V_TH), and independent of the input. It is, of course, plausible that α₁-α₃ must be independent of the input; otherwise, the polynomial’s order exceeds 3.

5.7.2 Undegenerated CS Stage

Consider the CS stage shown in Fig. 5.80. Submicron transistors substantially depart from square-law characteristics. The effect of mobility degradation due to both vertical and lateral fields in the channel can be approximated as

(5.183)

where μ₀ denotes the zero-field mobility, v_sat the saturation velocity of the carriers, and θ the effect of the vertical field [11]. If the second term in the denominator remains much less than unity, we can write (1 + ε)⁻¹ ≈ 1 − ε and hence

(5.184)

The input signal, V_in, is superimposed on a bias voltage, V_GS0 = V_b. We therefore replace V_GS with V_in + V_GS0, obtaining

(5.185)

where K = (1/2)μ₀C_ox(W/L) and a = μ₀/(2v_satL)+θ. We recognize the coefficient of V_in as the transconductance (∂I_D/∂V_in) and the last two terms as the bias current. It follows that

(5.186)

(5.187)

The IP₃ is given by

(5.188)-(5.189)

We note that the IP₃ rises with the bias overdrive voltage, reaching a maximum of

(5.190)

at V_GS0 − V_TH = (3a)⁻¹ (Fig. 5.84).

Figure 5.84 Behavior of IP₃ as a function of overdrive.

5.7.3 Differential and Quasi-Differential Pairs

In RF systems, differential signals can be processed using the differential pair shown in Fig. 5.85(a) or the “quasi-differential” pair depicted in Fig. 5.85(b). The two topologies exhibit distinctly different nonlinear characteristics. We know from our above analysis that the dependence of the mobility upon vertical and lateral fields in the channel results in third-order nonlinearity in the quasi-differential pair and an IP₃ given by Eq. (5.189). To study the nonlinearity of the standard differential pair, we recall from basic analog circuits that

(5.193)

Figure 5.85 (a) Differential and (b) quasi-differential pairs.

where V_in denotes the input differential voltage. If |V_in| I_SS/(μ_nC_oxW/L), then

(5.194)

That is,

(5.195)

(5.196)

and hence

(5.197)-(5.198)

where (V_GS0 − V_TH) is the overdrive voltage of each transistor in equilibrium (V_in = 0).²³

Interestingly, the standard differential pair suffers from third-order nonlinearity even in the absence of field-dependent mobility (i.e., with square-law devices). For this reason, the quasi-differential pair of Fig. 5.85(b) is preferred in cases where linearity is important. In fact, it is for this reason that the differential CS LNA of Fig. 5.65(b) does not employ a tail current source. The quasi-differential pair also saves the voltage headroom associated with the tail current source, proving more attractive as the supply voltage is scaled down.

5.7.4 Degenerated Differential Pair

Consider the degenerated pair shown in Fig. 5.86, where I_D1 − I_D2 is the output of interest. Since I_D1 + I_D2 = 2I₀, we have ∂(I_D1 − I_D2)/∂V_in = 2∂I_D1/∂V_in. Also, V_in1 − V_GS1 − I_SR_S = V_in2 − V_GS2 and I_S = I_D1 − I₀. It follows that

(5.199)

Figure 5.86 Degenerated differential pair.

where V_in = V_in1 − V_in2 and K = (1/2)μ_nC_ox(W/L). Differentiating both sides with respect to V_in yields

(5.200)

At V_in = 0, I_D1 = I_D2 and

(5.201)

where g_m = 2I₀/(V_GS0 − V_TH). Differentiating both sides of (5.200) with respect to V_in gives

(5.202)

Note that for V_in = 0, we have because ∂I_D1/∂V_in = −∂I_D2/∂V_in and the term in the second set of square brackets vanishes. Differentiating once more and exploiting this fact, we have

(5.203)

It follows that . We now have that

(5.204)

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[8] B. Razavi et al., “A UWB CMOS Transceiver,” IEEE Journal of Solid-State Circuits, vol. 40, pp. 2555–2562, Dec. 2005.

[9] M. Zargari et al., “A Single-Chip Dual-Band Tri-Mode CMOS Transceiver for IEEE 802.11a/b/g Wireless LAN,” IEEE Journal of Solid-State Circuits, vol. 39, pp. 2239–2249, Dec. 2004.

[10] J. R. Long and M. A. Copeland, “The Modeling, Characterization, and Design of Monolithic Inductors for Silicon RF ICs,” IEEE J. Solid-State Circuits, vol. 32, pp. 357–369, March 1997.

[11] B. Razavi, Design of Analog CMOS Integrated Circuits, Boston: McGraw-Hill, 2001.

Problems

5.1. Assuming Z_in = x + jy, derive an equation for constant-τ contours in Fig. 5.4.

5.2. If R_p = R_S and g_mR_S ≈ 1, determine the NF in Eq. (5.18) by considering the first three terms. What value of g_m is necessary to achieve a noise figure of 3.5 dB?

5.3. Repeat Example 5.5 by solving the specific network shown in Fig. 5.10(a).

5.4. Determine the noise figure of the stages shown in Fig. 5.87 with respect to a source impedance of R_S. Neglect channel-length modulation and body effect.

Figure 5.87 Stages for NF calculation.

5.5. For the inductively-loaded CS stage of Fig. 5.11(b), determine V_out/V_in and find the voltage gain at the resonance frequency, , if |jC₁ω₀| g_m.

5.6. For the CS stage of Fig. 5.13(a), determine the closed-loop gain and noise figure if channel-length modulation is not neglected. Assume matching at the input.

5.7. For the complementary stage shown in Fig. 5.15, determine the closed-loop gain and noise figure if channel-length modulation is not neglected. Assume matching at the input.

5.8. For the CG stage of Fig. 5.16(a), compute the noise figure at the output resonance frequency if g_m ≠ 1/R_S. How can g_m be chosen to yield a noise figure lower than 1 + γ + 4R_S/R_a?

5.9. A circuit exhibits a noise figure of 3 dB. What percentage of the output noise power is due to the source resistance, R_S? Repeat the problem for NF = 1 dB.

5.10. Determine the noise figure of the CG circuits shown in Fig. 5.17.

5.11. In Example 5.10, we concluded that the noise of M₂ reaches the output unattenuated if ω is greater than (R₁C_X)⁻¹ but much less than g_m2/(C_GS2 + C_X). Does such a frequency range exist? In other words, under what conditions do we have (R₁C_X)⁻¹ < ω g_m2/(C_GS2 + C_X) >? Assume g_m2 ≈ g_m1 and recall that g_m1R₁ is the gain of the LNA and C_X is on the order of C_SG2.

5.12. If L_G in Fig. 5.34 suffers from a series resistance of R_t, determine the noise figure of the circuit.

5.13. The LNA shown in Fig. 5.88 is designed to operate with low supply voltages. Each inductor is chosen to resonate with the total capacitance at its corresponding node at the frequency of interest. Neglect channel-length modulation and body effect and the noise due to the loss in L₂. Determine the noise figure of the LNA with respect to a source resistance R_S assuming that L₁ can be viewed as a resistance equal to R_p at the resonance frequency. Make sure the result reduces to a familiar form if R_p → ∞. (Hint: the equivalent transconductance of a degenerated common-source stage is given by g_m/(1 + g_mR₁), where R₁ denotes the degeneration resistance.)

Figure 5.88 Folded-cascode LNA.

5.14. Determine S₁₁ for both topologies in Fig. 5.40 and compute the maximum deviation of the center frequency for which S₁₁ remains lower than −10 dB.

5.15. Repeat the analysis of the CG stage in Fig. 5.43 while including channel-length modulation.

5.16. Repeat the NF analysis of the CG stage in Fig. 5.43 while including the noise of the feedback network as a voltage, , in series with its input.

5.17. Prove that the input-referred noise of the feedforward amplifier in Fig. 5.45(a) manifests itself as the fourth term in Eq. (5.124).

5.18. Repeat the analysis of the CG stage of Fig. 5.45(a) while including channel-length modulation.

5.19. Is the noise of R_F in Fig. 5.48(b) cancelled? Explain.

5.20. For the circuit shown in Fig. 5.89, we express the input-output characteristic as

(5.205)

where I₀ and V₀ denote the bias values, i.e., the values in the absence of signals. We note that ∂I_out/∂V_in = α₁ at V_in = V₀ (or I_out = I₀). Similarly, at V_in = V₀ (or I_out = I₀).

Figure 5.89 Stage for IP₂ calculation.

(a) Write a KVL around the input network in terms of V_in and I_out (with no V_GS). Differentiate both sides implicitly with respect to V_in. You will need this equation in part (b). Noting that , where K = μ_nC_oxW/L, find ∂I_out/∂V_in and hence α₁.

(b) Differentiate the equation obtained in part (a) with respect to V_in once more and compute α₂ in terms of I₀ and g_m.

(c) Determine the IP₂ of the circuit.

5.21. Determine the noise figure in Example 5.21 if the gain is reduced by 3 dB.

5.22. Compare the power consumptions of the single-ended and differential CS stages discussed in Section 5.6.1. Consider two cases: (a) the differential stage is derived by only halving L₁ (and hence has a lower noise figure), or (b) the differential stage is designed for the same NF as the single-ended circuit.

5.23. Repeat the analysis of the differential CG stage NF if a 1-to-2 balun is used. Such a balun provides a voltage gain of 2.

5.24. Consider a MOS transistor configured as a CS stage and operating in saturation. Determine the IP₃ and P_1dB if the device (a) follows the square-law behavior, I_D ∝ (V_GS − V_TH)², or (b) exhibits field-dependent mobility [Eq. (5.183)]. (Hint: IP₃ and P_1dB may not be related by a 9.6-dB difference in this case.)