IN THIS CHAPTER

Understanding latches and gated latches

Looking at flip-flops

Building some basic latch and flip-flop circuits

This chapter is about flip-flops, but not the kind you wear on your feet. I wish it were about the kind you wear on your feet, especially if I happened to be wearing a pair while I wrote this because that might mean I’d be writing this at the beach, parked in a beach chair watching children play with the waves.

Don’t you love watching children play with waves? They laugh uncontrollably as they chase after a retreating wave. But when the next wave comes in, the children turn and run, screaming with delight for fear that the wave might catch them, and they might — of all things — get wet.

Alas, this chapter isn’t about the kind of flip-flops you wear to the beach. Instead, it’s about the electronic kind of flip-flop. A flip-flop is a circuit that stores data. As such, flip-flops are the basis of modern computers.

Don’t you think it’s odd that one of the fundamental building blocks of modern thinking machines has a name that suggests it can’t make up its mind?

In this chapter, you learn how to work with simple flip-flop circuits. Before I tell you about flip-flops, however, I first show you a simpler type of circuit called a latch.

Looking at Latches

A latch is a logic circuit that has two inputs and one output. One of the inputs is called the SET input; the other is called the RESET input.

Latch circuits can be either active-high or active-low. The difference is determined by whether the operation of the latch circuit is triggered by HIGH or LOW signals on the inputs. (Refer to Chapter 2 of this minibook for an explanation of concepts such as HIGH and LOW.)

• Active-high circuit: Both inputs are normally tied to ground (LOW), and the latch is triggered by a momentary HIGH signal on either of the inputs.
• Active-low circuit: Both inputs are normally HIGH, and the latch is triggered by a momentary LOW signal on either input.

In an active-high latch, both the SET and RESET inputs are connected to ground. When the SET input goes HIGH, the output also goes HIGH. When the SET input returns to LOW, however, the output remains HIGH. The output of the active-high latch stays HIGH until the RESET input goes HIGH. Then, the output returns to LOW and will go HIGH again only when the SET input is triggered once more.

In other words, the latch remembers that the SET input has been activated. If the SET input goes HIGH for even a moment, the output goes HIGH and stays HIGH, even after the SET input returns to LOW. The output returns to LOW only when the RESET input goes HIGH.

On the other hand, in an active-low latch the inputs are normally held at HIGH. When the SET input momentarily goes LOW, the output goes HIGH. The output then stays HIGH until the RESET input momentarily goes LOW.

Note that most latch circuits actually have a second output that is simply the first output inverted. In other words, whenever the first output is HIGH, the second output is LOW, and vice versa. These outputs are usually referred to as Q and .

The notation is usually pronounced either “bar Q” or “Q bar,” though some people pronounce it “not Q.” The horizontal bar symbol over a label is a common logical shorthand for inversion. That is, is the inverse of Q. If Q is HIGH, is LOW, and if Q is LOW, is HIGH.

You can easily create an active-high latch from a pair of NOR gates, as shown in Figure 4-1. (Recall from Chapter 2 in this minibook that the output of a NOR gate is HIGH if both inputs are LOW; otherwise, the output is LOW.) In this circuit, the SET input is connected to one of the inputs of the first NOR gate, and the RESET input is connected to one of the inputs of the second NOR gate. The trick of the latch circuit is that the output of the NOR gates are cross-connected to the remaining NOR gate inputs. In other words, the output from the first NOR gate is connected to one of the inputs of the second NOR gate, and the output from the second NOR gate is connected to one of the inputs of the first NOR gate.

The schematic for an active-low latch is shown in Figure 4-2. As you can see, the only difference between this schematic and the one shown in Figure 4-1 is that the active-low latch uses NAND gates instead of NOR gates. Notice also in this diagram that the inputs are referred to as and rather than SET and RESET, which indicates that the inputs are active-low.

Projects 38 and 39 show you how to build simple active-high and active-low latch circuits using a 4001 quad 2-input NOR gate IC and a 4011 quad 2-input NAND gate IC. Both the Q and outputs are used to drive LEDs so you can see the state of the latch, and both inputs are controlled by normally open push buttons so that you can trigger the latch by momentarily pressing the buttons. Figure 4-3 shows the assembled active-high latch, and Figure 4-4 shows the assembled active-low latch.

If you compare the schematic diagrams between these two projects, you’ll see that there are only these two differences between them:

• Gates: The active-high circuit uses a 4001 IC, which contains NOR gates, while the active-low uses a 4011 IC, which contains NAND gates.
• Resistor and switch positions: The positions of R1 and R2 and SW1 and SW2 are reversed. In the active-high circuit, the resistors connect the two gate inputs to ground and the switches short the gate inputs to . In the active-low circuit, the resistors connect the gate inputs to and the switches short the gate inputs to ground.

Both of these circuits use simple push-button switches to provide the trigger inputs. However, you can easily imagine other sources for the trigger pulse. For example in a home alarm system, the input in an active-low latch might come from a window switch that breaks contact when the window is open, and the input may come from a key lock on the alarm system’s control panel.

Here are a few other things you should know about latches before we move on:

• A latch with a SET and RESET input is often called an SR latch. The term RS latch is also used.

• In some cases, you may need a latch in which one of the inputs is active-high and the other is active-low. For example, the key lock in an alarm system described in the previous paragraph may send a HIGH signal rather than a LOW signal when the alarm should be reset. Thus, the input for the alarm latch is active-low, but the RESET input is active high.

  You can easily accomplish that by adding an inverter to one of the inputs, as shown in Figure 4-5. Here, I’ve used NAND gates to create an active-low latch, but I’ve added a NOT gate to invert the RESET input. Thus, the input of this inverter is active-low, and the RESET input is active-high.

Project 38: An Active-High Latch

In this project, you use two of the NOR gates in a 4001 CMOS chip to build an active-high latch. The inputs to this latch are controlled by two breadboard-mounted push buttons, and the outputs are indicated by LEDs.

Project 39: An Active-Low Latch

In this project, you use a two of the NAND gates in a 4011 CMOS chip to build an active-low latch. The inputs to this latch are controlled by two breadboard-mounted push buttons, and the outputs are indicated by LEDs.

Looking at Gated Latches

A gated latch is a latch that has a third input that must be active in order for the SET and RESET inputs to take effect. This third input is sometimes called ENABLE because it enables the operation of the SET and RESET inputs.

The ENABLE input can be connected to a simple switch. Then, when the switch is closed, the SET and RESET inputs are enabled; when the switch is open, any changes in the SET and RESET inputs are ignored.

Alternatively, the ENABLE input can be connected to a clock pulse. For example, you could connect the output of a 555 timer circuit to the ENABLE input. Then, the latch inputs will be operational only when the 555 timer’s output is HIGH. Note that the ENABLE input is often called the CLOCK input. (For more information about 555 timer circuits, refer to Book 3, Chapter 2.)

You can easily add an ENABLE input to a latch by adding a pair of NAND gates as shown in Figure 4-6. Here, the SET and RESET inputs (SR latch) are connected to one input of each of the two NAND gates. The ENABLE input is connected to the other input of each NAND gate. Then, the output from these gates are used as the inputs to the basic latch circuit.

Another common type of gated latch is called a gated D latch, which has just two inputs: DATA and ENABLE. When a HIGH is received at the ENABLE input, the DATA input is copied to the output. Even if the ENABLE input then goes low, the output remains unchanged. The output cannot be changed until the ENABLE input goes high.

To create a gated D latch from a gated SR latch, you simply connect the SET and RESET inputs together through an inverter, as shown in Figure 4-7. Thus, the SET and RESET inputs will always be opposite of one another. When the DATA input is HIGH, the SET input is HIGH and the RESET input is LOW. When the DATA input is LOW, the SET input is LOW and the RESET input is HIGH.

Project 40 shows how to build a gated D latch using two 4011 Quad 2-Input NAND gates. Two 4011 chips are required because the latch requires a total of five gates (four NAND gates and one NOT gate), and each 4011 provides just four gates. In Chapter 2 of this minibook, you learn that you can create a NOT gate from a NAND gate simply by tying the two inputs of the NAND gate together. In this project, you use that technique to create the NOT gate.

Figure 4-8 shows the assembled gated D latch. In this circuit, the ENABLE input push button is on the left side of the breadboard, in columns B through D and the DATA input push button is on the right side of the breadboard, in columns F through G. The Q output is indicated by the LED in H30 and I29 on the breadboard, and the output LED is in A28 and B29.

After you’ve assembled the circuit, you can operate the latch as follows:

• Set the Q output to HIGH. First, press and hold the DATA input button, and then press and release the ENABLE input button to activate the latch. The first LED lights to indicate that the output is HIGH.
• Set the Q output to LOW (which sets the output to HIGH). Just press and release the ENABLE button without pressing the DATA button. The first LED goes out to indicate that the Q output is LOW, and the second LED lights to indicate that the output is HIGH.

Project 40: A Gated D Latch

In this project, you use five NAND gates provided by two 4011 CMOS chips to build a gated D latch. The inputs are controlled by two breadboard-mounted push buttons, and the outputs are indicated by LEDs.

Introducing Flip-Flops

A flip-flop is a special type of gated latch. The difference between a flip-flop and a gated latch is that in a flip-flop, the inputs aren’t enabled merely by the presence of a HIGH signal on the CLOCK input. Instead, the inputs are enabled by the transition of the CLOCK input. Thus, at the moment that the clock input transitions from low to high, the inputs are briefly enabled. Once the clock stabilizes at the HIGH setting, the output state of the flip-flop is latched until the next clock pulse.

Flip-flops are often said to be edge-triggered because it’s the edge of the clock signal that triggers the flip-flop. When used in clock-driven computer circuits, edge-triggering is an important characteristic because it helps circuit designers maintain better control over the timing in circuits that contain hundreds or perhaps thousands of flip-flops.

The circuitry that enables a flip-flop to respond to just the leading edge can be pretty complicated. One of the simplest methods is to feed the clock input into a NAND gate, passing one of the legs through an inverter, as shown in Figure 4-9. This works because in all logic gates, there is a very small delay between the time a signal arrives at the input and the correct signal arrives at the output.

Here I step you through what happens when the clock transitions from LOW to HIGH in Figure 4-9:

1. Initially, the clock input is LOW. The inverter causes the first input to the NAND gate (marked 1 in the figure) to be HIGH, while the second input is LOW. Because the inputs aren’t both HIGH, the output from the NAND gate at point 2 in the figure is HIGH. The second inverter inverts the NAND gate output so the final output from the circuit at point 3 is LOW, just like the clock input.
2. When the clock input goes high, the second input to the NAND gate goes high immediately. However, it takes a few milliseconds for the inverter to respond, so for those few milliseconds, the output from the inverter is still HIGH. Thus, both inputs to the NAND gate are HIGH for a few milliseconds, which causes the output from the NAND gate at point 2 in the figure to go LOW. Then, the second NOT gate inverts the NAND gate output, causing the output at point 3 in the signal to go HIGH for a brief moment.
3. Once the first NOT gate catches up and its output goes LOW (at point 1 in the figure), the NAND gate responds to the LOW and HIGH input by setting its output to HIGH at point 2 in the figure. The second NOT gate then inverts that output at point 3 in the figure.

The net result of the circuit in Figure 4-9 is that long clock pulses are turned into short clock pulses. The duration between the pulses remains the same, but the HIGH part of the pulse becomes much shorter.

Flip-flops are designed for use in circuits that use steady clock pulses. An easy way to provide clock pulses for a flip-flop circuit is to use a 555 timer IC, as described in Book 3, Chapter 2. However, the input source for the CLOCK input of a flip-flop doesn’t have to be an actual clock; it can also be a one-shot input triggered by a push button.

As with latches, there are several different types of flip-flops. The most common are:

• SR flip-flop: Is similar to an SR latch. Besides the CLOCK input, an SR flip-flop has two inputs, labeled SET and RESET. If the SET input is HIGH when the clock is triggered, the Q output goes HIGH. If the RESET input is HIGH when the clock is triggered, the Q output goes LOW.

  Note that in an SR flip-flop, the SET and RESET inputs shouldn’t both be HIGH when the clock is triggered. This is considered an invalid input condition, and the resulting output isn’t predictable if this condition occurs.

• D flip-flop: Has just one input in addition to the CLOCK input. This input is called the DATA input. When the clock is triggered, the Q output is matched to the DATA input. Thus, if the DATA input is HIGH, the Q output goes HIGH, and if the DATA input is LOW, the Q output goes LOW.

  Most D-type flip-flops also include S and R inputs that let you set or reset the flip-flop. Note that the S and R inputs in a D flip-flop ignore the CLOCK input. Thus, if you apply a HIGH to either S or R, the flip-flop will be set or reset immediately, without waiting for a clock pulse.

• JK flip-flop: A common variation of the SR flip-flop. A JK flip-flop has two inputs, labeled J and K. The J input corresponds to the SET input in an SR flip-flop, and the K input corresponds to the RESET input.

  The difference between a JK flip-flop and an SR flip-flop is that in a JK flip-flop, both inputs can be HIGH. When both the J and K inputs are HIGH, the Q output is toggled, which means that the output alternates between HIGH and LOW. For example, if the Q output is HIGH when the clock is triggered and J and K are both HIGH, the Q output is set to LOW. If the clock is triggered again while J and K both remain HIGH, the Q output is set to HIGH again, and so forth, with the Q output alternating from HIGH to LOW at every clock tick.

• T flip-flop: This is simply a JK flip-flop whose output alternates between HIGH and LOW with each clock pulse. Toggles are widely used in logic circuits because they can be combined to form counting circuits that count the number of clock pulses received.

  You can create a T flip-flop from a D flip-flop by connecting the output directly to the D input. Thus, whenever a clock pulse is received, the current state of the Q output is inverted (that’s what the output is) and fed back into the D input. This causes the output to alternate between HIGH and LOW.

  You can also create a T flip-flop from a JK flip-flop simply by hard-wiring both the J and K inputs to HIGH. When both J and K are HIGH, the JK flip-flop acts as a toggle.

Although you can construct your own flip-flop circuits using NAND gates, it’s much easier to use ICs that contain flip-flops. One common example is the 4013 Dual D Flip-Flop. This chip contains two D-type flip-flops in a 14-pin DIP package. The pinouts are listed in Table 4-1.

When you use one of the flip-flops in a 4013 IC, be sure to connect any unused inputs to ground. All unused inputs in CMOS logic chips should be connected to ground, but for simple breadboard circuits, the ground connections aren’t usually required. However, the DATA and CLOCK inputs of a 4013 flip-flop won’t work properly if you don’t ground the SET and RESET inputs.

Project 41 shows how to use a 4013 IC to create a basic D flip-flop. This circuit works much the same as the D-type latch you create in Project 40. However, it requires only one IC rather than two, and the wiring is much simpler. That’s because the engineers who designed the 4013 IC crammed all the wiring between the individual NAND gates in the IC, so you don’t have to wire the gates together on the breadboard. Instead, all you have to do is hook up the inputs and the outputs and watch the circuit work. Figure 4-10 shows the assembled circuit.

Project 41: A D Flip-Flop

In this project, you build a circuit that demonstrates the operation of a D flip-flop. This circuit uses one of the two flip-flops on a 4013 Dual D Flip-Flop IC. The Data and Clock inputs are controlled via breadboard-mounted push buttons, and the output is connected to an LED. The Q output isn’t connected.

Steps

1. Insert the 4013 IC.

   Pin 1 should be in E10.

2. Insert resistors R1, R2, and R3.

   : E20 to F20

   : E6 to F6

   : E8 to F8

3. Insert LED1.

   Cathode (short lead): Ground bus

   Anode (long lead): J8

4. Insert SW1.

   The pins should be inserted in B20, D20, B22, and D22 such that the switch opens and closes across rows 20 and 22.

5. Insert SW2.

   The pins should be inserted in B4, D4, B6, and D6 such that the switch opens and closes across rows 4 and 6.

6. Insert the jumper wires.

   1: Positive bus to A3

   2: Positive bus to A4

   3: Positive bus to A22

   4: Ground bus to J6

   5: Ground bus to J18

   6: Ground bus to J20

   7: E3 to F3

   8: E18 to F18

   9: A6 to A12

   10: A14 to A20

   11: B13 to B18

   12: C15 to C18

   13: D8 to D10

   14: D16 to D18

   15: G3 to G10

7. Connect the batteries.

   Red lead: Positive bus

   Black lead: Ground bus

Project 42 shows how to build a T flip-flop in which each press of a button causes an output LED to alternate between on and off. For this project, the output from the flip-flop is connected to the DATA input. Then, each time the Clock input goes HIGH, the inverted output from the output is fed into the DATA input. This causes the Q output to invert. Figure 4-11 shows the assembled circuit.

Project 42: A Toggle Flip-Flop

In this project, you build a toggle flip-flop using a 4013 Dual D Flip-Flop IC. The clock input is connected to a breadboard-mounted push button, and the output is connected to an LED. The Q output connected to the DATA input, which causes the Q output to invert at each clock pulse.

Debouncing a Clock Input

When you use a mechanical switch to trigger the clock input of a flip-flop, the switch will very likely have some mechanical bounce. This bounce happens when the switch contacts don’t close completely cleanly; instead, the contacts bounce a little bit when they first touch each other. Even though these bounces are usually just a few milliseconds apart, they can end up confusing the flip-flop, as it thinks that each bounce of the switch contacts is actually a separate press of the button. So instead of just turning the LED attached to the Q output from off to on, a single press of the button might turn it from off to on, and then back off, then on, then off again, and so on until the switch settles down into its fully closed position.

There are several different ways you can debounce a mechanical switch — that is, eliminate the bounce effect. The easiest is to connect the mechanical switch to a one-shot timer circuit that uses an RC network to create a very short time interval such as 10 or 20 ms. Though short, this interval is enough to eliminate the negative bouncing effect.

For more information about how to build a one-shot circuit using a 555 timer IC, refer to Chapter 2 of Book 3.