14.2.1 Electrical Switch Control

Ethernet switches are the most representative and widely used switches among electrical switches [1]. An Ethernet switch generally consists of a certain number of input and output ports, memory or buffer, microprocessors, and the switching hardware [2]. According to the ISO/OSI model, an Ethernet switch is a link layer device and implements the function of the message receiving and forwarding related to the MAC addresses and certain scheduling algorithms. In addition to avoiding packet collisions, the switch is also employed as a flow controller by sending queue status back to the transmitter to suspend the packet transmission.

Flow characteristics and the topology of network around the switch are two vital factors for the performance of an Ethernet switch. In a traditional Ethernet network, a switch dynamically learns the topology of the adjacency network and constructs a mapping table. The dynamic mapping table and the packets schedule are implemented by exploiting algorithms which can decrease the processing latency and increase the performance of switch. Therefore, to control the switch, the design of the switching technology should be based on the application of transmitting packets to minimize the latency of transmission and optimize system performance.

In order to ensure the stability and robustness of the real‐time control system, the most important control performance indicators can be characterized by the following three parameters: the maximum allowable transmission time, the sampling rate, and the richness of control data. The maximum allowable transmission time is a key factor for the stability of the control system. If the packet transmission time is larger than the maximum allowable transmission time, the performance of the entire system will be degraded, and a massive or possibly unbounded output will be generated. The sampling rate is the frequency at which the sensing device of the control system collects data. The value of the sampling rate depends on the performance of the processing unit and the communication medium. The abundance of control data directly determines the resolution of sampling and transmission data. The richness of the control data is determined by the quantizable packet size in bits.

In a real‐time network, when a node transmits control data from a transmitter to a receiver or from a control to an actuator, it will send a request packet containing the source and destination node MAC and IP addresses and the control parameter sets to the switch. The feasibility of scheduling request transmission is then calculated based on the earliest deadline priority scheduling algorithm. When the transmission request is not feasible, the switch will recommend that the transmitting node adjust the transmission rate according to the active queue control. In addition, the switch will send a packet with an acknowledgement or notify the transmitter.

The earliest deadline first (EDF) algorithm is employed as the scheduling algorithm for all incoming packages, which is a dynamic priority scheduling algorithm [3]. A switch scheduler exploiting the EDF algorithm always forwards the package whose absolute deadline is the earliest. Then package priorities are not fixed but change depending on the closeness of their deadline. The schedulable condition is checked by computing the total utilization of the requested packages. When receiving a request package, the switch calculates the total utilization of all the request packages. If the schedule is feasible, the switch acknowledges the transmitter with network schedule parameters. If the schedule is not feasible, the switch sends out a set of recommended control parameters for the request node. These control parameters are suggested based on the status of switch queue and the active queue control scheme. When the requesting network traffic is larger than the switch capacity, a request will not be feasibly scheduled. Under this situation, the switch will adopt the active queue control (AQC) to advise the transmitters of further incoming packages. Otherwise, the network payload will be overloaded and the performance of control will be degraded [3].

In general, the Ethernet switch controller implement a scheduling algorithm for the incoming network traffic by utilizing related switch variables such as queue length and throughput to allocate bandwidth for each connected node. When the network traffic load is low, the switch adopts the EDF algorithm to verify the feasibility of scheduling and transmit the incoming packets. When the network traffic load is too high, the AQC is adopted to allocate the available network bandwidth properly.

14.2.2 Slow Optical Switch Control

Bandwidth is limited by current optoelectronic optical switches being used for signal switching, which require conversion of signals from optical to electronic to process signal, and back to optical for transmitting. In order to eliminate this bottleneck, various approaches have been employed. The optical switch is a device that switches an optical signal from one optical port to another, without having to first convert the optical signal into an electrical signal. Optical switches became important because of the telecommunications industry’s desire to focus on all‐optical networks (AON), meaning total exclusion of electronics [4, 5].

A slow optical switch is a device that enables signals in optical fibers or integrated optical circuits to be selectively switched from one port to another within milliseconds and microseconds, such as those using moving fibers. Mechanical optical switches are typical switches that rely on the movement of optical fibers or optical components to switch the optical path, such as a mobile optical fiber type, moving the sleeve to move the lens (including mirrors, prisms, and self‐focusing lens) types. The biggest advantage of this kind of optical switch is the low insertion loss and low crosstalk. Its disadvantage is slow which within milliseconds and microseconds and easy to wear, easy to vibration, impact shocks.

One approach to optical switching has been the use of micro‐electrical mechanical system (MEMS) technology to fabricate tiny mirrors that perform the switching function. These tiny mirrors steer optical signals directly, without O/E conversion operation. MEMS optical switch are micrometer‐scale devices that rely on mechanical moving micro‐mirrors to switch the optical signal from input ports to output ports. In general, the core of the MEMS optical switch control is how to fast and stably move micro‐mirrors to satisfy the switching function. Meanwhile, considering the wear of the systems, a considerable number of control mechanisms have been employed.

The structure of MEMS consists of mechanical moving parts controlled by electronics, and hence usually show oscillating transitions between on and off states. This reduces switching speed and reliability, as the switch tends to wear out faster. Application of proper control system design emerges as a solution to these problems. The control system generally has two parts, a feed‐forward portion responsible for reaching proximity to the desired position and a feedback portion responsible for shaping the system dynamics for transient response conditioning [6].

Another approach to optical switching has been the use of Liquid Crystal on Silicon (LCoS) technology to design wavelength‐selective switch (WSS) systems for WDM applications. The LCoS device implement the amplitude, phase, or polarization modulation of the incident light by utilizing the electrically modulated optical properties of liquid crystals (LCs). The LCoS devices provided in the commercial market are reflective and composed of pixels coated with aluminum mirrors on the silicon backplane. The applied voltage on each pixel is individually controlled by the integrated driving circuitry underneath the aluminum mirrors on the silicon backplane [7].

LCoS is a very versatile switching element, although it is capable of easily switching between multiple ports there is no requirement to lock the spectrum of the switching to any predetermined channel plan. LCoS can be used for its polarization switching capabilities in a similar fashion to LC switches but the true flexibility of LCoS is unleashed by employing the LCoS in a variable phase spatial light modulator (SLM) which can be used to create from an incoming phase front the required outgoing phase front to couple efficiently to a configured output port selected by a applying a simple mathematical relationship [8–10].

It is simplest to consider the LCOS as being divided into a switching plane and a wavelength dispersive plane. The wavelengths of the optical spectrum are dispersed along the wavelength axis so that each wavelength can be operated upon separately and directed to the desired port. As such it is straightforward to have contiguous switching elements of variable width without any in‐band artifacts or glitches that could be detrimental to cascaded performance without sacrificing the spectral resolution of the optical switch. LCOS is now a mature wavelength switching technology which has proven itself in current applications that do not fully utilize the full flexibility such as 50 GHz multiport WSS [11].

14.2.3 Fast Optical Switch Control

Compare to slow optical switch, a fast optical switch is a device that enables signals in optical fibers or integrated optical circuits to be selectively switched from one circuit to another within nanoseconds and sub‐nanoseconds. Although lowering the time order of magnitude, it brings much challenges such as fast reconfiguration, precise time synchronization, fast clock data recovery, and scalability. Mach–Zehnder interferometers based optical switch, semiconductor optical amplifier based optical switch and AWGRs with tunable lasers are three typical fast optical switches.

The Mach–Zehnder interferometer (MZI) based switch consists of two 3 dB couplers, connected by two interferometer arms and shown in Figure 14.1. By controlling the effective refractive index of one of the arms, the phase difference at the beginning of the coupler can be changed, such that the light switches from one output port to the other. This switch has the advantage that the phase shifting part and the mode coupling part are separated, such that both can be optimized separately. Photonic switch networks constructed with MZI as switching elements (SE) can achieve nanosecond switching speed and has been demonstrated to scale up to 32‐by‐32 fabric port count [12]. Further scalability of the silicon integrated switch fabrics is limited by insertion loss and switching crosstalk [13].

SOA is an active optoelectronic device with optical gain similar in structure to the semiconductor laser. The SOA is of small size and electrically pumped. It can be potentially less expensive than the EDFA and can be integrated with semiconductor lasers, modulators, etc. With the increase of the intensity of the current injected into the device, when the number of particle inversion in the SOA reaches a certain degree, the optical gain begins to appear in the SOA, and the injection current corresponding to the transparent medium is the threshold current of the SOA. Beyond this threshold, SOA emerges the light amplification capabilities. When the SOA is turned on, the input optical signal passes through the device and the optical signal power is amplified. After the SOA is closed, the input optical signal is absorbed by the SOA. According to the wavelength and input port of the input optical signal, the switching state of the corresponding SOA can be adjusted and different optical signal paths can be selected to achieve wavelength switching. The combination of amplification in the on‐state and absorption in the off state makes this device capable of achieving very high extinction ratios. High‐radix switches can be fabricated by integrating SOAs with passive components [14].

Flow control and software‐defined networking (SDN) based control are typical switch control schemes among SOA‐based optical switches. Flow control technique is employed to resolve the packet contentions when multiple optical data packets have the same destination. Once contentions occur, the data packets with higher priority will be forwarded to the destination Top of Racks (ToRs) while the conflicted packets with lower priority will be forwarded to the ToRs with no destination request. This kind of packet forwarding mechanism guarantees that the receivers at each ToR receive a continuous traffic flow at every time slot. SDN‐enabled control and orchestration plane with extended OpenFlow (OF) protocol has been developed and implemented for the prototyped flow‐controlled and clock‐distributed optical data center network. With the abstracted information and translation offered by the OF‐agent, the SDN controller can flexibly slice the optical networks by updating the look‐up table and monitoring the stored statistics of the data plane. Such SDN‐enabled control interface is the key optimizer to implement the SDN control scheme for a programmable optical data center network.

AWGR, which is a passive and lossless optical interconnect element, basically, as shown in Figure 14.2, is a fully‐connected structure [15]. AWGR‐based switching fabric is power‐efficient as the signal is only switched to the desired output via the appropriate wavelength, instead of employing the broadcast‐and‐select mechanism that accompanies excessive power splitting losses. The cyclic wavelength routing characteristic of the AWGR allows different inputs to reach the same output simultaneously by using different wavelengths. Non‐blocking switching from any input port to any output port can easily be achieved by simply tuning the wavelength at each input. The power consumed in tunable wavelength converters (TWC) [16], the loopback shared buffer, and the control plane logic scale linearly with the number of ports, unlike other switches. In contrast to SOA, AWGR is a passive device depending on the control of input and output node. Predefined control and label control are employed to implement AWGR‐based optical switch control.

14.3.1 Scalable Control Plane

The control function is implemented by the switching control mechanism. In a simple end‐to‐end network topology, control plane executing control function can easily implement dual communication with low delay and high bandwidth. However, when the scale of network is expanded exponentially, which means the number of nodes in the network is increased to tens of thousands of nodes, whether the switching controller achieves the previous effect is a huge challenge. The increasing number of controlled nodes increases the burden of the switch, and brings about power consumption increase and blocking problems. One feasible solution to reduce the burden is to cascade or expand the use scale of the switch on the basis of the original structure. Whether original switch control is applicable to the new condition or meets the same QoS requirement are factors to consider in scalable control plane.

On the other hand, the increased nodes require the increasing radix of switch. Under the current existing technology, the radix of SOA of 32‐by‐32 has been achieved, which can support up to 10,000 nodes, but the increase of the insertion loss, which can be attributed to the increase of radix, has affected the design scheme of the switch. The radix of the AWGR is an important consideration in determining the scalability of the interconnect networks. An AWGR‐based switch has the potential ability to implement a high radix for the switch, up to 128 [18]. While high port count silicon photonic AWGRs with 512 ports have been experimentally demonstrated, in‐band crosstalk and the number of wavelengths become challenging. Noting that 32‐port AWGRs are commercially available and that 64‐port AWGRs were demonstrated with < −40 dB crosstalk and ∼6 dB insertion loss, the use of AWGRs with a port count value up to 64 is a viable solution both for passive AWGR interconnection and for active AWGR switches. Therefore, the applicability of the simple model is the first step towards implementation and the feasibility of the large‐scale network should be considered in the design of the controller.

14.3.2 Precise Time Synchronization

In pace with the scalability improvement of the switch structure, the demand for precision in time synchronization necessitates a key factor in the performance of switching [20]. Above all, the significance of precise time synchronization is proposed by the utilization rate of the bandwidth. On the basis of switches, to guarantee the validity of signals, the switch window will remain open before the transmission is completed under control. However, the throughput of the switches is ascertained with the guard bandwidth, in which the time synchronization can connect both switch and the endpoints at an appropriate granularity to increase the bandwidth utilization. Ideally, the permission of the lowest interval can reach the nanosecond in recent researches. Not only this, but the precise time‐slot alignment and the ultrafast control of the pass window based on time synchronization are of paramount importance in the time division multiplexing (TDM) and wavelength division multiplexing (WDM) system etc.

Corresponding to the different scenarios, there are several schemes of precise time synchronization nevertheless contributing various accuracy and precision to the switching process. Moreover, the precision of time synchronization protocol varies from millisecond to sub‐nanosecond in experiments. In a variety of such time synchronization protocols, network time protocol (NTP), the Global Positioning System (GPS), BeiDou Navigation Satellite System (BDS), IEEE 1588, precision time protocol (PTP, IEEE 1588V2), and Datacenter Time Protocol (DTP) are indicated in the order of the average precision elevating in systems. The introduction of techniques mentioned is shown in Table 14.1 with scalability and synchronization precision.

In the paper by Patel et al. [21], the stability of the technology‐based NTP depends on stable data center network (DCN). Imagine with such a scene, the effect of network fluctuations will contribute the disconnection of the client to the clock source server, which results in the loss of capturing reference time. This scheme can merely reach the accuracy of synchronization at the 50 ms level. Moreover, according to the main research in industry, the global navigation satellite system (GNSS) is a feasible scheme to acquire the reference time and clock frequency. Nevertheless, extra receivers of GNSS and cables deploying have increased the cost in a considerable scale. Furthermore, the sub‐microseconds accuracy of PTP implemented with dedicated devices of PTP and specialized cables, dramatically taking an additional cost in the system [22, 23]. The researchers of Cornell University [24] proposed the time synchronization mechanism on the basis of the physical layer, Datacenter Time Protocol (DTP). However, to synchronize the time and frequency, the master and slave will deploy dedicated clock channel and devices on the physical layer, while the complexity of link expanded with the application in datacenters.

With the problems in time synchronization, the researchers also proposed many other protocols to comprise, for example, the enhanced Just‐in‐time protocol [25], which reserves the resources to compensate the optical burst switching (OBS). Despite the challenges for the precise time synchronization, there may be a potential method to implement the accuracy, stability, and scalability simultaneously.

14.3.3 Fast Burst Clock Data Recovery

Before the introduction of the demands based on clock and data recovery (CDR), we will first explain the concept of CDR. While the optical packets are after transmission, the clock of the same frequency is required to recover the data carried on the optical signals in the receiver. However, the simplified method is the distribution of the frequency of the transmitter with an extra cost on the specialized cable. To this end, the economic feasibility of optical transmission is biased toward recovering the clock frequency from the injecting optical signals.

In the switching scenario, according to the research of Clark et al. [26], 97.8% of packets are small packets sized 576 bytes or less. However, compared to the electrical switches, optical switching requires the reconfiguration of the link every time in the instant of the dynamical state of the laser for transmission. The momentary process introduced undesirable burst‐CDR locking time for off‐the‐shelf nanosecond‐optical switches that can make small packets transmit practically. Moreover, the minimum guard‐band for the packets should meet the sum of optical switching time and CDR locked time, which confines the throughput and the bandwidth utilization of the switches. Additionally, the burst signals meet the recovery time sum‐up increasing in repetitive operations, which also reduces the utilization rate for the inducement of long guard‐band, shown in Figure 14.3.

The preamble block consists of some symbols that claim the subsequent block is the valid information. Additionally, the IPG block is the acronym for Inter‐Packet Gap, forbidding jitter and other influences in the packets. Moreover, the fundamental reason for the burst characteristic of optical signals is the lock loss of the phase locked loop (PLL) while there is no signal in the optical channel with a long gap. However, the procedure of CDR will be required, ensuring the optical signal injection. The process of CDR is divided in three parts: frequency recovery, phase recovery, and data recovery. The schemes for a burst‐mode receiver can basically be categorized into three main architectures: PLL‐based burst‐mode CDR (PLL‐based BMCDR), Oversampling‐based burst‐mode CDR (Oversampling‐based BMCDR), and Gated‐Voltage‐Oscillator‐based burst‐mode CDR (GVCO‐based BMCDR). In the experiment of Verbeke et al. [27], a 25 Gb/s all‐digital CDR circuit for burst mode achieved 37.5 ns recovery without the start‐of‐burst signal. Furthermore, in recent research of Zheng et al. [28], a DSP‐assisted 25 Gb/s burst‐mode receiver for 50G‐PON upstream transmission has been validated experimentally with approximately 200 ns recovery time.

However, with the fast CDR demands of both point‐to‐point and multipoint‐to‐point (MP2P) systems, the process of CDR should be implemented in nanoseconds or sub‐nanoseconds to match the development of transmission rates, which brings challenges for system control. Not focusing on the circuit or techniques to reduce the burst‐CDR locking time, in the previously mentioned experiment of [26], a feasible method proposed from the control plane of the system to relieve burst‐CDR locking time has been demonstrated. It exploits the distribution of reference clock in the system and the phase pre‐shifting based on the last value simultaneously to compensate the fluctuation of phase in transmission to achieve the lower CDR‐locking time.

14.3.4 Lack of Optical Buffer

The lack of optical buffer is one of the main architectural differences between electrical switches and optical switches, where the electrical switches employ random access memories (RAM) to buffer data packets that lost contention. Because no effective RAM exists in the optical domain, conflicted packets at the optical switch would be dropped and this results in high packet loss. Despite several approaches having been proposed to overcome this issue, based either on optical fiber delay lines (FDLs), wavelength conversion, or deflection routing, none of them is practical for large‐scale data center networks, due to the fixed buffering time (FDLs), extra hardware deployment (wavelength conversion), and management complexity (deflection routing).

Although there is a lack of optical buffer to overcome the bottleneck, it is the key part of optical packet switching, optical routing, and optical computing. Optical packet switching provides an almost arbitrary fine granularity but faces significant challenges in the processing and buffering of bits at high speeds. The simplest solution to overcome the contention problem is to buffer contending packets, thus exploiting the time domain. This technique is widely used in traditional electronic packet switches, where packets are stored in the switch RAM until the switch is ready to forward them. Electronic RAM is cheap and fast. On the contrary, photons are bosons, and they are theoretically impossible to stop without converting them into other forms of energy, so optical RAM does not exist. The only way out is to delay the light signal for a period of time so that it can be processed at high speeds. FDLs are the only way to “buffer” a packet in the optical domain. Contending packets are sent to travel over an additional fiber length and are thus delayed for a specific amount of time [29].

To highlight the scaling problem in large‐scale OPSs, consider an OPS or router with 1000 incoming and outgoing channels, each at a data rate of 40 Gb/s. In electronic routers, the buffering capacity per port is usually equal to around 250 ms of delay per port. At the 40 Gb/s data rate, this corresponds to a buffer capacity of around 10 Gb. If single‐wavelength FDLs were utilized in place of electronics for this buffering, then the total length of fiber needed for buffering all ports in the router would be approximately 40 Gm, or about 150 times the distance from the earth to the moon. Even if we set aside issues of signal distortion by dispersion and the very significant problem of power consumption by the necessary inline amplifiers, these lengths of fiber are quite unrealistic just on the basis of the physical space required to house the delay lines.

Several design ideas for optical buffer are presented here. The first is to increase the transmission distance, which is similar to the optical delay line, the second is to reduce the group speed, and the last is to design the optical buffer according to the specific application scenarios. By the way, fiber‐optic loop and slow light combination is the future of buffer [29, 30].

14.3.5 Reliability

Reliability is a standard concept for evaluating the effectiveness of a network system. Unlike the reliability of optical switching technology, the QoS after long‐time link construction has mainly been investigated. A well‐designed switching control scheme can control the optical switch continuously for a long time with low latency and low packet loss. In order to verify that the reliability requirements are met, it is necessary to carry out long‐term chain building tests in the experimental scenarios when designing the switching control mechanism.

14.4.1 Predefined Control

Predefined control is a control scheme in which data is deployed on the switch path before being transmitted to the switch input node. Fast optical switches based on passive optical device AWGR are widely used due to the interference of insertion loss and crosstalk. An optical switch based on AWGR can realize the design of a high‐radix situation, which can reach 128×128. The switch principle of a passive optical device is fixed by the device, not directly to reconstruct or control switches switching path, so need incoming ports to see predefined data in advance, after the predefined optical data can be carried out in accordance with the scheduled way switch, and finally complete the end‐to‐end communication. Precise time synchronization is the key to implement predefined control. It requires the synchronization of all sub‐clocks, also called the slave. The operation is effective only when all parts of the clock are synchronized in the same time domain. A White Rabbit (WR) switch is an Ethernet switch based on high‐precision clock distribution with performance much better than that of the PTP 1588 synchronization protocol. Generally, predefined control technology is a new control scheme proposed by the device itself, which needs continuous development.

14.4.2 SDN Control

To fulfill the promises of facilitating virtualization and enhancing the network performance by providing simplicity, programmability, and flexibility, SDN is penetrating the optical DCNs. OpenFlow (OF), the core technology of SDN, achieves centralized control of large‐scale network traffic by separating the control plane of network devices from the data plane and makes network management more convenient. After SDN deployment, the connectivity of routers of each node in the network is completely controlled by the upper layer automatically, without manual adjustment, and only corresponding network rules need to be defined in advance. In addition, users are allowed to modify the built‐in protocols of the device according to their needs to achieve better data switch performance.

To elaborate the control scheme, as is shown in Figure 14.4, the OpenDaylight (ODL) and OpenStack platforms are deployed as the base SDN controller and orchestrator, connecting the data plane by means of integrated OF Agents implementing an extended OF protocol. The OF Agents deployed on top of FPGA‐based ToRs and switch controllers are mediation entities between the control plane and data plane. Cooperating with OF protocol, these Agents enable the communications between the southbound interface (SBI) of ODL controller and the Peripheral Component Interconnect Express (PCIE) interfaces of data plane.

Apart from the forwarding control of optical packets, the FPGA‐based switch controllers report the counts of NACK signals indicating packet retransmissions to the SDN controller which, in turn, forwards them to the orchestrator for the full automation of network slicing (NS) deployment, featuring dynamic flow priority assignment and automatic load balancing to decrease the transmission latency and packet loss. To fulfil the promises of facilitating virtualization and enhance the network performance by providing simplicity, programmability, and flexibility, SDN is penetrating optical DCNs. In light of this, an SDN‐enabled control and orchestration plane with extended OF protocol has been developed and implemented for the prototyped flow‐controlled and clock‐distributed optical DCN. With the abstracted information and translation offered by the OF‐agent, the SDN controller can flexibly slice the optical networks by updating the look‐up table and monitoring the stored statistics of the data plane. Such SDN‐enabled control interface is the key enabler to realize the SDN control framework for a programmable optical data center network. By exploiting the nanoseconds forwarding of hardware control and the decoupled SDN control, assessments demonstrate the QoS guaranteed operation for the applications running in the optical switch‐based sliced networks [31, 32].

14.4.3 Label Control

Label control with a packet retransmission mechanism provides a promising solution to address the optical packet contention by pushing the buffer to the edge nodes in the electrical domain. In the fast label control system, each of the bidirectional label channels is a continuous link not only used to send the label requests from ToRs to switch controller and the flow control signals from the switch controller to the ToRs, but also used to distribute the clock from the switch controller to all the connected ToRs. In this way, all the transceivers of the ToRs are clocked with the same frequency and thereby the receivers eliminate the time‐consuming clock frequency recovery step. Moreover, to guarantee that the CDR circuits are active, the switch controller, which has the full vision of the traffic from the ToRs, exploits the multicast capability of the optical switch to forward packets to the non‐destined ToRs to fill the empty slots. It shows that this clock distribution technique achieves a constant 3.1 ns data recovery time regardless of the IPG length and with no deployment of the high‐cost burst‐mode CDR receivers [33].

The bidirectional label channels carrying the label signals and flow control signals are exploited in the nanoseconds optical switch and control system to implement the fast switch control, time allocation, and flow control as well as the clock distribution. To further improve the utilization of the label channels and to provision differentiated quality of service (QoS), the label channels can be utilized to deliver more useful information apart from the destination request and priority. For instance, one lower speed (that means lower cost) label channel can be used to carry several (current and following) destination requests for data packets from multiple data channels in an asynchronous mode. This could boost the label processing capability at the switch controller since the controller knows more destination requests. This could also improve the transmission throughput since the coming packets can be transmitted immediately, and do not need to follow the synchronous time slot. Moreover, heterogeneous requests can be delivered by the label signals to the switch controller to enable the dynamic QoS provisioning for data center applications with different requirements [34].

To elaborate the control scheme, as is shown in Figure 14.5, the LIONS [35, 36] consists of an AWGR, tunable wavelength converters (TWCs), an electrical control plane (CP), electrical loopback buffers, label extractors (LEs), and fiber delay lines. Between each terminal node and the switch, there is an optical channel adapter that serves as the media interface [37]. In general, the AWGR‐based switching fabric can easily realize the output queue, provided that a 1:N optical DEMUX with N receivers is available at each AWGR output. However, N receivers at each output may not be practical or scalable since this requires a total of N² receivers for the whole system.

When the optical labels arrive at the label extractor (LE), the optical labels are separated from the optical payloads by it and then transmitted to the control plane. The control plane is an electrical processing plane. After the optical to electrical (O‐E) conversion, the converted labels from the optical label packet first enter the label processor. The label processor has the preamble detector that implements the pre‐process operation of the inputs. Once the detector detects a valid input, the label processor will start to record the label contents which contains destination address and packet length following the preamble. The label processor then maps the destination address to the desired output port, and sends a request to the proper arbiter for contention resolution. After the arbiter processing, the control plane generates control signals for TWCs, setting their outputs to the proper wavelengths. For the winning inputs, the control plane assigns wavelengths that enable them to send packets to the desired AWGR output, while for inputs that do not get grants, the control plane assigns wavelengths that force them to send packets to the AWGR output connecting with the loopback shared buffer. While the control plane receives the label and makes the decision, the corresponding packet payload travels through the fixed length fiber delay line (FDL) to compensate for the control plane latency. The packets arrive at the inputs of TWCs after the TWCs set their output to the proper wavelengths. The control plane latency is measured as the time between the first bit of the optical label arrives at the O‐E converter and the TWC finishes the output wavelength tuning. Since the arbiter can distribute the TWC control signals in the same cycle for the requests that arrive on the same arbitration cycle, the control latency is identical for any packet arriving at any input [38, 39].

As shown in Figure 14.6, the SOA‐based FOS prototype includes an FPGA‐based switch controller and a switch fabric [40]. The switch fabric is a wavelength and space switch based on strictly non‐blocking architecture. The switch fabric consists of N identical modules and each of them handles the packets from the corresponding TORs. The label channels carry the packet destination and are processed by the switch control of each module. Meanwhile, the optical packets are fed into the SOA‐based 1×N switch. The switch controllers retrieve the label bits and check possible packets contentions, thereby configuring the 1×N switch to forward the optical packets. Moreover, the switch controllers also generate the ACK/NACK flow control messages, which are sent back to the ToRs to release or to ask for retransmission of the packets in case of contention, respectively.

14.4.4 AI Control

To date, AI control, employed in flow control, topology reconfiguration, and control prediction, is a new‐type control scheme for high‐layer network structure. The high‐layer network control is primarily for virtualization and cloud service. An intelligent engine that is easy to configure and use with high efficiency, combined with diverse domain knowledge and models, is needed for modern data centers to quickly learn and extract targeted valuable information and strategies from the massive amounts of data generated by various applications. The intelligent engine enables the data centers to provide rich platform services and application programming interfaces (APIs) with pre‐integrated machine learning, graphics engine, and search capabilities, as well as artificial intelligence (AI) services and APIs in common fields such as visual, voice, and language processing. These intelligent platforms and general AI/machine learning/deep learning services could work closely with the heterogeneous computing hardware such as graphics processing units (GPUs) and field‐programmable gate arrays (FPGAs) to implement the in‐depth optimization of application performance.