CHAPTER 12

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Some Ham Radio Circuits Related to SDR

There are many amateur radio circuits available today such as those used in software defined radios (SDR). In this chapter we will look into some of these circuits including building blocks that include crystal oscillator circuits, mixers, and simple RF matching circuits.

We will explore circuits published in magazines and books, and also those posted on the web. Because these are DIY (do-it-yourself) type circuits, there may be room for improving performance and reliability, or room to simplify these circuits.

This chapter will cover mainly amateur radio receiving circuits so that anyone can build and explore these without having to obtain a license (e.g., Technician, General, or Extra).

However, if you are transmitting ham radio signals you will require an FCC (Federal Communications Commission) license in the United States or an equivalent amateur radio license elsewhere.

Software Defined Radio Circuits

A software defined radio uses a computer to handle “middle and back” portions (intermediate frequency, IF, filter, demodulator/detector, audio filtering, and audio output circuits) of a superheterodyne (superhet) radio. Essentially, a basic superhet radio includes a tuned circuit for the received signal, a mixer circuit to shift down the received signal’s frequency, an intermediate frequency filter and amplifier, and finally a detector (e.g., AM) and audio amplifier. See Figure 12-1.

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FIGURE 12.1   A block diagram of a basic conventional superhet radio.

NOTE: RF mixing means we are in some way multiplying two signals to get a third signal.

As shown in Figure 12-1 the basic superhet radio requires an RF band-pass filter (BPF) to ensure that the RF mixer with the local oscillator provides an IF signal indicative of the tuned RF signal from the antenna. For example, in a standard AM radio, the IF is 455 kHz. This means that the local oscillator’s frequency is 455 kHz above the incoming RF signal. But if there is an RF signal that is 455 kHz above the local oscillator’s frequency, the IF signal will include an undesirable image signal interfering with the desired signal. For example, if the desired station is at 600 kHz, then the local oscillator’s frequency is 600 kHz + 455 kHz = 1055 kHz. The mixer will output a signal at |1055 kHz – 600 kHz| = 455 kHz. However, if the antenna receives a radio station at 1510 kHz, and if the BPF tuned to 600 kHz does not sufficiently attenuate signals at 1510 kHz, then the output of the mixer will have another signal at |1055 kHz – 1510 kHz| = 455 kHz. Thus, the RF band-pass filter should be tuned to the desired station and remove substantially all undesirable RF signals that would be inadvertently mixed down to the intermediate frequency. Fortunately, in most AM radios, there is a sufficiently high Q (e.g., narrow bandwidth) tuned circuit that passes the desired RF signal while substantially attenuating the image signal (e.g., 1510 kHz) that is 455 kHz above the local oscillator frequency (e.g., 1055 kHz). The IF filter and amplifier is usually a ceramic filter or an LC (inductor capacitor) band-pass filter with one or more transistors, or a dedicated IC (e.g., TA2003). The output of the IF filter-amplifier is then connected to a demodulator such as an AM (amplitude modulation) detector (e.g., half-wave rectifier circuit). If the system is an FM radio, the detector will employ a frequency modulation detector (e.g., a quadrature detector, a ratio detector, or a frequency discriminator). The detector is coupled to an audio amplifier that provides an audio signal to an earphone or loudspeaker.

One disadvantage of the traditional superhet radio is that the system blocks are fixed to one type of function. For example, if the incoming RF signals also include Morse Code CW (continuous wave) and single sideband signal (SSB) signals, then the detector system will be complex with multiple demodulation circuits (e.g., product detector with CW filter, product detector with SSB filter, etc.). Although these different types of detectors can be made in hardware, they can be mimicked via a software program in a computer, once signals are digitized through the soundcard. See Figure 12-2.

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FIGURE 12.2   A block diagram of an SDR front-end system with low-pass filters for the IF.

As we can see in Figure 12-2, there are some similarities with the standard superhet radio. There’s still an RF band-pass filter, but now we have twice as many RF mixers, twice as many signals for the local oscillator, and twice as many IF amplifiers and filters. Fortunately, these types of mixers and IF filters (low-pass filters, LPFs) can be implemented with op amps and simple resistor capacitor filters. The reason for having twice as many parts after the RF band-pass filter is so the computer can take the two signals, I OUT and Q OUT, and process them such that any image signal will be cancelled out via the software program installed in the computer (e.g., Winrad). Basically, the local oscillator has an I phase signal (defined as 0 degrees phase reference) and a Q phase signal (90 degrees phase shift from the I phase signal). The outputs of each of these I and Q oscillator signals are fed to separate I and Q RF mixers. From the outputs of the I and Q mixer are frequency translated signals of two low-frequency IF signals that are 90 degrees phase shifted from each other in terms of their carrier signals. Figures 12-3 and 12-4 illustrate this. The two low-pass filters then provide signals whose intermediate frequency is generally within a 20-kHz, 40-kHz, or 96-kHz bandwidth for a computer soundcard.

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FIGURE 12.3   An example RF amplitude modulation signal at a high frequency such as > 1 MHz or more.

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FIGURE 12.4   Examples of two lower intermediate frequency (IF) signals where the carrier signal’s phase of the bottom AM signal is 90 degrees shifted with respect to the top waveform. See center vertical axis as a reference.

Now let’s examine a simple mixer SDR front-end circuit that includes the RF band-pass filter, I and Q analog switch mixers, and low-pass filter amplifiers. We will first start with Figure 12-5, the local oscillator that generates I phase and Q phase carrier signals.

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FIGURE 12.5   A crystal oscillator circuit with flip flops to generate I and Q carrier signals, where Vosc_I is defined as the 0 degrees signal and Vosc_Q is 90 degrees shifted in reference to the Vosc_I signal.

A basic crystal oscillator via IC1E utilizes a logic inverter gate configured as an inverting gain amplifier via negative feedback resistor R1 to establish a DC operating point such that the logic inverter gate IC1E is self-biased in an amplifying region. The value of R1 is chosen to be high resistance, with R1 ≥ 1MΩ so that it will not load down the signal from the crystal Y1 at C5. If R1’s resistance is too small (e.g., < 1000Ω), the circuit may not oscillate due to excess attenuation at pin 11. The oscillator circuit requires a phase lag of about 60 degrees or more from RC filter R8 and C4 so that the crystal Y1 and capacitor C5 form another phase lag circuit of at least 90 degrees (e.g., 90 degrees to 135 degrees). To ensure oscillation, the phase lag from R8 and C4 combined with the phase lag from Y1 and C5 has to be in the order of 180 degrees since the inverter gate “automatically” gives another 180 degrees of shift. With a total phase shift of 360 degrees via the phase shift networks (R8, C4, Y1, C5), an oscillation occurs at IC1E pin 10. The oscillator signal is coupled to a buffer inverter IC1A that drives a binary divider, IC3A, which provides a divide by 2 signal at pin 3 and a divide by 4 signal at pin 4 of the 74HC393 IC. A D flip flop is clocked by the divide by 2 signal (e.g., 7.16MHz) at pin 3 IC3A, which provides one-bit sample-and-hold signals of the divide by 4 signal at pin 2 of the 74HC74, which in turn provides a quarter-cycle or 90 degrees delayed signal of the original divide by 4 signal. See Figure12-6.

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FIGURE 12.6   Top trace is Vosc_I (0 degrees reference) square-wave signal and the bottom trace is Vout_Q (90 degrees), a delayed square-wave signal.

The two oscillator signals, Vosc_I and Vosc_Q, will be used for the I and Q mixers as shown in Figure 12-7 where IC5A and IC5B are square-wave RF mixers.

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FIGURE 12.7   An SDR front-end circuit with input band-pass filter (Cvar1 and L1) amplifier Q1, I and Q mixers (IC5A and IC5B) and low-pass filter amplifiers (R4, C12, IC6A; R5, C13, IC6B).

Vin is from a 50Ω antenna tuned to ~ 3.60 MHz for the 80-meter ham radio band. RF matching network Cvar1, L1, and R13 form an RF matching network for Rin = 50Ω. This RF matching network is a high Q high-pass filter that includes some band-pass filtering around the resonant frequency of about 3.60 MHz. Generally, we want to step up the RF input voltage via Cvar1 and L1 many times. This step-up factor is Q and generally we want Q ≥ 3 so that the subsequent calculation will be accurate for practical purposes (e.g., within 10 percent).

The RF voltage across L1 is basically Q × Vin. So, this RF matching network provides an equivalent step-up transformer effect. For example: Q = XL1/50Ω, for 3.60 MHz = fres and L1 ~ 22 uH, XL1 = 2πfres(L1) so Q = 2π(3.60MHz)(22 uH)/50Ω or Q ~ 10. We can find Cvar1 from fres = 3.60 MHz = Images, which leads to Cvar1 = 1/[L1(3.60 MHz × 2π)2] Cvar1 = 1/[22 uH (3.58MHz × 2π)2] Cvar1 = [1/(1.112)10] farad or Cvar1 = 90 pf. Cvar1 can be a polyvaricon variable capacitor used in AM radios (e.g., two sections, 0–60 pf and 0–140 pf).

To ensure that Rin = 50Ω, R13 is required to “terminate” at L1 so at the resonant frequency of 3.60 MHz, Rin is resistive and at 50Ω. Having Rin = 50 Ω is important so that the antenna’s coaxial cable is properly loaded/terminated to ensure low SWR (standing wave ratio), which means maximum power from the antenna is transferred to the front in circuit at Vin via Cvar1. To calculate R13, you can use the following formulas for Q ≥ 3.

Note that Cvar1 is adjusted for maximum amplitude at transistor Q1’s emitter since L1’s inductance is accurate to about 10 percent to 20 percent.

R13 = Q × XL1 = 10 × 2πfres(L1) = 10 × 2π(3.60MHz)(22 uH), or R13 ~ 5000Ω. When you know Q, another faster way of calculating R13 is to use the following:

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If higher Q is desired, we can raise the L1’s inductance such as L1 = 47 uH, then Q = 23.7. This will lead to having Cvar1 = 42 pf and R13 = (23.7)2 × 50Ω or R13 = 28KΩ. (Note: You can use 27KΩ, which is close enough.)

Note that Q1 does not have infinite input resistance to its base terminal. This input resistance at Q1’s base is roughly β × (R11 || ZL2), which will be in parallel with R13. For an approximation given R11 = 1KΩ and |ZL2| = 2π(3.6 MHz)L2 = 2π(3.6 MHz)330 uH = 7.46KΩ >> 1KΩ. So β × (R11 || ZL2) ~ β(R11) = β(1KΩ). Since β ranges between 50 to 100, the input resistance is about 50KΩ to 100KΩ, which is in parallel with R13. Given R13 in these two examples can be 5KΩ or 28KΩ, a good approximation is just to increase R13 by 20 percent from the calculated value. Thus 5KΩ → 6KΩ (6.2KΩ for a standard resistor value), and 28KΩ → 33.6KΩ (33KΩ or 36KΩ). Thus, slightly increasing R13’s calculated resistance compensates for Q1’s input load resistance.

NOTE: In many instances, the antenna may just be a long wire connected to Vin or Cvar1 directly. Here, the source resistance of the long wire antenna may not be 50Ω, and it is possible that R13 can be removed to maximize gain at the resonant frequency.

Emitter follower Q1 acts as a unity gain amplifier with high input resistance at the base of Q1. With L1 providing a 0-volt Q1 DC base bias voltage, Q1’s emitter DC voltage is –0.7 volt since VBEQ1 = +0.7 volt. If you are not sure how the DC voltages for this Q1 emitter follower are calculated, you can build it with L1, Q1, R12, R11 with ± 5-volt supplies and measure the emitter voltage with a voltmeter with the negative test lead connected to ground.

The DC collector current is set by R11, ICQ1 ~ (–0.7 v – –5 v)/R11 ~ 4.3 v/1000Ω or ICQ1 = 4.3 mA. However, the DC collector current can be lowered to as low as ~ 2 mA or R11 → 2200Ω, because the input signal will be very small (< 100 mV) and does not require large signal swings at Q1’s emitter. The output of Q1 is fed through a coupling capacitor C9 into a large value inductor that establishes 0 volt DC at the “Y” inputs of the 74HC4053 analog switches at pin 13 and pin 1 of IC5A and IC5B. Note that series resistor R10 = 47Ω provides some isolation from the “kickback” spikes or glitches that will emanate to the input terminals at pins 13 and 1 due to switching characteristics of the 74HC4053. In general, when using an analog switch as an RF mixer, it is always good to add a small value series resistor to the input so that the amplifier driving it (e.g., Q1 in this case) does not exhibit instability due to the dynamic loading caused by the 74HC4053 input terminals’ glitch signals. Note that there is an alternative to lowering the amount of glitch kickback by choosing a lower capacitance analog switch such as the SD5000 series FET (Note that the SD5000 or SD5200 quad switch has a different pin out than the 74HC4053).

Now let’s take a look at the mixers, IC5A and IC5B, that gate through the RF input signal via Q1’s emitter at a rate of the local oscillator’s frequency. The output of each of the mixers at pins 14 and 15 will contain signals related to RF input signal, an IF signal related to the difference of the frequency of the RF signal and the frequency of the local oscillator, plus other high-frequency signals beyond the frequency of the RF input signal. See Figures 12-8 and 12-9.

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FIGURE 12- 8   Top trace is the RF input AM signal at 3.6 MHz carrier at 1 kHz modulation; bottom trace is a mixer output at IC5A pin 14. Note the two amplitudes are the same.

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FIGURE 12.9   Top trace is the same RF input signal; bottom trace is the low-pass filtered version at R4/C12. Note that the filtered version is about one-third the amplitude of the RF input signal.

With the local oscillator providing 3.58 MHz and with a 3.60 MHz RF input signal, the IF (intermediate frequency) will be |3.60 MHz – 3.58 MHz| = 0.02 MHz or the IF = 20 kHz.

As we can see in Figure 12-9, when all the high-frequency components are filtered out of the amplitude of the IF signal, we see a signal that still retains the type of amplitude modulation envelope of the RF input signal. However, the amplitude is reduced to about one-third. That is the conversion gain = amplitude of the IF signal after filtering (e.g., at R4/C12) divided by the amplitude of the RF input signal at the input of the mixer (e.g., pin 13 of IC5A).

Theoretically, for the IC5A/B mixer using Fourier Series (which the reader does not need to know), the conversion gain = (1/π) = 31.847%, which is close to 33 percent or one-third.

Amplifiers U6A and U6B are non-inverting gain amplifiers each with a gain of (1 + 47K/1K) or a gain of 48. The total conversion gain from the input of the mixer at L2 or pins 13 and 1 of IC5A/B to the output of either U6A or U6B is then (1/π) × 48 = 15.2.

NOTE: The op amp chosen in this example is the OPA2134, which has an 8 MHz gain bandwidth product. So, for a gain of 48, the resulting bandwidth will be 8 MHz/48 ~ 166 kHz, which is sufficient for an audio sound card that accepts a 96 kHz analog input bandwidth using a 192-kHz sampling rate.

Some Troubleshooting Tips Concerning Figure 12-5 and Figure 12-7

1.   Check wiring on the pin outs for all the ICs. If an IC is loaded in reverse, you may burn it out because the power and ground pins are at pins 14 and 7 or at pins 16 and 8. Reversing the IC will supply positive voltage to the ground pin and ground the + power pin, which will damage the chip. If this happens, shut off the power and carefully remove the chip and put in a new one with the correct orientation. It generally helps to use IC sockets instead of soldering the chip directly into the circuit board.

2.   Confirm that the power supplies +5 volts and –5 volts are at the appropriate pins for IC5, IC6, the collector of Q1, and emitter resistor R11. And confirm +5 volts on the power pins of IC1, IC3, and IC4. Also, with an ohm meter, confirm the ground terminal pins for IC1, IC3, IC4, and IC5. Also, make sure that the power supply decoupling capacitors C10, C14, C15, and C16 are each located near (within half an inch of) the power pins to the ICs. Confirm that these decoupling caps are making continuity to the ICs’ power pins (e.g., pin 14 for a 14-pin chip and pin 16 for a 16-pin chip), and that the other sides of the decoupling caps are connected to ground with short leads. The ground connection of a decoupling capacitor can be made via a ground plane on a printed circuit board or to pin 7 of a 14-pin chip or for a 16-pin chip to pin 8.

3.   For the oscillator board in Figure 12-5, confirm that the crystal oscillator is working with an oscilloscope. Make sure that the oscilloscope is set to a bandwidth of at least 50 MHz bandwidth, otherwise a 14.318-MHz square wave will look too sinusoidal. Confirm a 14.318-MHz sine wave of at least 1 volt peak to peak at pin 11 of IC1E, and an approximate square wave at IC1E pin 10 and IC1A pin 2 of about 5 volts peak to peak also at 14.318MHz. If you see noise at IC1E pin 10, check if R1 (2.2MΩ) is the correct value and that it is connected as shown in Figure 12-5; or try another crystal. Also, check R8 (2200Ω) for the correct resistance, and confirm that C4 and C5 are 22 pf.

4.   Check for a 5-volt peak to peak square wave at IC3A pin 3 that should be one-half the frequency (7.16 MHz) from IC1A pin 2, and confirm that pin 4 of IC3A has a one-quarter frequency (3.58 MHz) square wave at about 5 volts peak to peak. If you see no output, confirm that pin 2 of IC3A is grounded.

5.   With an oscilloscope, check for 90 degrees difference in waveform in Vosc_I at pin 2 of IC4A and Vosc_Q at pin 5 of IC4A. See Figure 12-5. If signal Vosc_Q is not a 90-degree phase-shifted square-wave signal relative to Vosc_I, then make sure pin 1, pin 4, and pin 14 of IC4A have +5 volts on all of them, and that pin 7 of IC4A is connected to ground.

6.   At this point if you see very small amplitude waveforms, check to see if any of the output pins such as IC1E pin 10 and IC1A pin 2, IC3A pins 3 and 4, or IC4A pin 5 are shorted to ground or shorted to +5 volts.

7.   For the SDR front-end board in Figure 12-7, we can confirm that the oscillator signals, Vosc_I and Vosc_Q, are at IC5A pin 11 and at IC5A pin 10, respectively.

8.   Connect a 50Ω source resistance generator at 3.60 MHz and 200 mV peak to peak into the Vin terminal at Cvar1. With an oscilloscope probe at the emitter of Q1, confirm at least 1.5 volts peak to peak when Cvar1 is adjusted for maximum amplitude. The gain should be close to 10 ± 20 percent from Vin to the emitter of Q1. You may need to set your scope to “Bandwidth Limit” and AC coupling. Bandwidth Limit reduces the analog signal bandwidth to 20 MHz in most oscilloscopes but allows for viewing cleaner waveforms. Since the frequency is 3.6 MHz, the 20-MHz bandwidth limitation does not interfere in observing waveforms accurately for the SDR front-end circuit. Usually, you can obtain an accurate frequency (< 0.05 percent error) digitally synthesized waveform generator for less than $100.

9.   Confirm sine waveforms at pins 13 and 1 of IC5 that are at least 1.4 volts peak to peak at 3.60 MHz.

10.   Confirm sine waveforms at pin 3 and pin 5 of U6, which should be about one-third the amplitude of the waveform at pins 13 and 1 of IC5. For example, we should see at least 1.4 volts/3 or at least 0.46 volt peak to peak at about 22 kHz at pins 3 and 5 of U6.

11.   The gain of U6 is about 48, so we will get clipping at the outputs pin 1 and pin 7 of U6. Thus, turn down the RF generator from 200 mV peak to peak to 40 mV peak to peak at 3.60 MHz. With a reduction by fivefold, we should get about 0.092 volt peak to peak at pins 3 and 5 of U6. The output of U6 pins 1 and 7 should now have 48 × 0.092 volt peak to peak or 4.4 volts peak to peak sine wave at about 22 kHz. Confirm that V_I and V_Q have a phase difference of about 90 degrees.

12.   If there are problems with getting waveforms in the “ball park,” confirm the component values of R4, R5, C12, C13, and R8, R9, R6, and R7. For example, here’s a test for the bandwidth of the low-pass filters R4/C12 and R5/C13. You can sweep the RF frequency, fRF, of the input RF signal from 3.59 MHz to 3.69 MHz while probing low-pass filter output at R4/C12 and low-pass filter output at R5/C13 to confirm that the frequency response is “flat” from 10 kHz to about 40 kHz and has a –3 dB amplitude point (70.7 percent reference) at 100 kHz. Remember that the resulting frequencies from the down-converted IF (intermediate frequency) signal at the low-pass filters is |fRF – fLO|, where fLO = local oscillator frequency, which is 3.58 MHz = fLO. Actually, the precise local oscillator frequency is 3.579545 MHz ~ 3.58 MHz, so more accurately, the IF = |fRF – 3.579545 MHz|.

A Common Sample-and-Hold RF Mixer Circuit

The switch mode RF mixer shown in Figure 12-7 has the advantage that it does not load the input signal much because of the series resistors in the low-pass filter circuits, R4 and R5 (both 3000Ω), which can be made larger for less loading if needed. For example, if the same bandwidth is required, we can just keep the same RC time constant, which is R4 × C12 or 3000Ω × 470 pf = 1.41 μsec. So, for instance, we can have R4 = R5 → 10KΩ and C12 = C13 → 140 pf. This way, the loading at the input terminals pins 13 and 1 of IC5A/B will be 10KΩ, worst case. Again, see Figure 12-7. The IC5A/B mixer can be made to switch very fast if other analog switches are used such as the SD5000 quad FET (Field Effect Transistor) or if two FST3253 ICs are used. Note that neither SD5000 nor the FST3253 devices are pin for pin compatible with the 74HC4053 chip.

However, the conversion gain of the IC5A/B in Figure 12-7 is “lossy” because it has about a 32 percent conversion gain (see Figures 12-8 and 12-9). If the RF mixer is a sample-and-hold circuit where the sampling time is relatively small, such as ≤ 25% × (1/fLO), then the conversion gain goes up to ≥ 80 percent. See Figure 12-10. In this section we will explore the Tayloe RF Mixer, which is based on sample-and-hold circuits.

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FIGURE 12.10   A simple sample-and-hold circuit; note that the sampling pulse < 50 percent duty cycle.

A simple sample-and-hold circuit is modeled by a finite source resistance, Rsource, such as a 50Ω source from Vin. However, Rsource should also include in series the ON resistance of the analog switch. For example, if Vin has a 50Ω source resistance (such as from a 50Ω antenna) and U1B, has an ON resistance of 20Ω, then Rsource = 50Ω + 20Ω = 70Ω. As we will find out soon Rsource plays an important part in terms of using an analog switch as an RF mixer. The basic operation of the sample-and-hold circuit is when V_LO’s signal is logic high, the analog switch closes and connects for a short duration signal from Vin through Rsource to charge up capacitor C1. When V_LO goes to logic low, the analog switch becomes an open circuit, which disconnects Vin and Rsource from C1. Then capacitor C1 retains the charge and provides a constant voltage during the logic low state from V_LO. See Figure 12-11.

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FIGURE 12.11   An example output signal from a sample-and-hold circuit on the bottom trace versus the input signal on the top trace. The stair-step waveform (bottom trace) from the sample-and-hold circuit maintains the same voltage until the next sampling pulse comes along.

See Figure 12-12 for magnified view of the stair step waveform.

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FIGURE 12.12   A closer look and the sample-and-hold waveform with input signal at the top trace and the sampled-and-held waveform on the bottom trace.

Note that frequency of the local oscillator or V_LO is close to the frequency of Vin, the RF input signal. The output at Vout is then an IF signal that has a low frequency due to |fRF – fLO| = IF and fRF almost equal to fLO. For example, we want |fRF – fLO| < 100 kHz so that the IF signal at Vout can be sent to a sound card in a computer to run an SDR program. If we are trying to down-convert an 80-meter ham radio RF input signal frequency fRF = 3.800 MHz, the local oscillator signal, V_LO, can have a frequency of fLO = 3.810 MHz such that: |fRF – fLO| = IF = |3.800 MHz – 3.810 MHz| = |–0.01 MHz| = 0.01 MHz or the IF = 10 kHz.

In general, the sampling pulse (high logic state duration) should be << 50 percent duty cycle. That is, if you have a 1-MHz sampling frequency, the period is 1 μsecond (μsecond = μsec). The duty cycle is the “ON” time divided by the period. In this example, it will be ON time/1 μsec. Normally, you would like to have the ON time as short a duration as possible. In sampling theory the ON time duration → 0 μsec, but this is not practical because with Rsource in series with sampling capacitor C1, the capacitor C1 in Figure 12-10 cannot charge up instantaneously. So, we need to first define what the duty cycle will be. Then second, determine what we need for a good C1 capacitance value to use given that Rsource is known. To get a feel of the effects of too much capacitance in C1 see Figure 12-13, which shows examples of pulse responses with “too much capacitance” on the longer RC time constant waveform compared to the shorter RC time constant waveform that provides the final voltage with a small time interval.

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FIGURE 12 -13   With different RC time constants we see that it takes a longer sampling pulse (t) to arrive at the final voltage V0. And ~ V0 is achieved at t1 with a shorter RC time constant when compared to ~V0/2 on the longer RC time constant waveform.

The actual equation for the voltage across the capacitor as the analog switch is closed for the duration a positive going pulse from 0 volts to V0 volts is:

Vout = V0(1 – et/RC)

where V0 = peak to peak amplitude of the pulse and where the pulse starts at 0 volts, t = time duration of the sampling pulse (e.g., time duration of the V_LO in the logic high state), and where R = Rsource and C = C1 as shown in the circuit of Figure 12-10, and where e = 2.71828.

Ideally, we want Vout to have the same value as V0 instantly. But this will not happen due to the finite resistance, Rsource. So, here’s what the charge-up voltage at Vout looks like in terms of RC time constants where “t” is the ON time duration:

Vout = 63% of V0 when t = RC

Vout = 86% of V0 when t = 2RC

Vout = 95% of V0 when t = 3RC

For example, suppose we want to build a sample-and-hold mixer for the 80-meter band around 3.600 kHz, and we want to use a 25 percent duty cycle base on a local oscillator frequency at 3.600 MHz, whose period for one cycle is 1/(3.6 MHz) = 0.277 μsec or 277 nsec (nano seconds). For a 25 percent duty cycle, the logic high “ON” duration will be 25% × (277 nsec) = 69 nsec. If we want to have Vout come up to 95 percent of input value, we have to set the RC time constant to one-third of the “ON” duration or (1/3) (69 nsec) or t' = RC = 23 nsec. This means if Rsource = 50Ω, then C1 = t'/Rsource = (23 nsec)/50Ω or C1 = 463 pf ~ 470 pf. We label this as C180meters = 463 pf. Note: For 86 percent of input value set RC to (1/2) (69 nsec).

But what if we want to receive other ham radio bands up to 20 meters? Then we simply scale C1 accordingly to a smaller value in proportion to C1 for 80 meters.

That is, C120meters = (20 meters/80 meters) C180meters.

Or for 20 meters, C1 = (1/4) 463 pf or C1 = 115 pf ~ 120 pf or 100 pf.

But what this really means also is that you can use the 20 meters C1 value for any lower frequency. For example, if C1 = 100 pf in Figure 12-10 with Rsource = 50Ω, this means for the lower frequencies (e.g., 40 meters, 80 meters, and 160 meters) the pulse duration will be longer and Vout will be greater than 95 percent (but always less than 100 percent).

Now let’s look at the consequence of having too large of a C1 value when we want to measure the IF bandwidth or roll-off. That is what happens when the RF input signal’s frequency starts separating more from the local oscillator frequency. Will the IF signal’s amplitude have the same output voltages at 5 kHz versus 20 kHz or 100 kHz? The answer is no. The larger the C1 capacitance, the poorer the frequency response will be on the higher frequency end of the IF signal. See Table 12-1, where Rsource is 50Ω that represents a “best” case scenario. There are times when the source resistance is much higher, such as when connecting a single “untuned” long wire antenna directly into the RF mixer without an amplifier. Such resistances can be much higher, such as 300Ω or more. Table 12-1 will “stop” at the –3 dB frequency for each C1 value from Figure 12-10. The lowest frequency, 100 Hz, is defined as 100 percent with the 0.01 uf = C1.

The test setup has the local oscillator signal, V_LO, at 3.6000 MHz with a 25 percent duty cycle (69.4 nsec high logic level for a one-cycle period of 277.7 nsec). Vin is a signal at 3.6000 MHz plus the frequencies shown in Table 12-1.

For example, to provide a 1000 Hz IF signal at Vout, the input RF signal is 3.6010 MHz, such that 3.6010 MHz – 3.6000 MHz = 0.001 MHz = 1 kHz.

TABLE 12.1   Comparing Frequency Response of the IF Signal at Vout of Figure 12-10, a Single Sample-and-Hold Circuit with Different Hold Capacitor Values for C1 and with Rsource = 50Ω

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As we can see, there is a penalty in having a large capacitance hold capacitor C1. With the 0.22 μf for C1, the usable bandwidth is about 5 kHz, which is about one-fourth the bandwidth most minimum sampling rate sound cards can do at 44.1 kHz, which provides an analog signal bandwidth of 20 kHz. Reducing the capacitance from 0.22 μf to 0.01 μf is much better and a 90-kHz bandwidth is achieved when Rsource = 50Ω. However, if Rsource > 50Ω, such as 300Ω, then we are back to a reduced bandwidth situation. Also, if we want to listen in on higher frequency signals such as in the 40- or 20-meter ham radio bands, then the high logic level “ON” time reduces accordingly to about 35 nsecs or 17.5 nsecs. Thus, the 0.01 μf value for C1 will start providing some more bandwidth loss due to the shorter sampling intervals.

For RF sample-and-hold mixer circuits, the hold capacitor should be in the range of 47 pf to 1000 pf; this will allow for providing a good IF bandwidth up to 90 kHz or more, which can be taken advantage of with a high-quality sound card with 192 kHz sampling frequency. With higher IF bandwidth, more of the radio band can be tuned with a fixed frequency local oscillator.

In general, when using a software defined radio (SDR) program such as Winrad (or others), the span of tuning across the radio band is related to twice the IF bandwidth. Recall that in Figure 12-2, there are two mixers, one I and one Q. Both mixers will provide the same IF bandwidth, and if the hold capacitor has too much capacitance, then the tuning range within the SDR software program will be restricted.

For example, with C1 = 0.22 μf for each of the sample-and-hold mixers (I and Q), the IF bandwidth is ~ 5 kHz. This means only 2 × 5 kHz or 10 kHz of tuning across the band is possible. If C1 = 0.01 μf for a 90 kHz IF bandwidth, then we get 2 × 90 kHz or 180 kHz of tuning range. This then is eighteen times better than the 5 kHz IF bandwidth.

A Preferred Implementation with Sample-and-Hold Circuits

As have already seen in Table 12-1, using a large-value hold capacitor dramatically reduces the IF bandwidth that hinders tuning range. With all sample-and-hold circuits, an important principle to keep in mind is the hold capacitor such as C1 in Figure 12-10 needs to be connected to a high impedance input amplifier. That is, any (e.g., low to medium) resistive loading (e.g., ≤ 10kΩ) across the hold capacitor (e.g., C1) will discharge the capacitor’s voltage before the next sample pulse and result in a loss of output signal voltage.

In some cases, the type of amplifier used to amplify the capacitance voltage at C1 of Figure 12-10 should be FET or amplifiers with extremely low input bias currents (e.g., ≤ 0.200 nA for JFET op amps). In general, almost any FET op amp will work, such as the LF353, TL082, TLC272, etc., providing you keep track of the gain and IF bandwidth.

For example, if you want a 100-kHz closed loop bandwidth from the op amp non-inverting gain amplifier and the gain bandwidth product is 3 MHz, then the maximum gain you can have is about +30 since +30 × 100 kHz = 3 MHz.

Figure 12-14 shows a preferred way of providing amplification to a sample-and-hold circuit, and Figures 12-15, 12-16, and 12-17 illustrate ways of causing problems to the sample-and-hold circuit that should not be used unless corrected or modified.

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FIGURE 12.14   A preferred way of buffering or amplifying voltage across a hold capacitor to keep the hold capacitor’s voltage at C1 steady until the next sampling pulse arrives via V_LO.

The voltage across C1, Vout, preferably should be amplified or buffered with a high input resistance amplifier (e.g., > 1 MΩ). If an op amp is used, this means that only non-inverting gain amplifier configurations will work. At first look, Figure 12-14 may seem “funny” or incorrect because there is no bias resistor to set the DC bias for the (+) input terminal of the op amp. The reason we can get away from having a bias resistor at the (+) input is that the analog switch, U1B, will transfer a sample of the input voltage to C1, which in turn biases the (+) input terminal.

In Figure 12-14, note that the input signal Vin must have a DC path to a DC voltage source or to ground. The gain of the amplifier is Vout2/Vin = [1 + (R1/R2)]. Generally, the gain is in the order of 10 to 100 in most cases. With higher bandwidths such as having a gain of 100 with an IF bandwidth of 96 kHz, you can choose an op amp (e.g., TLE082) with a gain bandwidth product of ≥ 10 MHz since 100 × 96 kHz equals 9.6 MHz. See the end of this chapter for more on gain bandwidth product.

Alternatively, you can split the gain of 100 by cascading two amplifiers by having each non-inverting gain op amp stage provide a gain of 10. This way, you can get away with an op amp with a gain bandwidth product of about 1 MHz. However, it’s best to be on the safe side and use commonly available op amps such as the TLC272, TL082, or LF353 that have gain bandwidth products of > 2MHz. The penalty for this is adding more op amps, but usually these op amps are less costly than the high-speed versions.

AC bypass capacitor, C2, can be omitted with R1 grounded on the R1/C2 side. However, C2 may be used to avoid amplifying DC voltages. Recall the input signal into the computer for the SDR program typically will be AC coupled into the sound card. If Vin has a DC bias voltage, then the op amp with C2 will just pass the same DC offset voltage to Vout2 without amplifying the DC offset voltage that can cause the op amp to saturate or clip at its output Vout2.

In Figure 12-15, there is no need to include R3 in the circuit, especially if this resistor discharges C1 too quickly. Setting a value such as < 50KΩ (e.g., R3 = 10KΩ or R3 = 1KΩ) will cause the sample-and-hold circuit to have a reduced output voltage at Vout2. If resistor R3 were a higher resistance value in the range of 1MΩ to 10MΩ, then there would generally be a minimal signal amplitude reduction at Vout2, and this change into much higher resistance values will fix the problem. However, you can just remove R3.

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FIGURE 12.15   A non-inverting gain amplifier with a 10kΩ resistor R3 across hold capacitor C1. R3 prevents C1 from doing its job of holding a steady voltage until the next local oscillator sampling pulse arrives. To correct the situation, R3 may be removed.

We now turn our attention to another error with sample-and-hold circuits that are connected to inverting gain amplifiers. One of the most “major” mistakes is to connect the hold capacitor (e.g., C1) to an inverting gain operational amplifier circuit that has a low input resistance. This low input resistance will then discharge the hold capacitor that results in an attenuated output voltage. See Figure 12-16.

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FIGURE 12.16   A sample-and-hold circuit that will definitely not work as planned because the hold capacitor is connected to an inverting gain amplifier that has a low input resistance via R1.

In Figure 12-16, the load resistance as seen by the hold capacitor, C1, is Rin, which is an equivalent resistor that is in parallel to C1. The reason for this is because the (–) or inverting input terminal of the op amp U2A is a virtual ground due to its (+) input terminal (e.g., pin 3) being connected to ground. Typically, R1 will be ≤ 1KΩ (e.g., R1 has a range of 10Ω to 220Ω in some circuits found on the web or Internet). This very low resistance will then cause the hold capacitor C1 to discharge almost fully or substantially before the next sampling pulse arrives in the V_LO signal. Because the IF signal is attenuated at C1 (Vout) due to Rin’s low input resistance of R1, the gain has to be pumped back up. So typically, R1 ~ 10Ω and R2 ~ 5KΩ for a gain of 500. Because of the high gain a required IF bandwidth of up to 96 kHz, the op amp U2A has to be a high-speed op amp with a gain bandwidth product of ≥ 50 MHz. So, a 3 MHz TL082 as shown inFigure 12-13 will not work very well and result in a closed loop bandwidth of 3 MHz/500 = 6 kHz that yields a 6 kHz IF bandwidth.

NOTE: The sampling pulses as shown in Figure 12-16 show about a 25 percent duty cycle. For only Figures 12-16 and 12-17 more conversion gain may be had if V_LO were 50 percent square waves. At this point the hold capacitor, C1, does almost nothing since the low impedance of Rin diverts most of the IF signal current away from C1.

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FIGURE 12.17   A sample-and-hold circuit that will not work as planned because the hold capacitor C1 is connected directly to the inverting input of the op amp that can cause parasitic oscillations from the op amp.

Our next circuit in Figure 12-17 shows another added problem when the input resistor R1 → 0Ω, which can cause an op amp to oscillate due to hold capacitor C1 adding extra phase shift.

By having a hold capacitor, C1, connected directly to the inverting input of the op amp with feedback resistor, R2, an oscillation can occur. The reason is that R2 and C1 form a low-pass filter that causes a phase lag from Vout3 to pin 2, the (–) input terminal. This extra phase shift along with the phase shift of the op amp can then cause a net positive feedback situation, which in turn produces oscillation. Only by “luck” of picking the op amp and having an R2 × C1 time constant that does not have sufficient phase shift is there no oscillation. If other capacitance values for C1 are chosen or if a different op amp is used, then oscillation at Vout3 can occur. In summary, Figure 12-17 represents a circuit “waiting for a problem.”

And of course, the input resistance, Rin, is very low. In general, the |Rin| ~ R2/[a(f)], where a(f) is the open loop gain of the op amp. So even if R2 → 5KΩ, we know that Rin < 5KΩ because a(f) is generally much greater than 1 (e.g., a 50 MHz op amp will still have an open loop gain of 10 at 5MHz, and an open loop gain of 100 at 500 kHz, and an open loop gain of 1000 at 50kHz). For example, if a 50 MHz op amp U2A is used such as an LM4562, and R2 = 10kΩ, and the IF or mix down frequency is 50 kHz:

Rin = R2/(open loop gain at 50 kHz) = 10kΩ/1000 or Rin ~ 10Ω

So again in Figure 12-14, the hold capacitor, C1, cannot hold a constant voltage from one sample pulse to another (e.g., see Figure 12-14 where the hold capacitor loading into infinite or high resistance (e.g. ≥ 1 MΩ) results in a constant voltage before the next sample pulse and a stair step waveform (flat steps) is produced).

A Cool Four-Phase Commutating Mixer

Figure 12-7 showed a simple I and Q mixer for software defined radios (SDRs). We will now look into the terrific Tayloe four-phase RF mixer that can be used for generating I and Q signals for SDRs. First let’s look at a basic configuration. See Figure 12-18.

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FIGURE 12.18   A Tayloe RF mixer that provides I and Q signals.

In some of the most basic configurations, input capacitor C1 (e.g., C1 = 1 μf) serves as an AC short circuit and blocks DC voltages from Vin. However, it is better for having L1 and C1 forming a basic high-pass filter that removes low-frequency interference signals. This high-pass filter may be a broadband filter such as rejecting signals below several hundred kHz, while passing RF signals above 500 kHz. Generally, as with any sampling or switch mode filter, an RF band-pass filter is desirable before the RF mixer to ensure that any out-of-band signal does not down-convert to an interfering IF signal. For example, we can also select values for L1 and C1 as a high Q (e.g., Q ≥3) high-pass filter by having [2πfres (L1)]/50Ω ≥3, where

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and where Vin (e.g., an antenna) has a source resistance of 50Ω.

This mixer operates by sampling and holding the (four) signals between four equally spaced intervals that are one-quarter cycle apart. So, there is a four-position sequence of 0 degrees, 90 degrees, 180 degrees, 270 degrees, and then the sequence repeats over time. For example, in a 160-meter receiver at 1.8000 MHz, the switch control signal, Vsw-control, provides a sampling pulse for each phase at a 1.8000 MHz rate. With an equivalent circuit using four separate switches, Figure 12-19 shows the “ON” time when the multiplexor, MUX gates Vin' to each of the capacitors, C_0, C_90, C_180, and C_270. Figure 12-19 shows that each capacitor is charged via Vin' one at a time and just as one pulse ends, another starts via Vsw_0, Vsw_90, Vsw_180, and Vsw_270. The period of each pulse waveform will still be [1/(1.8000 MHz)] = 0.555 µsec in this example for a frequency of 1.8000 MHz.

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FIGURE 12.19   Timing pulses for four sampling switches. This circuit mimics MUX1 in Figure 12-18.

Now getting back to Figure 12-18, the voltage across each capacitor is connected to an input terminal of a differential amplifier (e.g., DA1 or DA2), which can be implemented with instrumentation amplifiers (e.g., INA163). Ideally, the input resistance to each input (e.g., Rin_0 to Rin_270) is infinite or in the order of ≥ 1MΩ so that the hold capacitors C_0, C_90, C_180, and C_270 do not discharge, causing a drop in voltage before the next sampling pulse comes along.

The output of DA1, Vout_I = k(V_0 – V_180), and the output of DA2, Vout2 = k(V_90 – V_270), where k is the gain of the differential amplifier (or instrumentation amplifier).

Now let’s take a look at a circuit that can be improved as shown in Figure 12-20.

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FIGURE 12.20   An example four-phase RF mixer that can be improved. Capacitors C4 and C6 can cause op amps U3 and U4 to oscillate if R7 = R8 = 0Ω.

Some circuits posted on the web (world wide web) are similar to the one in Figure 12-20. In some cases, R7 = R8 have a range from 0Ω to 220Ω. The circuit will still provide I and Q signals at Vout_I and Vout_Q. However, the amplitude signal levels at V_180 and V_270 will be very small due to the hold capacitors, C4 and C6, being loaded to a low-resistance load via R7 and R8, whereas the two other hold capacitors, C5 and C7, are not loaded at all since these two capacitors are connected to the high resistance non-inverting inputs of U4 and U5.

The frequency bandwidth at V_0 and V_90 will be low, in the order of less than 10 kHz. This is because the hold capacitors (C5 = C7 = 0.27 µf) have large capacitances and form a low-pass filter effect. As for the voltages at V_180 and V_270, we will see that they will produce “unexpected” signals and they will not be the expected phase inversion signals of V_0 and V_90.

The V_0 and V_90 signals are on the non-inverting inputs (pin 3) of both op amps U3 and U4. Since the inverting input terminal voltages must match the non-inverting input voltages, the signal voltages at V_180 and V_270 are “overridden” by V_0 and V_90. And the voltage at the inverting input terminal is like a low-impedance voltage source since the inverting input signal matches the signal at the non-inverting input terminal. Again, see Figure 12-20.

For example, you can think of a voltage follower circuit via the inverting input terminal pin 2 of U3 is driving C4 via low-resistance resistor R7. So, if you look at the signal voltage V_0 at C5, you will see almost the same signal voltage V_180 at C4. Likewise, the V_90 voltage you see at C7 will be approximately the same as the voltage at V_270 at C6. Remember in an op amp circuit with negative feedback, it is the voltage at the non-inverting input terminal (e.g., pin 3) that determines what the voltage will be at the inverting input terminal (e.g., pin 2). That is, the voltages at pin 3 (positive input) and pin 2 (negative input) will be the same.

For example, if we look ahead at Figure 12-23, the signal voltages at C4 and C6 are “washed out” and you will not see the expected inverted phase signals there. In essence, the inverted phase signals V_180 and V_270 are “thrown away” in this circuit. But we can fix this by using an instrumentation op amp (see Figure 12-25) or by using voltage followers (see Figure 12-27) that will amplify each hold capacitor’s (C4, C5, C6, and C7) voltage with high-resistance input terminals.

In terms of troubleshooting this circuit (Figure 12-20), the first place to start is at V_CLK, which is 3 volts to 5 volts peak to peak pulsed waveform such as a square wave signal. At pin3 of U2A and pin 11 of U2B, you should confirm the clock signal. To determine the frequency, you need to know which radio frequencies you want to receive via Vin. V_CLK will have a frequency 4x the incoming RF frequency. For example, if you want to listen in on the 80-meter band around 3.6000 MHz, V_CLK will have a frequency of 4 × 3.6000 MHz or 14.400 MHz. A V_CLK generator may come from a frequency synthesizer chip with crystal oscillator or from a crystal oscillator. If frequency generators are using an LC (inductor capacitor) or RC (resistor capacitor) oscillators, the frequency stability is most likely inadequate. Fortunately, today you can purchase an inexpensive crystal-controlled, two-channel variable frequency signal generator for testing these types of circuits. Again, see Figure 12-20.

For digital counter/divider chips (U2A and U2B) the first thing to check for is that there is +5 volts at the power pin 14, and pin 7 is tied to ground. Then confirm that the preset and reset pins are tied to logic high (e.g., +5 volts). We should see +5 volts at pins 4 and 10 for the preset pins and pins 1 and 13 for the reset pints. Second, confirm the (clock) CLK pins 3 and 11 U2A and U2B are tied together with a pulsed waveform on these pins, that is, in the 3-volt to 5-volt peak to peak range. Next, confirm with a two-channel oscilloscope with U2A pin 6 connected to Channel 1 and pin 9 of U2B to Channel 2 (of the scope), that you see 5-volt peak to peak waveforms that are 90 degrees phase- shifted from each other. Also, these two waveforms, when starting from both signals at 0 volts, should have a sequence of 0, 2, 3, and 1 where pin 6 of U2A is the least significant bit, and pin 9 is the most significant bit. Confirm these two waveforms are at U1 pins 14 and 2 (Figure 12-21). Also note the waveforms are not always clean pulses and you may see some small overshoot or slight ringing, which should not be a problem with logic circuits.

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FIGURE 12.21   Top waveform at pin 14 (A input control line LSB) and bottom waveform at pin 2 (B input control line MSB) of the FST3253 analog switch with a 00, 01, 11, and 10 binary sequence or equivalently a 0, 2, 3, 1 order.

In Figure 12-21 the bottom waveform is one-quarter cycle or 90 degrees shifted from the top waveform. Also, note the repeating binary count sequence from the top waveform for the least significant bit and the bottom waveform for the most significant bit. Two-bit binary numbers equal the following in decimal numbers: 00 binary = 0 in decimal, 01 binary = 1 in decimal, 10 binary = 2 in decimal, and 11 binary = 3 in decimal. A low logic state is 0 in binary, and a high logic state is 1 in binary. The binary count sequence as shown in Figure 12-21 is: 00, 10, 11, 01, 00 . . . Thus, there is a four-state repeating pattern, which translates into 0, 2, 3, 1, 0, . . . When we look at the output pins of U1 for C0, C1, C2, and C3, the numeral following the “Cx” is the state of the address line. So, the sequence of 0, 2, 3, 1 translates to a sequence of C0 first, C2 second, C3 third, and C1 fourth. Because 0 degrees → C0, 90 degrees → C2, 180 degrees → C3, and 270 degrees → C1, we see that the sequence is correct in having 0, 90, 180, and 270 degrees in order.

DC Bias Conditions

Confirm that pin 14 and pin 2 of U1 have the ~ 5-volt peak to peak waveforms as shown in Figure 12-21 when V_CLK is a 5-volt peak to peak square wave signal at 14.400 MHz.

Make sure the connections in U1 are connected as shown in the schematic in Figure 12-20, and that there is +5 volts at pin 16 and that pin 8 is tied to ground. Confirm that there is 2.5 volts DC at pins 7 and 9. If you do not have this, check the R1 and R2 voltage divider circuit and that there is 2.5 volts at C2 as shown in the schematic.

With Vin disconnected for now, measure the DC voltages at the hold capacitors C4, C5, C6, and C7 that should all measure about 2.5 volts within 15 percent. Also measure the DC output voltage at pin 6 of U3 and U4, which should be ~ 2.5 volts DC within 15 percent. Also confirm that the power supply decoupling capacitor, C3, has short leads (less than 0.5 inch) and is very close to pin 16 of U1. Likewise, decoupling capacitor C13 should have short leads and be close to pin 14 of U2A.

Testing Circuit with an RF or Function Generator

Again, with the generator at V_CLK set to 14.4000 MHz, with R7 = R8 = 47Ω and with a 240-mV peak to peak sine wave signal 3.600900 MHz set for 50Ω source resistance for Vin, you should see 900 Hz IF signals at V_0 and V_90 that are 90 degrees apart.

Confirm large amplitude signals (e.g., 6.0 to 8.0 volts peak to peak) at Vout_I and Vout_Q that are the same amplitude and 90 degrees apart. See Figure 12-22 where the amplitudes are ~ 7.3 volts peak to peak.

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FIGURE 12.22   V_I and V_Q output signals (~ 900 Hz) from top and bottom waveforms with ~ 7.3 volts to 7.5 volts peak to peak output, and with a 92-degree phase shift between the two waveforms.

However, does Figure 12-20’s circuit really work the way it should with two of its hold capacitors, C4 and C6, coupled to the low-resistance input terminals via R7 and R8? We should see signal from the hold capacitors C5, C7, C4, and C6 waveforms at 0, 90, 180, and 270 degrees. Just because we see the final result at V_I and V_Q that seems to look correct with about 90 degrees shifted apart in Figure 12-23, it does not mean everything is working correctly. We need to check further back and probe the hold capacitors. See Figure 12-23.

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FIGURE 12.23   Signals from top to bottom at C5, C7, C4, and C6 that we expect the waveforms to be at 0, 90, 180, and 270 degrees. However, this is clearly not the case. Amplitudes are measured at 200 mV/division for all waveforms.

In Figure 12-23 the first and second waveforms should be 90 degrees apart, which is not the case. Also, the amplitudes of all waveforms should be equal, which is not the case.

Clearly, the low resistance loading of C4 and C6 in Figure 12-20 has an effect of “messing” up the amplitudes and phases of the waveforms.

The order of the waveforms can be viewed from the top as the first followed below by the second, followed again below by the third, and the fourth at the bottom.

As a matter of fact, the first and third waveforms just like the second and fourth waveforms should be 180 degrees apart or out of phase, but in fact they are nearly identical in phase.

If we disconnect or remove R7 from C4 and R8 from C6 in Figure 12-20 so that all hold capacitors are either loading into a high-resistance input of the op amps or left open circuit we see the hold capacitors’ waveforms in Figure 12-24, which looks like what we expect.

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FIGURE 12.24   Waveforms from top to bottom of C5, C7, C4, and C6 that show the expected 0-, 90-, 180-, and 270-degree phase shifts, and note all waveforms have the same amplitude.

From Figure 12-24, as long as we keep all hold capacitors, C5, C7, C4, and C6, loading into a very high resistance (e.g., > 1MΩ, or infinite resistance), we will get the correct results. The waveforms shown in Figure 12-24 were done by disconnecting R7 and R8 from capacitors C4 and C6. Note now that the third waveform is 180 degrees phase shifted from the first waveform, and that the fourth waveform is an inverted version (180 degrees) of the second waveform. These inversions are what we expect as shown in the original concept via Figures 12-18 and 12-19.

Improving the “Original Design”

One way to improve the design is to use instrumentation amplifiers. This will provide high-resistance inputs to all the hold capacitors. Note that the 0.27-μf hold capacitors C4, C5, C6, and C7 will still yield only a < 10 kHz bandwidth, but they can be reduced in capacitance to as low as 1000 pf, which will provide close to 100 kHz IF bandwidth. See Figure 12-25 for one implementation that provides a high resistance load to all the hold capacitors.

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FIGURE 12.25   An improved version with instrumentation amplifiers INA163 (U3 and U4) to provide equal high resistance loading to the hold capacitors C4, C5, C6, and C7.

Because we are using instrumentation amplifiers for U3 and U4, the DC voltages at Vout_I and Vout_Q will be close to 0 volts. This is because the DC voltages are about the same at all the hold capacitors C4, C5, C6, and C7. The instrumentation amplifiers will provide a pure subtraction of the DC voltages between V_0 and V_180 and also between V_90 and V_270, which leaves 0 volts at their output terminals (pins 8 and 9 of U3 and U4).

By replacing the LT1115 single op amps in Figure 12-20 with INA163 instrumentation op amps in Figure 12-25, this circuit now works more ideally to what a sample-and-hold RF mixer is capable of. The IF bandwidth at V_0, V_90, V_180, and V_270 are now equal and can be controlled further by changing the capacitances of the hold capacitors, C4, C5, C6, and C7. For example, C4, C5, C6, and C7 can be changed from 0.27 μf to 1000 pf to provide a wider IF bandwidth. We can now compare the phases with the four signals at V_0, V_90, V_180, and V_270. Set the frequency of V_CLK to 14.4000 MHz at 5 volts peak to peak. Set an RF signal generator or function generator to 100 mV peak to peak with a source resistance of 50Ω at 3.600100 MHz (for an IF = 100 Hz). Note that the unloaded signal from the generator will be twice the amplitude, or 200 mV peak to peak when observed connected directly to an oscilloscope oscilloscope with a 1MΩ or 10MΩ input resistance.

Observe with an oscilloscope the 100 Hz IF signals at the hold capacitors, C4, C5, C6, and C7 as shown in Figure 12-25. The voltages, V_0, V_90, V_180, and V_270 should be about 90 percent of the open circuit voltage of the generator. This will then be 90% × 200 mV peak to peak or about 180 mV peak to peak at the hold capacitors.

Note because the IF bandwidth will be low, < 10 kHz, you can use a VFO (variable frequency oscillator, crystal controlled via a synthesizer chip) to tune across the ham radio band. Another way is to use a fixed oscillator for a particular band and tune just portion of it, such as a 96 kHz span in the 80-meter band. If you have a 192 kHz analog to digital converter sound card (which is somewhat expensive), you can tune up to 192 kHz across a ham radio band when C4, C5, C6, and C7 are changed to a lower capacitance such as 1000 pf.

To measure the output signals from the instrumentation amplifiers, reduce the amplitude of the signal generator from 100 mV peak to peak at 50Ω source resistance to 10 mV peak to peak at 50Ω source resistance and at 3.600100 MHz. The open circuit voltage will then be 20 mV peak to peak. Each capacitor voltage will have 90 percent of 20 mV peak to peak or 18 mV peak to peak. However, since the phases of the V_180 and V_270 are inverted phases of the signals from V_0 and V_90, the difference or subtraction of V_0 and V_180 will be twice the signal.

That is V_180 = –V_0, so (V_0 – V_180) = (V_0 – –V_0) = (V_0 + V_0) or (V_0 – V_180) = 2 × V_0.

With V_0 having 18 mV peak to peak, (V_0 – V_180) = 2 × V_0 = 2 × 18 mV peak to peak or (V_0 – V_180) = 36 mV peak to peak.

Note that V_270 = –V_90, and with V_90 = 18 mV peak to peak we have:

(V_90 – V_270) = (V_90 – –V_90) = (V_90 + V_90) = 2 × V_90

or

(V_90 – V_270) = 2 × 18 mV peak to peak or
(V_90 – V_270) = 36 mV peak to peak

The outputs of the instrumentation amplifiers are approximately:

(1 + 6000Ω/R7)(V_0 – V_180) and (1 + 6000Ω/R8)( V_90 – V_270)

In this case, R7 = R8 = 62Ω and 6000Ω/62Ω = 6000/62, so the outputs are:

(1 + 6000/62)(V_0 – V_180) = 97.7(V_0 – V_180), and 97.7(V_90 – V_270)

The expected outputs from the Vout_I = 97.7(V_0 – V_180); Vout_I = 97.7 (36 mV peak to peak) or Vout_I = 3.5 volts peak to peak. Similarly, Vout_Q = 3.5 volts peak to peak.

Because low noise instrumentation amplifiers are not always available, we can slightly modify Figure 12-20’s circuit at least two ways. See Figure 12-26 where the 180- and 270-degree signals are not used so that the op amps use only their high-resistance non-inverting input terminals for amplifying the 0- and 90-degree signals. In Figure 12-26 sample-and-hold capacitors C4 and C6 are not used and can be removed. However, all sample-and-hold capacitors are reduced in capacitance to 1000 pf to provide a wider IF bandwidth out to about 100 kHz.

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FIGURE 12.26   A circuit requiring only the 0- and 90-degree signals via V_0 and V_90.

For Figure 12-26’s circuit, the DC bias conditions should have 2.5 volts at pins 7 and 9 of U1 and also 2.5 volts DC at hold capacitors C5 and C7. Amplifiers U3 and U4 are configured as unity gain voltage followers for DC signals (e.g., for DC analysis, imagine removing the 100 uf capacitors C15 and C16). This means that the DC voltages at pin 6 of U3 and U4 will also be about 2.5 volts since the hold capacitor voltages at C5 and C7 are at 2.5 volts.

The AC gains for U3 and U4 are (1 + R3/R7) or (1 + R4/R8), which in this case is (1 + 4700/47), which leads to (1 + 100) = 101.

With the same test conditions for Figure 12-25’s circuit where V_CLK is at 14.400 MHz and 5 volts peak to peak square wave, the RF or function generator provides Vin = 10 mV peak for 50Ω source resistance with 20 mV peak to peak into a “no load” condition with frequency at 3.600100 MHz. The output amplitudes from Vout_I and Vout_Q should be 20 mV × 90% × 101 or 1.8 volts peak to peak. There should be a 90-degree phase shift on the Vout_Q referenced to Vout_I.

If we utilize all the signal voltages from the hold capacitors as shown in Figure 12-27, then we can about double the gain by adding voltage follower amplifiers U3A and U3B. These two voltage followers provide an equivalent instrumentation amplifier circuit. Via R7 and R8, the added voltage followers drive the inverting input terminals of U4A and U4B.

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FIGURE 12.27   Partial schematic with LM833 dual op amps that have 15-MHz gain bandwidth products, which replace instrumentation amplifiers (e.g., INA163 in Figure 12-25).

Not shown in Figure 12-27 are the connections to pins 7, 9, 14, and 2 of U1, which are connected to the circuits in Figure 12-26. For example, U1 pins 14 and 2 are connected to pins 6 and 9 of the U2A/B circuit in Figure 12-26. Also pins 7 and 9 of U1 in Figure 12-27 will be connected to an input circuit L1 and C1 as shown in Figure 12-26.

In this configuration, dual op amps are used. U3A and U3B are unity gain voltage followers with U4A and U4B as voltage gain amplifiers. The voltage gains for the various AC signals across the hold capacitors are as follows:

Vout_I = (1 + R3/R7) × V_0 + –(R3/R7) × V_180

However, V_180 = –V_0. This leads to:

Vout_I = (1 + R3/R7) × V_0 + –(R3/R7) × –V_0 which leads to: (1 + R3/R7) × V_0 + (R3/R7) × V_0, or Vout_I = [1 + 2(R3/R7)] × V_0

With R3 = 7500Ω and R7 = 150Ω, Vout_I = [1 + 2(7500/150)] × V_0 or Vout_I = (1 + 100) × V_0

Vout_I = 101 × V_0

Vout_Q = (1 + R4/R8) × V_90 + –(R4/R8) × V_2700. But V_270 = –V_90.

Likewise, from the same type of calculations for Vout_I:

Vout_Q = [1 + 2(R4/R8)] × V_90

Vout_Q = 101 × V_90

With a Vin at 10 mV peak to peak signal for 50Ω source resistance (20 mV peak to peak into an open circuit and at 3.600100 MHz with V_CLK being a 14.4000 MHz 5-volt peak to peak square wave, the amplitude of Vout_I = 20 mV × 90% × 101 = 1.8 volts peak to peak.

Similarly, the amplitude of Vout_Q is also 1.8 volts peak to peak and phase shifted 90 degrees referenced to Vout_I with sine waves at 100 Hz.

In terms of the DC voltages at pins 1 and 7 of U4A/B, there are 2.5 volts DC at all the hold capacitors C4, C5, C6, and C7 so we have the following:

U4A pin 1 DC = (1 + R3/R7) × 2.5 v + –(R3/R7) × 2.5 v, which results in: U4A pin 1 DC = 2.5 v + (R3/R7) × 2.5 v + –(R3/R7) × 2.5 v U4A pin 1 DC = 2.5 volts. This is because the (R3/R7) × 2.5 v terms cancel out.

Thus, U4A pin 1 DC = 2.5 volts DC.

And similarly, U4B pin 7 DC = 2.5 volts DC.

Another View of Op Amp Circuits (Where the Inverting Input Drives a Load)

If we examine Figure 12-20’s circuit with C4 and R7 and also look at the waveforms of Figure 12-23, then we would expect the first and third waveforms to be 180 degrees apart, which they are not. Then the question is why? It turns out that the (+) input to a negative feedback amplifier actually provides a low-impedance “output” impedance to the (–) input terminal. The reason is that as long as the output signal of the negative feedback amplifier is not clipping to the power supply rail, then the (–) input’s voltage has to be about the same voltage as the (+) input terminal. The (–) input voltage follows the (+) input’s signal. See Figure 12-28.

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FIGURE 12.28   Examining why the voltages V_0 and V_180 are not as expected as shown in this circuit, which is similar to part of Figure 12-20.

In a non-inverting gain op amp configuration, the input voltage, V_0, is applied to the (+) input terminal. Once this happens, the (–) input terminal must be “equal” to the (+) input. The output voltage at pin 6 U3 adjusts accordingly so that the voltage at the (–) terminal matches the voltage of the (+) terminal. In essence, the signal to the (+) input terminal is the determining factor for “everything.” If you try to apply another voltage (e.g., V_180) to the (–) input via R7 or a series resistor, you will change the output voltage at pin 6, but you will not be able to the change the (–) input’s signal at pin 2. Thus at (–) input pin 2 we have V_0 due to the negative feedback system via feedback resistor R3. Since pin 2 represents a pure voltage source of V_0 also, it provides a voltage to the right side of R7. So, going “backwards,” there is a V_0 voltage via R7 that travels into hold capacitor C4. The signal at C4 via V_0 overpowers the V_180 signal from the analog switch, so that C4 has some version of V_0 instead of V_180, where V_180 is a 180 degrees out-of-phase signal. So, the 180 degrees signal at C4 is “washed” out by the 0 degrees signal at C5. And the C4 signal looks similar in phase to the signal at C5. In fact, this is what we see when we compare the top first signal for C5 to the third signal for C4 in Figure 12-23.

As shown in Figure 12-29, you can make a voltage follower with a series output resistor such as R3 (e.g., 2200Ω) and still provide a low output resistance source of V_0 into the load, R7 and C4. The reason why ~ V_0 has a low resistance in spite of R3 being in series is that the negative feedback terminal (–) input is taken at ~ V_0. The negative feedback system then turns up Vout_I to compensate for loss due to the loading effects of R7 and C4 on R3. The true output resistance at the ~V_0 is approximately R3/a0(f), where a0(f) is the frequency-dependent gain of the open loop gain from U3. For example, if the LT1115 has a 50-MHz gain bandwidth product (GBWP), and we want to know the gain at f = 1 kHz, then a0(f) = a0(1kHz) = GBWP/f = 50 MHz/1kHz or 50,000. Then output resistance at ~V_0 is about R3/50,000 or 2200Ω/50,000 = 0.044Ω < 1Ω. We can see now that ~V_0 has low-output resistance and for all practical purposes, ~V_0 is a voltage drive signal into R7 (“Load”) as shown in Figure 12-29. So that is why in Figure 12-23, C4 has a voltage that looks more like V_0 instead of C4 having a signal that is out of phase (e.g., V_180).

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FIGURE 12- 29   Redrawn Figure 12-28 for clarity as negative feedback amplifier with a series resistance R3 within the negative feedback loop.

Suggested System Approach

In Figures 12-20, 12-25, 12-26, and 12-27, the input signal Vin (e.g., an antenna signal) goes directly to the mixer chip such as an FST3253. A better way is to take the matching network from Figure 12-7 with Cvar1, L1, R13 (e.g., R13 = 5100Ω for a Q ~ 10), R12, Q1, R10, R11, and C9. C9 from Figure 12-7 then feeds the Vin of Figures 12-20, 12-25, 12-26, and 12-27. This matching network steps up the antenna signal like a step-up transformer so that the antenna’s signal level is sufficiently large such that medium low noise op amps such as NE5523 or LM833 can be used. Secondly, the RF matching network via Cvar1 and L1 forms a filter network that reduces out-of-band signals and noise that would be mixed down to the IF signal.

Crystal Oscillators

For many amateur radio circuits a very stable frequency oscillator usually points toward a crystal resonator, although sometimes a ceramic resonator can be used. The order with the best to worst frequency stability for oscillator circuits we have: crystal, ceramic, inductor-capacitor (LC), and lastly resistor–capacitor (RC).

Before we look into some oscillator circuits, let’s take a look at a crystal or ceramic resonator. See Figure 12-30 of different types of crystal and ceramic resonators.

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FIGURE 12.30   Cylindrical crystals or tuning forks on the left side, standard size crystals HC-49/S (shorter version) and HC-49/U (standard “longer” size) in the center, and a ceramic resonator on the right side that includes a three-lead ceramic resonator with built-in 15 pf capacitors.

The models of crystal or ceramic resonators are shown in Figure 12-31 with some circuits.

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FIGURE 12-31(A) TO (D)   Schematic representation of a crystal or ceramic resonator Y1 in (a), a two-gate crystal/resonator oscillator in (b), a single-gate crystal/resonator oscillator in (c), and an oscillator where a three-terminal resonator Y1 includes internal capacitors C2 and C3 in (d).

As shown in Figure 12-31(a), a crystal can be modeled as a series resonant circuit with inductor Ls, capacitor Cs, and series resistor Rs. Many oscillators are configured to use a crystal as a series resonant circuit, as shown in Figures 12-31(b), (c), and (d). Figure 12-31(a) shows the lead body capacitance, Co, which then also forms a parallel resonant circuit with Ls, Cs, and Rs. However, as we will see, most crystal oscillators run in some form of a series resonant mode.

Let’s first take a look at Figure 12-31(b), a two-gate oscillator circuit. Because there are two inverters (U1B and U1C) in series, the net phase shift is 180 degrees plus 180 degrees, or 360 degrees, which is like 0 degrees. Oscillation then occurs when the crystal acts like a band-pass filter with zero degrees phase shift at the resonant or crystal frequency. With this circuit, generally, capacitor C1 has a large value such as 0.01 μf. However, C1 may be selected to a different value to adjust the oscillation frequency. C1 should be larger than 15 pf or a parasitic oscillation may occur.

In Figure 12-31(b), the first inverting gate, U1B has a feedback resistor, R1, that forms a low input resistance at pin 3. The R1 resistance value is chosen to be in the few hundreds to few thousands of ohms depending on the oscillation frequency. U1B via R1 has been configured as an analog inverting gain amplifier with low-resistance input. If the crystal, Y1, is removed, the output of the first inverter with R1 will sit at one-half the supply voltage (e.g., 2.5 volts) for 74AC (up to ~ 30 MHz), HC (up to ~ 10 MHz), and 4000 series CMOS chips (less than 1 MHz). When the crystal Y1 is put back in, it completes a positive feedback loop with the maximum gain at the crystal’s resonant frequency determined by Ls and Cs in Figure 12-31(a) that form a series resonant circuit within the crystal. This series resonant circuit in Y1 provides zero phase shift and maximum gain (amplitude) at resonance. For series mode crystals, the resonant frequency is just the one imprinted on the package. And for crystals with a load capacitance, the series capacitor C1 is set to the load capacitance (e.g., 18 pf) to tune the crystal to the specified frequency. C1 allows “tweaking” the oscillation frequency further even for series mode crystals, which means C1 can have a range of 0.1 uf to about 100 pf. Note that R2 and C2 along with C3 are included in Figure 12-31(b) to prevent parasitic high frequency oscillations.

If we now look at Figure 12-31(c), we see a single inverter gate oscillator configured as an analog inverting amplifier. R1 is generally a very high resistance value ≥ 1MΩ to avoid loading down the oscillation signal at C3. The crystal Y1 is modeled as a series resistor inductor capacitor circuit with C3, the load capacitance of the crystal (e.g., 11 pf to 33 pf) that forms a low-pass filter. This low-pass filter at C3 provides 90 degrees to 135 degrees of phase shift at the resonant frequency. To achieve oscillation, we need 180 degrees of phase shift from the output pin 2 to the input pin 1 of U2A. To add more phase shift, R2 and C2 form an RC low-pass filter. Generally, we set the –3 dB cut-off frequency of the R2-C2 low-pass filter at about one-half the crystal frequency to provide about 60 degrees of phase shift, which will be sufficient for the circuit to oscillate. Typically, R2 is in the range of 470Ω and 2200Ω and C2 has a capacitance value equal to or larger than C3, the crystal’s specified load capacitance. In certain cases, R2 may be increased to about 5kΩ and R1 → 4.7MΩ to 10MΩ for low-frequency (cylindrical) crystals whose frequencies ≤ 200 kHz.

Figure 12-31(d) shows essentially the same circuit as Figure 12-31(c) with a three-terminal ceramic resonator having internal C2 and C3 capacitors. This type of ceramic resonator has three leads including center ground lead. This device is symmetrical, and the two outer leads can be reversed. The center lead stays connected to ground. Typical values for R2 range from 220Ω to about 3300Ω.

NOTE: All crystals are symmetrical or non-polarized, which means that they will perform the same function with their leads reversed.

Types of Crystals

When you purchase crystals, they are separated into two groups. The most common group is crystals that are specified with loading capacitances such as 11 pf to 33 pf. Common loading capacitances are in the 18 pf to 22 pf range. The oscillator shown in Figure 12-31(b) is a series resonant circuit; the loading capacitance is C1. In series with crystal Y1 is C1 to tune the crystal to the specified frequency. For example, in Figure 12-31(b) having U1B and U1C alternatively as 74AHC04, R1 = 3300Ω, R2 = 56Ω, C2 = 10 pf, C3 = 10 pf, and with Y1 = 3.0000 MHz specified with 30 pf loading so C1 = 30pf, the oscillation frequency at pin 6, Vout measured at 2.999971 MHz or about 29 Hz off, which is within the 10-ppm tolerance of the crystal. For a 3-MHz crystal 10 ppm (10 parts per million) yields a tolerance of ±(3 MHz × 10/million), which leads to ±30 Hz.

Other oscillators that make use of the loading capacitance specification are shown in Figures 12-31(c) and 12-31(d). In these two figures, C3 is the loading capacitance value. So, if you have a crystal specified at 18 pf, then C3 = 18 pf. The other capacitor, C2, works with resistor R2 to form a low-pass filter that provides a lagging phase shift of at least 45 degrees but less than 90 degrees. Typically, the phase shift is set to about 60 degrees by having the cut-off frequency, fc = 1/(2πR2C2), set to one-half the crystal frequency. For example, suppose you have a 7 MHz crystal, you can set fc = 3.5 MHz. Now we have to find a C2, but what’s a good value for R2? R2 generally can be in the range of 470Ω to 4700Ω. So, we can just pick R2 = 1000Ω. Then this leads to C2 = 1/(2πR2fc) = 1/(2π1000Ω × 3.5MHz) = 45.5 pf, or C2 ~ 47 pf. Actually, C2 in the range of 47 pf to 68 pf will work fine. In other cases, you can use identical capacitance values for C2 and C3 that equal the specified loading capacitance such as 18 pf or 22 pf while having R2 = 470Ω to 4700Ω.

What if you want more phase shift closer to 90 degrees by lowering the cut-off frequency further to, for example, one-twentieth of the crystal frequency? This will make C2 about 10 × 47 pf or C2 → 470 pf. The oscillator may not oscillate because although the phase shift will be about 87 degrees, the amplitude is attenuated by twentyfold, so only about 5 percent of the signal will enter the crystal Y1 on the right terminal side. The inverter gate U2A configured as an inverting gain amplifier will have to have sufficient gain to make up the attenuation to ensure oscillation. A twentyfold attenuation may have too much loss for the circuit to oscillate.

The second group of crystals is the series resonant type, and there is no loading capacitance specification. Basically, it means if you were to put a series mode crystal, Y1, in Figure 12-31(b) with C1 shorted out or C1 is from 0.01 μf to 0.1 μf (e.g., an AC short-circuit at the oscillation frequency), the oscillator will oscillate at the specified frequency.

Low-Frequency Cylindrical Crystals, “Standard” Crystals, and Ceramic Resonators

In the twenty-first century, most low-frequency crystals at ≤ 200 kHz are the types shown in Figure 12-30 (left side). These provide accurate frequency references for clocks, watches, and other devices. A very popular frequency 32.768 kHz is used in almost all watches. These low frequency crystals may have about a thousand times more loss due to Rs ~ 50kΩ as shown in Figure 12-31(a), whereas the larger standard size HC-49/S and HC-49/U crystals have Rs ~ 50Ω or less. Typically, the load capacitance of the low-frequency smaller cylindrical crystals is in the 11 pf to 22 pf range. Also, they must be driven with lower AC currents when compared to the standard crystals or ceramic resonators. So, you can more easily damage a low-frequency cylindrical crystal if you are not careful.

A low-frequency oscillator such as in Figure 12-31(c) has the low-pass filter section R2 = 4700Ω, C2 = 1000 pf, Y1 = 32.768 kHz to 100 kHz, C3 = 15 pf, and R1 = 4.7MΩ. It is important to raise R1 to 4.7MΩ so that the lossy Rs = 50kΩ inside the cylindrical crystal transfers enough AC signal into the input terminal of the inverter gate, U2A that has been converted to an inverting gain amplifier. Note: If R1= 1MΩ, this resistance value may be too low; and the circuit might not oscillate with cylindrical crystals whose frequencies are ≤ 200 kHz. Given the low oscillation frequency, inverter U2A may be a 74C04 or CD4069 for slower rise/fall times that do not propagate output signal glitches, or you can still use the faster 74HC04 chip.

Standard HC-49 and High-Frequency Cylindrical Crystals

Standard crystals such as HC-49/S and HC-49/U have series resistance, Rs < 100Ω and with that generally as shown in Figure 12-31(c), R2 can be in the 470Ω to 2200Ω range. Again, R1 can be in the 1MΩ to 4.7MΩ range. Typically, R1 = 2.2MΩ. In general, C2 should be at least the loading capacitance, if not more. For example, suppose the crystal frequency is 20 MHz with an 18 pf load capacitance. We should choose a fast inverter gate beyond a 74HC04 such as a 74AC04, 74AHC04, or 74VHC04. C3 will equal the load capacitance of 18 pf, and if R2 = 470Ω, then C2 = 33 pf for an R2/C2 low-pass filter cut-off frequency, fc = 1/(2πR2C2). We set fc = [0.5 × crystal frequency], and this will be 10MHz, half of the crystal’s 20-MHz frequency to provide about 60 degrees of phase shift at 20 MHz.

Note there are fundamental frequency crystals above 200 kHz such as ≥ 3MHz that are available in cylindrical packages like the 32.768 kHz types. However, these cylindrical crystals have the series resistance, Rs, much lower at ≤ 200Ω, which allows them to be used in crystal oscillator circuits with essentially the same R2, C2, and C3 values like the HC-49/S and HC-49/U crystals.

In terms of frequency accuracy, crystals are rated in parts per million (ppm) and can range from 10 ppm to 100 ppm. For good accuracy, you can specify for better (less) than 30 ppm. But just remember the more frequency accuracy you require, the more it may cost. Fortunately, in some cases, you can replace C3 in Figure 12-31(c) with a variable trimmer capacitor (e.g., 5 pf to 35 pf) to adjust the frequency.

Ceramic Resonators

There are generally two types of ceramic resonators, low frequency and higher frequency types. The lower frequency ones resonate below 1.3 MHz with load capacitances in the 100 pf to 560pf. For the resonators above 1.3 MHz, the load capacitances are from 15 pf to 33 pf, which is similar to crystals. Their equivalent series resistance is < 500Ω, so they can be used very much like standard crystals. Ceramic resonators are generally used in situations when the required frequency accuracy is better than an LC or RC oscillator, but does not need to be as accurate as a crystal. Ceramic resonators find their way in almost all remote controls. The frequency tolerance rating is in the order of 0.3 percent to 0.5 percent or 3000 ppm to 5000 ppm. There are some ceramic resonators that have accuracies in the order of 0.1 percent or 1000 ppm, such as the surface mount package Murata CSTNR_GH5L (4.00 MHz to 7.99 MHz), CSTNE_GH5L (8.00MHz to 13.99 MHz), and CSTNE_VH3L (14.00 MHz to 20.00 MHz).

As an example, using instead a 74AHC04 inverter gate in Figure 12-31(c), set R1 = 4.7MΩ, R2 = 2200Ω, and with Y1 = 455 kHz (e.g., Murata CDBLA455KCAY16-B0), set the cut-off frequency fc = 1/(2πR2C2) = 0.5 × 455 kHz = 227.5 kHz. This leads to:

C2 = 1/[2π2200Ω(227.5 kHz)] or C2 = 318 pf ~ 330 pf

Initially set C3 to 330 pf, then try different values from 100 pf to 560 pf to trim the oscillation frequency to 455 kHz using a frequency counter set to the 1MΩ input resistance mode. In this 1MΩ input resistance mode, you can generally use a ×10 scope probe to measure the oscillation frequency if there is sufficient output signal (e.g., > 2 volts peak to peak).

NOTE: Some frequency counters have a 50Ω input resistance mode, which will load down the oscillator’s signal.

If C3 is replaced with a variable capacitor, such as 10 pf to 365 pf air dielectric type or a poly varicon (e.g., a 10 pf to 140 pf or a 10 pf to 270 pf), then this 455-kHz oscillator may be used for product detectors or beat frequency oscillators with variable pitch control.

Finally, Figure 12-31(d) shows a ceramic resonator circuit with built-in capacitors C2 and C3. For some ceramic resonators, the capacitances are 15 pf each. Other ceramic resonators may be up to 47 pf for their internal C2 and C3. As always, you can add parallel capacitor(s) across the internal C2 and/or C3 to adjust the frequency. Or a variable trimmer capacitor such as 5 pf to 35 pf can be placed between the inverter’s input pin and ground. The feedback resistor R1 may be in the 1MΩ to 4.7MΩ range. Again, set the R2 resistance to provide a phase shift with the internal C2. For example, if the ceramic resonator is at 7.2 MHz and the internal C2 and C3 are 15 pf each, R2 can be set as: R2 = 1/[2π15pf(7.2MHz/2)] or R2 = 1474Ω ~ 1500Ω. Again, the cut-off frequency is set at one-half the oscillation frequency of 7.2 MHz, which results in 3.6 MHz (7.2 MHz /2).

We now will look at a one-transistor oscillator with a logic level shifting amplifier that is commonly used when a 0- to 5-volt logic signal is required to drive logic circuits including flip flops, gates, etc. See Figure 12-32.

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FIGURE 12.32   A “typical” one-transistor emitter follower crystal oscillator Q1 with common emitter amplifier Q2 to provide logic level signals for 5 volts peak to peak output.

C5 is generally the crystal’s specified load capacitance such as 18 pf. However, C5 may be replaced with a 5 pf to 35 pf trimmer variable capacitor to adjust the frequency exactly at Vout1 using a frequency counter. If Y1 is a series resonant crystal, C5 = 0.01 uf, which is close to an AC short-circuit at the crystal’s frequency.

So how does the Q1 crystal oscillator work? Q1 is an emitter follower, which means it has a voltage gain of about 1. Yet somehow this circuit must step up the signal voltage at the resonant frequency of the crystal, Y1. At the emitter, you will notice a small value capacitor C1 that forms a very slight low-pass filter effect. That is the signal at Q1’s emitter has a high-frequency roll-off compared to Q1’s base signal. The high-frequency roll-off at the emitter also causes a phase lag with respect to the signal at Q1’s base. In order to get an oscillation going, we need C3 and Y1 to form a high Q high-pass filter that has a peaked amplitude response near the crystal’s frequency. The signal voltage at VY1 or base of Q1 is a signal that is stepped up and has a phase lead referenced to the signal at the emitter of Q1. Crystal Y1 forms an inductive impedance at near the crystal frequency. By near the crystal frequency, we mean within less than 0.1 percent tolerance of the crystal frequency, typically within 0.01 percent or better. For example, if the crystal frequency is 10.000 MHz, the oscillator will provide signal at 10.000 MHz within 1.0 kHz. For example, 1 kHz is 0.01 percent of 10.000 MHz or 100 ppm of 10.000 MHz where ppm = parts per million, and 100/million × 10 million Hz = 1 kHz. Because there is a phase lead due to the crystal and a phase lag via C2, the net phase shift is 0 degrees. And the stepped-up signal via the high Q high-pass filter sustains an oscillation. The actual signal at VY1 (or VE1) is generally not always a sine wave, but instead it can be a distorted waveform. See Figure 12-33.

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FIGURE 12.33   Top trace is a ~ 2-volt peak to peak 28 MHz signal at Q2’s base or VY1; the bottom waveform shows 5 volts peak to peak 28 MHz at Vout1 for Figure 12-32’s circuit.

To troubleshoot this circuit, we first look at the DC conditions, which are easier to measure when the crystal Y1 is removed. The reason for this is when a circuit generates high-frequency AC signals, it causes measurement problems when using a DVM.

A first approximation for Q1’s base voltage is determined by the resistive voltage divider circuit R2 and R3. Since they are equal, the Q1 base DC voltage should be about half of the 5-volt supply voltage, or 2.5 volts DC. The emitter voltage then should be about 0.7 volt below the base voltage. So, the DC emitter voltage of Q1 should be 2.5 volts – 0.7 volt or about 1.8 volts.

In general, there will be some base current from the transistors due to the current gain, β, not being “infinite.” So, the emitter voltage can be as low as 80 percent of the calculated value (e.g., if the emitter voltage is calculated to be 1.8 volts, the base currents may cause the emitter voltage to drop to 1.8 volts × 0.80 or 1.44 volts).

For example, Q1 = 2N3904 and Q2 = 2N3906, where β for each transistor is generally ≥ 100. If by chance Q1’s base voltage is much lower than 2.5 volts, such as 1 volt or less, check to see if the transistor’s collector and emitter leads are installed correctly. If the collector and emitter terminals are reversed, the current gain, β, drops to < 5 and there will be excessive base currents drawn through R2 and R3 that will produce a much lower DC voltage at Q1’s base terminal.

There is a base series resistor, R1 at 47Ω, to prevent parasitic high-frequency oscillations. Without it, or R1 = 0Ω, there can be a “risk” of the oscillator working incorrectly. Also note that L1 and C1 provide localized power supply decoupling so that any power supply glitches or noise does not induce noise into the +5-volt supply line that may be powering other circuits.

With the crystal Y1 reinstalled, you will need an oscilloscope next to troubleshoot this circuit. The values for C2 and C3 depend on the crystal’s frequency. See Table 12-1 for suggested values for Figure 12-32.

TABLE 12.1   Suggested Capacitor Values Based on the Crystal’s Frequency

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NOTE: The crystal Y1 is a fundamental frequency crystal. Be sure to look out for that and not use an overtone frequency crystal.

The signals from the oscillator section coupled to the base of the amplifier, Q2, and the final output signal at Q2’s collector are shown in Figure 12-33. Notice that the output signal is not necessarily always a nice pulse signal.

An alternative circuit using DC feedback with a filter capacitor can also be implemented. The advantage of this circuit is that the oscillator and amplifier can work with a range of voltages without having to change value for Q2’s base biasing resistors. See Figure 12-34.

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FIGURE 12.34   Automatically biasing Q2 for a range of supply voltages via resistors R5 and R6 with feedback filter capacitor C5; use the suggested C2, C3, C4, and R4 values in Table 12-1.

C6 is generally the crystal’s specified load capacitance such as 18 pf. However, C6 may be replaced with a 5 pf to 35 pf trimmer variable capacitor to adjust the frequency exactly at Vout1 using a frequency counter. If Y1 is a series resonant crystal, C6 = 0.01 uf, which is close to an AC short-circuit at the crystal’s frequency.

Q2’s base voltage is biased to the supply voltage –0.7 volt and in this example it is 5 v – 0.7 v or 4.3 volts at Q2’s base. For troubleshooting, we can safely probe the DC voltage at C5, which will have a DC voltage close to 4.3 volts, but likely to be in the range of 0.5 volt to 1.2 volts lower than Q2’s base voltage.

So C5’s DC voltage may be in the range of:

(4.3 volts – 0.5 volt) = 3.8 volts to (4.3 volts – 1.2 volts) = 3.1 volts

Again, you can have Q1 as 2N3904 and Q2 as 2N3906, or equivalent transistors. Generally, these transistors will work fine for oscillation frequencies up to 30 MHz and possibly more.

Of course, we can use a single logic gate inverter chip to make a crystal oscillator with logic-level output. We first encountered this in Figure 12-5, IC1E (74HC04 hex inverter gate) and in Figure 12-31(c). Let’s take another look at these types of oscillators. In Figure 12-35(a) we see a very common single-gate inverter crystal oscillator with a DC bias feedback resistor R1, which is usually between 1MΩ and 4.7MΩ. The reason for the high resistance value is to avoid loading down the signal at C5 via the crystal Y1.

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FIGURE 12.35   (a) A simple and not so reliable version of the one-gate oscillator, (b) a model of the oscillator, and (c) a more reliable design with series resistor R8.

NOTE: The crystal Y1 acts like an inductor and forms a two-pole, low-pass filter with C5 as a voltage divider with the internal equivalent series capacitor in Y1. This two-pole, low-pass filter provides another 90 degrees to 150 degrees of phase lag to combine with R8 and C4 so that there is a total of 180 degrees of phase shift that will enable oscillation. If you want to confirm that Y1 acts like an inductor to enable oscillation, you can substitute an inductor such as 1 μH to 10 μH in place of Y1 in Figure 12-31(c) and you will see that the circuit oscillates.

For example, if R1 has a smaller resistance value such as 470Ω, the oscillation signal at C5 will be attenuated to the point where no oscillation occurs. R1 is to bias the inverter gate to become an inverting gain amplifier with a “reasonable” high input resistance as seen by C5 looking into R1 and IC1A’s input pin 1. For 74ACxx, 74HCxx, 74AHCxx, 74VHCxx, and 4000 series CMOS gates, R1 biases the input pin 1 to one-half the supply voltage such as 2.5 volts DC to provide close to 50 percent duty cycle pulses at output pin 2.

The problem with Figure 12-35(a) is that C4 is used to provide a phase lag of at least 45 degrees (via a –3 dB cut-off frequency) with the internal output resistance of IC1A. However, with faster chips such as the 74HC or 74AC logic families, the internal resistance is so low that it may not provide enough phase lag, and therefore no oscillation occurs. The reason why Figure 12-35(a) works is because the crystal frequency is high enough (e.g., > 14 MHz) such that the gate delay of the inverter IC1A plus the output resistance with C4 has enough phase lag to ensure oscillation. If you try a lower frequency crystal in the ≤1 MHz range, chances are that the reliability of oscillation will be spotty. To examine further the phase lag requirement and role from C4, please see Figure 12-35(b).

A model of the crystal oscillator is shown in Figure 12-35(b) where Rout is the internal output resistance of the logic inverter gate. In the first generation CD4000 series CMOS (Complementary Metal Oxide Silicon) logic chips, Rout was in the order of 500Ω to 2000Ω. Thus, the phase lag network was approximated by a Rout-C4 low-pass filter with a – 3dB cut-off frequency fc = 1/[2π(Rout C4)]. If Rout = 1800Ω and C4 = 22 pf, then fc = 4 MHz for a 5-volt supply. However, if we used a faster logic gate, such as a 74AC04 that has Rout < 10Ω, having C4 at 22 pf will not provide enough phase lag. We would have to either increase C4 to something like 4700 pf that will then cause the output pin to waste power driving C4’s low impedance, or better yet we can reduce power by adding a series resistor R8 as shown in Figure 12-35(c). By having R8 in the 200Ω to 2700Ω range, we can ensure that C4 provides the necessary phase lag for oscillation. In general, the inverter’s input capacitor C5 can be set to the crystal’s loading capacitance, which is specified generally between 11 pf and 39 pf, with common loading capacitances of 18 pf and 22 pf for C5. See Table 12-2 for suggested R8 and C4 values, types of inverter gates, and types of resonators Y1 that can include crystal or ceramic resonators.

TABLE 12.2   Suggested Values for Figure 12-35(c) Using Fundamental Frequency Crystals and Resonators Having Load Capacitance

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Be Aware of Overtone Crystals

For most crystals in the ≤ 30 MHz frequency range, you can buy a fundamental frequency crystal. This means when you build any of the oscillator circuits as shown in Figure 12-35(a) or 12-35(c), the waveform will provide a frequency as marked on the crystal.

However, once you go above 23 MHz, you will find in many cases there is an overlap of fundamental frequency and third overtone frequency crystals. So, you will have to download the data sheet to be sure. Most crystals above 30 MHz will be third overtone versions.

For example, suppose we choose a 60-MHz crystal. It will most likely be a third overtone type, which means its fundamental frequency is 60 MHz/3 or 20 MHz. If you put a third overtone crystal into any of the previous circuits, it may oscillate at 20 MHz instead of the expected 60 MHz. To ensure the correct oscillation frequency, we have to add a band-pass filter at 60 MHz to the oscillator to eliminate the chance that the crystal will oscillate at a lower frequency. See Figure 12-36.

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FIGURE 12.36   A third overtone crystal oscillator with a L1-C4-CVAR1 band-pass filter tuned to the crystal’s frequency to avoid having a one-third oscillation frequency.

For higher frequencies above 30 MHz, the inverter gates should be of the 74AC04, 74AHC04, or 74VHC04 family. The 74HC or 4000 HC logic families top out at around 15 MHz for reliable oscillation. Although there is a slightly faster version called the 74HCU04, it is not nearly as fast as the AC, AHC, or VHC versions.

In Figure 12-36, there is a pre-filter R2 and C7 to prevent high-frequency parasitic oscillations and to prevent excessive output current flowing out of pin 2. Inductor L2 is typically 10 to 20 times the inductance of L1. Inductor L2 forms with L1 an inductive voltage divider circuit that has an equivalent Thevenin series inductance of ~ (L1||L2). Because L2 >> L1, L1||L2 ~ L1. Inductor L1 forms a high Q resonant low-pass filter circuit with (C4 + CVAR1), which provides 90 degrees of phase lag at the resonant frequency at:

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Capacitor C3 provides DC blocking so that IC1A’s output pin 2 does not short to ground in a DC manner via L2 and L1.

For example, if Y1 is a 57.3 MHz = fr, a third overtone crystal, then how do we pick some values for L1 and C4 with CVAR? One way is to pick (C4 + CVAR1) ~ 30 pf. This would mean C4 ~ 15 pf so that CVAR1 with a range of 5 pf to 35 pf will have enough range needed to tune with L1.

L1 = 1/[(C4 + CVAR1) × (2πfr)2] = 1/[(30 pf) × (2π 57.3 MHz)2] or L1 ~ 0.257 μH. We can have L1 = 0.22 μH and 10L1 ≤ L2 ≤ 20L1, so if we choose L2 = 3.3 μH we are fine since the L2 inductance range is 2.2 μH to 4.4μH.

To adjust CVAR1, we need to temporarily add Ctest, a small capacitance value capacitor of 3 pf in series with C5 so that the ×10 oscilloscope’s 11 pf to 22 pf probe capacitance does not load down the signal at C5. This way, we add at most 3 pf in parallel to C5. The oscillator is monitored with oscilloscope ×10 probes at the buffered output pin 4 (IC1A) and at Ctest as shown in Figure 12-36. CVAR1 is adjusted for maximum amplitude at Ctest. When adjusting CVAR1 is done, we can remove Ctest from the oscillator circuit.

An advantage of using logic inverter gates is that they can provide a buffered output (e.g., pin 4 in Figure 12-36) such that when the oscillator signal is driving a load that includes parasitic capacitance to ground (e.g., a board trace or cable capacitance), the frequency does not change.

Gain Bandwidth Product Revisited

There were examples on page 284 of setting the gain of an op amp based on gain bandwidth product (GBWP). In these examples we used the “best” case scenario calculations. For example, a TL082 has a 3 MHz GBWP, which means if you want a 100 kHz closed loop bandwidth (CLBW), the gain is set to 30. However, setting the closed loop gain to 30 (e.g., Figure 12-14 with [(R2 + R1)/R1] = 30) may not be repeatable because the TL082’s 3 MHz GBWP is only typical. A better way is to set the gain lower by 3 fold such as a gain of 10 to get a typical 300 kHz CLBW, which will ensure a 100 kHz minimum bandwidth. The other solution is to set the gain to 30 but use a faster op amp by at least three fold such as a TLE082 that has a 10 MHz GBWP, which will again ensure at least a 100 kHz CLBW.

Summary

We have looked at a few circuits related to amateur radio, but there are obviously many more that can be explored. And there are whole books written just on ham radio circuits.

What’s up ahead in the next chapter will be 555 timer circuits.

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