The instruction set of an architecture varies according to various features present in the architecture. This recipe demonstrates how instruction sets are defined for the target architecture.
Three things are defined in the instruction target description file: operands, an assembly string, and an instruction pattern. The specification contains a list of definitions or outputs and a list of uses or inputs. There can be different operand classes such as the register class, and immediate or more complex register + imm
operands.
Here, a simple add instruction definition is demonstrated. It takes two registers for the input and one register for the output.
SAMPLEInstrInfo.td
in the lib/Target/SAMPLE
folder:$ vi SAMPLEInstrInfo.td
def ADDrr : InstSAMPLE<(outs GRRegs:$dst), (ins GRRegs:$src1, GRRegs:$src2), "add $dst, $src1, $src2", [(set i32:$dst, (add i32:$src1, i32:$src2))]>;
The add
register instruction specifies $dst
as the resultant operand, which belongs to the general register type class; the $src1
and $src2
inputs as two input operands, which also belong to the general register class; and the instruction assembly string as add $dst, $src1, $src2
, which is of the 32-bit integer type.
So, an assembly will be generated for add between two registers, like this:
add r0, r0, r1
This tells us to add the r0
and r1
registers' content and store the result in the r0
register.
X86InstrInfo.td
file located at lib/Target/X86/
18.223.213.238